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[net-next-2.6.git] / arch / cris / arch-v10 / drivers / sync_serial.c
CommitLineData
c974a9e5
JN		 1/*
2 * Simple synchronous serial port driver for ETRAX 100LX.
3 *
4 * Synchronous serial ports are used for continuous streamed data like audio.
5 * The default setting for this driver is compatible with the STA 013 MP3
6 * decoder. The driver can easily be tuned to fit other audio encoder/decoders
7 * and SPI
8 *
9 * Copyright (c) 2001-2008 Axis Communications AB
10 *
11 * Author: Mikael Starvik, Johan Adolfsson
12 *
13 */
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/errno.h>
18#include <linux/major.h>
19#include <linux/sched.h>
c974a9e5
JN		 20#include <linux/interrupt.h>
21#include <linux/poll.h>
22#include <linux/init.h>
0c401df3 23#include <linux/smp_lock.h>
c974a9e5
JN		 24#include <linux/timer.h>
25#include <asm/irq.h>
26#include <asm/dma.h>
27#include <asm/io.h>
556dcee7 28#include <arch/svinto.h>
c974a9e5
JN		 29#include <asm/uaccess.h>
30#include <asm/system.h>
31#include <asm/sync_serial.h>
556dcee7 32#include <arch/io_interface_mux.h>
c974a9e5
JN		 33
34/* The receiver is a bit tricky beacuse of the continuous stream of data.*/
35/* */
36/* Three DMA descriptors are linked together. Each DMA descriptor is */
37/* responsible for port->bufchunk of a common buffer. */
38/* */
39/* +---------------------------------------------+ */
40/* | +----------+ +----------+ +----------+ | */
41/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */
42/* +----------+ +----------+ +----------+ */
43/* | | | */
44/* v v v */
45/* +-------------------------------------+ */
46/* | BUFFER | */
47/* +-------------------------------------+ */
48/* |<- data_avail ->| */
49/* readp writep */
50/* */
51/* If the application keeps up the pace readp will be right after writep.*/
52/* If the application can't keep the pace we have to throw away data. */
53/* The idea is that readp should be ready with the data pointed out by */
54/* Descr[i] when the DMA has filled in Descr[i+1]. */
55/* Otherwise we will discard */
56/* the rest of the data pointed out by Descr1 and set readp to the start */
57/* of Descr2 */
58
59#define SYNC_SERIAL_MAJOR 125
60
61/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
62/* words can be handled */
63#define IN_BUFFER_SIZE 12288
64#define IN_DESCR_SIZE 256
65#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
66#define OUT_BUFFER_SIZE 4096
67
68#define DEFAULT_FRAME_RATE 0
69#define DEFAULT_WORD_RATE 7
70
71/* NOTE: Enabling some debug will likely cause overrun or underrun,
72 * especially if manual mode is use.
73 */
74#define DEBUG(x)
75#define DEBUGREAD(x)
76#define DEBUGWRITE(x)
77#define DEBUGPOLL(x)
78#define DEBUGRXINT(x)
79#define DEBUGTXINT(x)
80
81/* Define some macros to access ETRAX 100 registers */
82#define SETF(var, reg, field, val) \
83 do { \
84 var = (var & ~IO_MASK_(reg##_, field##_)) | \
85 IO_FIELD_(reg##_, field##_, val); \
86 } while (0)
87
88#define SETS(var, reg, field, val) \
89 do { \
90 var = (var & ~IO_MASK_(reg##_, field##_)) | \
91 IO_STATE_(reg##_, field##_, _##val); \
92 } while (0)
93
94struct sync_port {
95 /* Etrax registers and bits*/
96 const volatile unsigned *const status;
97 volatile unsigned *const ctrl_data;
98 volatile unsigned *const output_dma_first;
99 volatile unsigned char *const output_dma_cmd;
100 volatile unsigned char *const output_dma_clr_irq;
101 volatile unsigned *const input_dma_first;
102 volatile unsigned char *const input_dma_cmd;
103 volatile unsigned *const input_dma_descr;
104 /* 8*4 */
105 volatile unsigned char *const input_dma_clr_irq;
106 volatile unsigned *const data_out;
107 const volatile unsigned *const data_in;
108 char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
109 char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
110 char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */
111
112 char output_dma_bit; /* In R_IRQ_MASK2_RD */
113 /* End of fields initialised in array */
114 char started; /* 1 if port has been started */
115 char port_nbr; /* Port 0 or 1 */
116 char busy; /* 1 if port is busy */
117
118 char enabled; /* 1 if port is enabled */
119 char use_dma; /* 1 if port uses dma */
120 char tr_running;
121
122 char init_irqs;
123
124 /* Register shadow */
125 unsigned int ctrl_data_shadow;
126 /* Remaining bytes for current transfer */
127 volatile unsigned int out_count;
128 /* Current position in out_buffer */
129 unsigned char *outp;
130 /* 16*4 */
131 /* Next byte to be read by application */
132 volatile unsigned char *volatile readp;
133 /* Next byte to be written by etrax */
134 volatile unsigned char *volatile writep;
135
136 unsigned int in_buffer_size;
137 unsigned int inbufchunk;
138 struct etrax_dma_descr out_descr __attribute__ ((aligned(32)));
139 struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32)));
140 unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
141 unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32)));
142 unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
143 struct etrax_dma_descr *next_rx_desc;
144 struct etrax_dma_descr *prev_rx_desc;
145 int full;
146
147 wait_queue_head_t out_wait_q;
148 wait_queue_head_t in_wait_q;
149};
150
151
152static int etrax_sync_serial_init(void);
153static void initialize_port(int portnbr);
154static inline int sync_data_avail(struct sync_port *port);
155
156static int sync_serial_open(struct inode *inode, struct file *file);
157static int sync_serial_release(struct inode *inode, struct file *file);
158static unsigned int sync_serial_poll(struct file *filp, poll_table *wait);
159
90276a1a 160static int sync_serial_ioctl(struct file *file,
c974a9e5
JN		 161 unsigned int cmd, unsigned long arg);
162static ssize_t sync_serial_write(struct file *file, const char *buf,
163 size_t count, loff_t *ppos);
164static ssize_t sync_serial_read(struct file *file, char *buf,
165 size_t count, loff_t *ppos);
166
167#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
168 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
169 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
170 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
171#define SYNC_SER_DMA
172#endif
173
174static void send_word(struct sync_port *port);
175static void start_dma(struct sync_port *port, const char *data, int count);
176static void start_dma_in(struct sync_port *port);
177#ifdef SYNC_SER_DMA
178static irqreturn_t tr_interrupt(int irq, void *dev_id);
179static irqreturn_t rx_interrupt(int irq, void *dev_id);
180#endif
181#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
182 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
183 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
184 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
185#define SYNC_SER_MANUAL
186#endif
187#ifdef SYNC_SER_MANUAL
188static irqreturn_t manual_interrupt(int irq, void *dev_id);
189#endif
190
191/* The ports */
192static struct sync_port ports[] = {
193 {
194 .status = R_SYNC_SERIAL1_STATUS,
195 .ctrl_data = R_SYNC_SERIAL1_CTRL,
196 .output_dma_first = R_DMA_CH8_FIRST,
197 .output_dma_cmd = R_DMA_CH8_CMD,
198 .output_dma_clr_irq = R_DMA_CH8_CLR_INTR,
199 .input_dma_first = R_DMA_CH9_FIRST,
200 .input_dma_cmd = R_DMA_CH9_CMD,
201 .input_dma_descr = R_DMA_CH9_DESCR,
202 .input_dma_clr_irq = R_DMA_CH9_CLR_INTR,
203 .data_out = R_SYNC_SERIAL1_TR_DATA,
204 .data_in = R_SYNC_SERIAL1_REC_DATA,
205 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data),
206 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready),
207 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr),
208 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop),
209 .init_irqs = 1,
210#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
211 .use_dma = 1,
212#else
213 .use_dma = 0,
214#endif
215 },
216 {
217 .status = R_SYNC_SERIAL3_STATUS,
218 .ctrl_data = R_SYNC_SERIAL3_CTRL,
219 .output_dma_first = R_DMA_CH4_FIRST,
220 .output_dma_cmd = R_DMA_CH4_CMD,
221 .output_dma_clr_irq = R_DMA_CH4_CLR_INTR,
222 .input_dma_first = R_DMA_CH5_FIRST,
223 .input_dma_cmd = R_DMA_CH5_CMD,
224 .input_dma_descr = R_DMA_CH5_DESCR,
225 .input_dma_clr_irq = R_DMA_CH5_CLR_INTR,
226 .data_out = R_SYNC_SERIAL3_TR_DATA,
227 .data_in = R_SYNC_SERIAL3_REC_DATA,
228 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data),
229 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready),
230 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr),
231 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop),
232 .init_irqs = 1,
233#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
234 .use_dma = 1,
235#else
236 .use_dma = 0,
237#endif
238 }
239};
240
241/* Register shadows */
242static unsigned sync_serial_prescale_shadow;
243
244#define NUMBER_OF_PORTS 2
245
828c0950 246static const struct file_operations sync_serial_fops = {
90276a1a
JN		 247 .owner = THIS_MODULE,
248 .write = sync_serial_write,
249 .read = sync_serial_read,
250 .poll = sync_serial_poll,
251 .unlocked_ioctl = sync_serial_ioctl,
252 .open = sync_serial_open,
253 .release = sync_serial_release
c974a9e5
JN		 254};
255
256static int __init etrax_sync_serial_init(void)
257{
258 ports[0].enabled = 0;
259 ports[1].enabled = 0;
260
261#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
262 if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) {
263 printk(KERN_CRIT "ETRAX100LX sync_serial: "
264 "Could not allocate IO group for port %d\n", 0);
265 return -EBUSY;
266 }
267#endif
268#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
269 if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) {
270#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
271 cris_free_io_interface(if_sync_serial_1);
272#endif
273 printk(KERN_CRIT "ETRAX100LX sync_serial: "
274 "Could not allocate IO group for port %d\n", 1);
275 return -EBUSY;
276 }
277#endif
278
279 if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial",
280 &sync_serial_fops) < 0) {
281#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
282 cris_free_io_interface(if_sync_serial_3);
283#endif
284#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
285 cris_free_io_interface(if_sync_serial_1);
286#endif
287 printk("unable to get major for synchronous serial port\n");
288 return -EBUSY;
289 }
290
291 /* Deselect synchronous serial ports while configuring. */
292 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
293 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
294 *R_GEN_CONFIG_II = gen_config_ii_shadow;
295
296 /* Initialize Ports */
297#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
298 ports[0].enabled = 1;
299 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra);
300 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
301#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
302 ports[0].use_dma = 1;
303#else
304 ports[0].use_dma = 0;
305#endif
306 initialize_port(0);
307#endif
308
309#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
310 ports[1].enabled = 1;
311 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra);
312 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
313#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
314 ports[1].use_dma = 1;
315#else
316 ports[1].use_dma = 0;
317#endif
318 initialize_port(1);
319#endif
320
321 *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */
322
323 /* Set up timing */
324 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = (
325 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) |
326 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) |
327 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) |
328 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) |
329 IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) |
330 IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate,
331 DEFAULT_FRAME_RATE) |
332 IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) |
333 IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));
334
335 /* Select synchronous ports */
336 *R_GEN_CONFIG_II = gen_config_ii_shadow;
337
338 printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n");
339 return 0;
340}
341
342static void __init initialize_port(int portnbr)
343{
344 struct sync_port *port = &ports[portnbr];
345
346 DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr));
347
348 port->started = 0;
349 port->port_nbr = portnbr;
350 port->busy = 0;
351 port->tr_running = 0;
352
353 port->out_count = 0;
354 port->outp = port->out_buffer;
355
356 port->readp = port->flip;
357 port->writep = port->flip;
358 port->in_buffer_size = IN_BUFFER_SIZE;
359 port->inbufchunk = IN_DESCR_SIZE;
360 port->next_rx_desc = &port->in_descr[0];
361 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1];
362 port->prev_rx_desc->ctrl = d_eol;
363
364 init_waitqueue_head(&port->out_wait_q);
365 init_waitqueue_head(&port->in_wait_q);
366
367 port->ctrl_data_shadow =
368 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) |
369 IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) |
370 IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) |
371 IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) |
372 IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) |
373 IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) |
374 IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) |
375 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) |
376 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) |
377 IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) |
378 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) |
379 IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) |
380 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) |
381 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) |
382 IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) |
383 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) |
384 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)|
385 IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)|
386 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) |
387 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) |
388 IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)|
389 IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high);
390
391 if (port->use_dma)
392 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
393 dma_enable, on);
394 else
395 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
396 dma_enable, off);
397
398 *port->ctrl_data = port->ctrl_data_shadow;
399}
400
401static inline int sync_data_avail(struct sync_port *port)
402{
403 int avail;
404 unsigned char *start;
405 unsigned char *end;
406
407 start = (unsigned char *)port->readp; /* cast away volatile */
408 end = (unsigned char *)port->writep; /* cast away volatile */
409 /* 0123456789 0123456789
410 * ----- - -----
411 * ^rp ^wp ^wp ^rp
412 */
413 if (end >= start)
414 avail = end - start;
415 else
416 avail = port->in_buffer_size - (start - end);
417 return avail;
418}
419
420static inline int sync_data_avail_to_end(struct sync_port *port)
421{
422 int avail;
423 unsigned char *start;
424 unsigned char *end;
425
426 start = (unsigned char *)port->readp; /* cast away volatile */
427 end = (unsigned char *)port->writep; /* cast away volatile */
428 /* 0123456789 0123456789
429 * ----- -----
430 * ^rp ^wp ^wp ^rp
431 */
432
433 if (end >= start)
434 avail = end - start;
435 else
436 avail = port->flip + port->in_buffer_size - start;
437 return avail;
438}
439
440
441static int sync_serial_open(struct inode *inode, struct file *file)
442{
443 int dev = MINOR(inode->i_rdev);
444 struct sync_port *port;
445 int mode;
0c401df3 446 int err = -EBUSY;
c974a9e5 447
0c401df3 448 lock_kernel();
c974a9e5
JN		 449 DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
450
451 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
452 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
0c401df3
JC		 453 err = -ENODEV;
454 goto out;
c974a9e5
JN		 455 }
456 port = &ports[dev];
457 /* Allow open this device twice (assuming one reader and one writer) */
458 if (port->busy == 2) {
459 DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
0c401df3 460 goto out;
c974a9e5
JN		 461 }
462 if (port->init_irqs) {
463 if (port->use_dma) {
464 if (port == &ports[0]) {
465#ifdef SYNC_SER_DMA
466 if (request_irq(24, tr_interrupt, 0,
467 "synchronous serial 1 dma tr",
468 &ports[0])) {
469 printk(KERN_CRIT "Can't alloc "
470 "sync serial port 1 IRQ");
0c401df3 471 goto out;
c974a9e5
JN		 472 } else if (request_irq(25, rx_interrupt, 0,
473 "synchronous serial 1 dma rx",
474 &ports[0])) {
475 free_irq(24, &port[0]);
476 printk(KERN_CRIT "Can't alloc "
477 "sync serial port 1 IRQ");
0c401df3 478 goto out;
c974a9e5
JN		 479 } else if (cris_request_dma(8,
480 "synchronous serial 1 dma tr",
481 DMA_VERBOSE_ON_ERROR,
482 dma_ser1)) {
483 free_irq(24, &port[0]);
484 free_irq(25, &port[0]);
485 printk(KERN_CRIT "Can't alloc "
486 "sync serial port 1 "
487 "TX DMA channel");
0c401df3 488 goto out;
c974a9e5
JN		 489 } else if (cris_request_dma(9,
490 "synchronous serial 1 dma rec",
491 DMA_VERBOSE_ON_ERROR,
492 dma_ser1)) {
493 cris_free_dma(8, NULL);
494 free_irq(24, &port[0]);
495 free_irq(25, &port[0]);
496 printk(KERN_CRIT "Can't alloc "
497 "sync serial port 1 "
498 "RX DMA channel");
0c401df3 499 goto out;
c974a9e5
JN		 500 }
501#endif
502 RESET_DMA(8); WAIT_DMA(8);
503 RESET_DMA(9); WAIT_DMA(9);
504 *R_DMA_CH8_CLR_INTR =
505 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop,
506 do) |
507 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr,
508 do);
509 *R_DMA_CH9_CLR_INTR =
510 IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop,
511 do) |
512 IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr,
513 do);
514 *R_IRQ_MASK2_SET =
515 IO_STATE(R_IRQ_MASK2_SET, dma8_eop,
516 set) |
517 IO_STATE(R_IRQ_MASK2_SET, dma9_descr,
518 set);
519 } else if (port == &ports[1]) {
520#ifdef SYNC_SER_DMA
521 if (request_irq(20, tr_interrupt, 0,
522 "synchronous serial 3 dma tr",
523 &ports[1])) {
524 printk(KERN_CRIT "Can't alloc "
525 "sync serial port 3 IRQ");
0c401df3 526 goto out;
c974a9e5
JN		 527 } else if (request_irq(21, rx_interrupt, 0,
528 "synchronous serial 3 dma rx",
529 &ports[1])) {
530 free_irq(20, &ports[1]);
531 printk(KERN_CRIT "Can't alloc "
532 "sync serial port 3 IRQ");
0c401df3 533 goto out;
c974a9e5
JN		 534 } else if (cris_request_dma(4,
535 "synchronous serial 3 dma tr",
536 DMA_VERBOSE_ON_ERROR,
537 dma_ser3)) {
538 free_irq(21, &ports[1]);
539 free_irq(20, &ports[1]);
540 printk(KERN_CRIT "Can't alloc "
541 "sync serial port 3 "
542 "TX DMA channel");
0c401df3 543 goto out;
c974a9e5
JN		 544 } else if (cris_request_dma(5,
545 "synchronous serial 3 dma rec",
546 DMA_VERBOSE_ON_ERROR,
547 dma_ser3)) {
548 cris_free_dma(4, NULL);
549 free_irq(21, &ports[1]);
550 free_irq(20, &ports[1]);
551 printk(KERN_CRIT "Can't alloc "
552 "sync serial port 3 "
553 "RX DMA channel");
0c401df3 554 goto out;
c974a9e5
JN		 555 }
556#endif
557 RESET_DMA(4); WAIT_DMA(4);
558 RESET_DMA(5); WAIT_DMA(5);
559 *R_DMA_CH4_CLR_INTR =
560 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop,
561 do) |
562 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr,
563 do);
564 *R_DMA_CH5_CLR_INTR =
565 IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop,
566 do) |
567 IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr,
568 do);
569 *R_IRQ_MASK2_SET =
570 IO_STATE(R_IRQ_MASK2_SET, dma4_eop,
571 set) |
572 IO_STATE(R_IRQ_MASK2_SET, dma5_descr,
573 set);
574 }
575 start_dma_in(port);
576 port->init_irqs = 0;
577 } else { /* !port->use_dma */
578#ifdef SYNC_SER_MANUAL
579 if (port == &ports[0]) {
580 if (request_irq(8,
581 manual_interrupt,
582 IRQF_SHARED | IRQF_DISABLED,
583 "synchronous serial manual irq",
584 &ports[0])) {
585 printk(KERN_CRIT "Can't alloc "
586 "sync serial manual irq");
0c401df3 587 goto out;
c974a9e5
JN		 588 }
589 } else if (port == &ports[1]) {
590 if (request_irq(8,
591 manual_interrupt,
592 IRQF_SHARED | IRQF_DISABLED,
593 "synchronous serial manual irq",
594 &ports[1])) {
595 printk(KERN_CRIT "Can't alloc "
596 "sync serial manual irq");
0c401df3 597 goto out;
c974a9e5
JN		 598 }
599 }
600 port->init_irqs = 0;
601#else
602 panic("sync_serial: Manual mode not supported.\n");
603#endif /* SYNC_SER_MANUAL */
604 }
605 } /* port->init_irqs */
606
607 port->busy++;
608 /* Start port if we use it as input */
609 mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow);
610 if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) ||
611 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) ||
612 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) ||
613 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) {
614 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
615 running);
616 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
617 enable);
618 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
619 enable);
620 port->started = 1;
621 *port->ctrl_data = port->ctrl_data_shadow;
622 if (!port->use_dma)
623 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
624 DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev));
625 }
0c401df3
JC		 626 ret = 0;
627
628out:
629 unlock_kernel();
630 return ret;
c974a9e5
JN		 631}
632
633static int sync_serial_release(struct inode *inode, struct file *file)
634{
635 int dev = MINOR(inode->i_rdev);
636 struct sync_port *port;
637
638 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
639 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
640 return -ENODEV;
641 }
642 port = &ports[dev];
643 if (port->busy)
644 port->busy--;
645 if (!port->busy)
646 *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) |
647 (1 << port->transmitter_ready_bit));
648
649 return 0;
650}
651
652
653
654static unsigned int sync_serial_poll(struct file *file, poll_table *wait)
655{
656 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
657 unsigned int mask = 0;
658 struct sync_port *port;
659 DEBUGPOLL(static unsigned int prev_mask = 0);
660
661 port = &ports[dev];
662 poll_wait(file, &port->out_wait_q, wait);
663 poll_wait(file, &port->in_wait_q, wait);
664 /* Some room to write */
665 if (port->out_count < OUT_BUFFER_SIZE)
666 mask |= POLLOUT | POLLWRNORM;
667 /* At least an inbufchunk of data */
668 if (sync_data_avail(port) >= port->inbufchunk)
669 mask |= POLLIN | POLLRDNORM;
670
671 DEBUGPOLL(if (mask != prev_mask)
672 printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n",
673 mask,
674 mask & POLLOUT ? "POLLOUT" : "",
675 mask & POLLIN ? "POLLIN" : "");
676 prev_mask = mask;
677 );
678 return mask;
679}
680
90276a1a 681static int sync_serial_ioctl_unlocked(struct file *file,
c974a9e5
JN		 682 unsigned int cmd, unsigned long arg)
683{
684 int return_val = 0;
685 unsigned long flags;
686
687 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
688 struct sync_port *port;
689
690 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
691 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
692 return -1;
693 }
694 port = &ports[dev];
695
696 local_irq_save(flags);
697 /* Disable port while changing config */
698 if (dev) {
699 if (port->use_dma) {
700 RESET_DMA(4); WAIT_DMA(4);
701 port->tr_running = 0;
702 port->out_count = 0;
703 port->outp = port->out_buffer;
704 *R_DMA_CH4_CLR_INTR =
705 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
706 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
707 }
708 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
709 } else {
710 if (port->use_dma) {
711 RESET_DMA(8); WAIT_DMA(8);
712 port->tr_running = 0;
713 port->out_count = 0;
714 port->outp = port->out_buffer;
715 *R_DMA_CH8_CLR_INTR =
716 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
717 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
718 }
719 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
720 }
721 *R_GEN_CONFIG_II = gen_config_ii_shadow;
722 local_irq_restore(flags);
723
724 switch (cmd) {
725 case SSP_SPEED:
726 if (GET_SPEED(arg) == CODEC) {
727 if (dev)
728 SETS(sync_serial_prescale_shadow,
729 R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
730 codec);
731 else
732 SETS(sync_serial_prescale_shadow,
733 R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
734 codec);
735
736 SETF(sync_serial_prescale_shadow,
737 R_SYNC_SERIAL_PRESCALE, prescaler,
738 GET_FREQ(arg));
739 SETF(sync_serial_prescale_shadow,
740 R_SYNC_SERIAL_PRESCALE, frame_rate,
741 GET_FRAME_RATE(arg));
742 SETF(sync_serial_prescale_shadow,
743 R_SYNC_SERIAL_PRESCALE, word_rate,
744 GET_WORD_RATE(arg));
745 } else {
746 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
747 tr_baud, GET_SPEED(arg));
748 if (dev)
749 SETS(sync_serial_prescale_shadow,
750 R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
751 baudrate);
752 else
753 SETS(sync_serial_prescale_shadow,
754 R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
755 baudrate);
756 }
757 break;
758 case SSP_MODE:
759 if (arg > 5)
760 return -EINVAL;
761 if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT)
762 *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit;
763 else if (!port->use_dma)
764 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
765 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg);
766 break;
767 case SSP_FRAME_SYNC:
768 if (arg & NORMAL_SYNC)
769 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
770 f_synctype, normal);
771 else if (arg & EARLY_SYNC)
772 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
773 f_synctype, early);
774
775 if (arg & BIT_SYNC)
776 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
777 f_syncsize, bit);
778 else if (arg & WORD_SYNC)
779 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
780 f_syncsize, word);
781 else if (arg & EXTENDED_SYNC)
782 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
783 f_syncsize, extended);
784
785 if (arg & SYNC_ON)
786 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
787 f_sync, on);
788 else if (arg & SYNC_OFF)
789 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
790 f_sync, off);
791
792 if (arg & WORD_SIZE_8)
793 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
794 wordsize, size8bit);
795 else if (arg & WORD_SIZE_12)
796 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
797 wordsize, size12bit);
798 else if (arg & WORD_SIZE_16)
799 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
800 wordsize, size16bit);
801 else if (arg & WORD_SIZE_24)
802 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
803 wordsize, size24bit);
804 else if (arg & WORD_SIZE_32)
805 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
806 wordsize, size32bit);
807
808 if (arg & BIT_ORDER_MSB)
809 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
810 bitorder, msb);
811 else if (arg & BIT_ORDER_LSB)
812 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
813 bitorder, lsb);
814
815 if (arg & FLOW_CONTROL_ENABLE)
816 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
817 flow_ctrl, enabled);
818 else if (arg & FLOW_CONTROL_DISABLE)
819 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
820 flow_ctrl, disabled);
821
822 if (arg & CLOCK_NOT_GATED)
823 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
824 clk_mode, normal);
825 else if (arg & CLOCK_GATED)
826 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
827 clk_mode, gated);
828
829 break;
830 case SSP_IPOLARITY:
831 /* NOTE!! negedge is considered NORMAL */
832 if (arg & CLOCK_NORMAL)
833 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
834 clk_polarity, neg);
835 else if (arg & CLOCK_INVERT)
836 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
837 clk_polarity, pos);
838
839 if (arg & FRAME_NORMAL)
840 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
841 frame_polarity, normal);
842 else if (arg & FRAME_INVERT)
843 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
844 frame_polarity, inverted);
845
846 if (arg & STATUS_NORMAL)
847 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
848 status_polarity, normal);
849 else if (arg & STATUS_INVERT)
850 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
851 status_polarity, inverted);
852 break;
853 case SSP_OPOLARITY:
854 if (arg & CLOCK_NORMAL)
855 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
856 clk_driver, normal);
857 else if (arg & CLOCK_INVERT)
858 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
859 clk_driver, inverted);
860
861 if (arg & FRAME_NORMAL)
862 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
863 frame_driver, normal);
864 else if (arg & FRAME_INVERT)
865 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
866 frame_driver, inverted);
867
868 if (arg & STATUS_NORMAL)
869 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
870 status_driver, normal);
871 else if (arg & STATUS_INVERT)
872 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
873 status_driver, inverted);
874 break;
875 case SSP_SPI:
876 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl,
877 disabled);
878 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder,
879 msb);
880 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize,
881 size8bit);
882 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
883 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize,
884 word);
885 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype,
886 normal);
887 if (arg & SPI_SLAVE) {
888 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
889 frame_polarity, inverted);
890 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
891 clk_polarity, neg);
892 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
893 mode, SLAVE_INPUT);
894 } else {
895 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
896 frame_driver, inverted);
897 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
898 clk_driver, inverted);
899 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
900 mode, MASTER_OUTPUT);
901 }
902 break;
903 case SSP_INBUFCHUNK:
904#if 0
905 if (arg > port->in_buffer_size/NUM_IN_DESCR)
906 return -EINVAL;
907 port->inbufchunk = arg;
908 /* Make sure in_buffer_size is a multiple of inbufchunk */
909 port->in_buffer_size =
910 (port->in_buffer_size/port->inbufchunk) *
911 port->inbufchunk;
912 DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n",
913 port->inbufchunk, port->in_buffer_size));
914 if (port->use_dma) {
915 if (port->port_nbr == 0) {
916 RESET_DMA(9);
917 WAIT_DMA(9);
918 } else {
919 RESET_DMA(5);
920 WAIT_DMA(5);
921 }
922 start_dma_in(port);
923 }
924#endif
925 break;
926 default:
927 return_val = -1;
928 }
929 /* Make sure we write the config without interruption */
930 local_irq_save(flags);
931 /* Set config and enable port */
932 *port->ctrl_data = port->ctrl_data_shadow;
933 nop(); nop(); nop(); nop();
934 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow;
935 nop(); nop(); nop(); nop();
936 if (dev)
937 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
938 else
939 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
940
941 *R_GEN_CONFIG_II = gen_config_ii_shadow;
942 /* Reset DMA. At readout from serial port the data could be shifted
943 * one byte if not resetting DMA.
944 */
945 if (port->use_dma) {
946 if (port->port_nbr == 0) {
947 RESET_DMA(9);
948 WAIT_DMA(9);
949 } else {
950 RESET_DMA(5);
951 WAIT_DMA(5);
952 }
953 start_dma_in(port);
954 }
955 local_irq_restore(flags);
956 return return_val;
957}
958
90276a1a
JN		 959static long sync_serial_ioctl(struct file *file,
960 unsigned int cmd, unsigned long arg)
961{
962 long ret;
963
964 lock_kernel();
965 ret = sync_serial_ioctl_unlocked(file, cmd, arg);
966 unlock_kernel();
967
968 return ret;
969}
970
c974a9e5
JN		 971
972static ssize_t sync_serial_write(struct file *file, const char *buf,
973 size_t count, loff_t *ppos)
974{
975 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
976 DECLARE_WAITQUEUE(wait, current);
977 struct sync_port *port;
978 unsigned long flags;
979 unsigned long c, c1;
980 unsigned long free_outp;
981 unsigned long outp;
982 unsigned long out_buffer;
983
984 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
985 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
986 return -ENODEV;
987 }
988 port = &ports[dev];
989
990 DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n",
991 port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE));
992 /* Space to end of buffer */
993 /*
994 * out_buffer <c1>012345<- c ->OUT_BUFFER_SIZE
995 * outp^ +out_count
996 * ^free_outp
997 * out_buffer 45<- c ->0123OUT_BUFFER_SIZE
998 * +out_count outp^
999 * free_outp
1000 *
1001 */
1002
1003 /* Read variables that may be updated by interrupts */
1004 local_irq_save(flags);
1005 if (count > OUT_BUFFER_SIZE - port->out_count)
1006 count = OUT_BUFFER_SIZE - port->out_count;
1007
1008 outp = (unsigned long)port->outp;
1009 free_outp = outp + port->out_count;
1010 local_irq_restore(flags);
1011 out_buffer = (unsigned long)port->out_buffer;
1012
1013 /* Find out where and how much to write */
1014 if (free_outp >= out_buffer + OUT_BUFFER_SIZE)
1015 free_outp -= OUT_BUFFER_SIZE;
1016 if (free_outp >= outp)
1017 c = out_buffer + OUT_BUFFER_SIZE - free_outp;
1018 else
1019 c = outp - free_outp;
1020 if (c > count)
1021 c = count;
1022
1023 DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n",
1024 outp, free_outp, c));
1025 if (copy_from_user((void *)free_outp, buf, c))
1026 return -EFAULT;
1027
1028 if (c != count) {
1029 buf += c;
1030 c1 = count - c;
1031 DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n",
1032 free_outp-out_buffer, c, c1));
1033 if (copy_from_user((void *)out_buffer, buf, c1))
1034 return -EFAULT;
1035 }
1036 local_irq_save(flags);
1037 port->out_count += count;
1038 local_irq_restore(flags);
1039
1040 /* Make sure transmitter/receiver is running */
1041 if (!port->started) {
1042 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
1043 running);
1044 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
1045 enable);
1046 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
1047 enable);
1048 port->started = 1;
1049 }
1050
1051 *port->ctrl_data = port->ctrl_data_shadow;
1052
1053 if (file->f_flags & O_NONBLOCK) {
1054 local_irq_save(flags);
1055 if (!port->tr_running) {
1056 if (!port->use_dma) {
1057 /* Start sender by writing data */
1058 send_word(port);
1059 /* and enable transmitter ready IRQ */
1060 *R_IRQ_MASK1_SET = 1 <<
1061 port->transmitter_ready_bit;
1062 } else
1063 start_dma(port,
1064 (unsigned char *volatile)port->outp, c);
1065 }
1066 local_irq_restore(flags);
1067 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n",
1068 port->port_nbr, count));
1069 return count;
1070 }
1071
1072 /* Sleep until all sent */
1073 add_wait_queue(&port->out_wait_q, &wait);
1074 set_current_state(TASK_INTERRUPTIBLE);
1075 local_irq_save(flags);
1076 if (!port->tr_running) {
1077 if (!port->use_dma) {
1078 /* Start sender by writing data */
1079 send_word(port);
1080 /* and enable transmitter ready IRQ */
1081 *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit;
1082 } else
1083 start_dma(port, port->outp, c);
1084 }
1085 local_irq_restore(flags);
1086 schedule();
1087 set_current_state(TASK_RUNNING);
1088 remove_wait_queue(&port->out_wait_q, &wait);
1089 if (signal_pending(current))
1090 return -EINTR;
1091
1092 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count));
1093 return count;
1094}
1095
1096static ssize_t sync_serial_read(struct file *file, char *buf,
1097 size_t count, loff_t *ppos)
1098{
1099 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
1100 int avail;
1101 struct sync_port *port;
1102 unsigned char *start;
1103 unsigned char *end;
1104 unsigned long flags;
1105
1106 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
1107 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
1108 return -ENODEV;
1109 }
1110 port = &ports[dev];
1111
1112 DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n",
1113 dev, count, port->readp - port->flip,
1114 port->writep - port->flip, port->in_buffer_size));
1115
1116 if (!port->started) {
1117 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
1118 running);
1119 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
1120 enable);
1121 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
1122 enable);
1123 port->started = 1;
1124 }
1125 *port->ctrl_data = port->ctrl_data_shadow;
1126
1127 /* Calculate number of available bytes */
1128 /* Save pointers to avoid that they are modified by interrupt */
1129 local_irq_save(flags);
1130 start = (unsigned char *)port->readp; /* cast away volatile */
1131 end = (unsigned char *)port->writep; /* cast away volatile */
1132 local_irq_restore(flags);
1133 while (start == end && !port->full) {
1134 /* No data */
1135 if (file->f_flags & O_NONBLOCK)
1136 return -EAGAIN;
1137
1138 interruptible_sleep_on(&port->in_wait_q);
1139 if (signal_pending(current))
1140 return -EINTR;
1141
1142 local_irq_save(flags);
1143 start = (unsigned char *)port->readp; /* cast away volatile */
1144 end = (unsigned char *)port->writep; /* cast away volatile */
1145 local_irq_restore(flags);
1146 }
1147
1148 /* Lazy read, never return wrapped data. */
1149 if (port->full)
1150 avail = port->in_buffer_size;
1151 else if (end > start)
1152 avail = end - start;
1153 else
1154 avail = port->flip + port->in_buffer_size - start;
1155
1156 count = count > avail ? avail : count;
1157 if (copy_to_user(buf, start, count))
1158 return -EFAULT;
1159 /* Disable interrupts while updating readp */
1160 local_irq_save(flags);
1161 port->readp += count;
1162 if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
1163 port->readp = port->flip;
1164 port->full = 0;
1165 local_irq_restore(flags);
1166 DEBUGREAD(printk(KERN_DEBUG "r %d\n", count));
1167 return count;
1168}
1169
1170static void send_word(struct sync_port *port)
1171{
1172 switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize,
1173 port->ctrl_data_shadow)) {
1174 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
1175 port->out_count--;
1176 *port->data_out = *port->outp++;
1177 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1178 port->outp = port->out_buffer;
1179 break;
1180 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
1181 {
1182 int data = (*port->outp++) << 8;
1183 data |= *port->outp++;
1184 port->out_count -= 2;
1185 *port->data_out = data;
1186 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1187 port->outp = port->out_buffer;
1188 break;
1189 }
1190 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
1191 port->out_count -= 2;
1192 *port->data_out = *(unsigned short *)port->outp;
1193 port->outp += 2;
1194 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1195 port->outp = port->out_buffer;
1196 break;
1197 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
1198 port->out_count -= 3;
1199 *port->data_out = *(unsigned int *)port->outp;
1200 port->outp += 3;
1201 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1202 port->outp = port->out_buffer;
1203 break;
1204 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
1205 port->out_count -= 4;
1206 *port->data_out = *(unsigned int *)port->outp;
1207 port->outp += 4;
1208 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1209 port->outp = port->out_buffer;
1210 break;
1211 }
1212}
1213
1214
1215static void start_dma(struct sync_port *port, const char *data, int count)
1216{
1217 port->tr_running = 1;
1218 port->out_descr.hw_len = 0;
1219 port->out_descr.next = 0;
1220 port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */
1221 port->out_descr.sw_len = count;
1222 port->out_descr.buf = virt_to_phys(data);
1223 port->out_descr.status = 0;
1224
1225 *port->output_dma_first = virt_to_phys(&port->out_descr);
1226 *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
1227 DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n",
1228 (unsigned long)data, count));
1229}
1230
1231static void start_dma_in(struct sync_port *port)
1232{
1233 int i;
1234 unsigned long buf;
1235 port->writep = port->flip;
1236
1237 if (port->writep > port->flip + port->in_buffer_size) {
1238 panic("Offset too large in sync serial driver\n");
1239 return;
1240 }
1241 buf = virt_to_phys(port->in_buffer);
1242 for (i = 0; i < NUM_IN_DESCR; i++) {
1243 port->in_descr[i].sw_len = port->inbufchunk;
1244 port->in_descr[i].ctrl = d_int;
1245 port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]);
1246 port->in_descr[i].buf = buf;
1247 port->in_descr[i].hw_len = 0;
1248 port->in_descr[i].status = 0;
1249 port->in_descr[i].fifo_len = 0;
1250 buf += port->inbufchunk;
1251 prepare_rx_descriptor(&port->in_descr[i]);
1252 }
1253 /* Link the last descriptor to the first */
1254 port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]);
1255 port->in_descr[i-1].ctrl |= d_eol;
1256 port->next_rx_desc = &port->in_descr[0];
1257 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1];
1258 *port->input_dma_first = virt_to_phys(port->next_rx_desc);
1259 *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
1260}
1261
1262#ifdef SYNC_SER_DMA
1263static irqreturn_t tr_interrupt(int irq, void *dev_id)
1264{
1265 unsigned long ireg = *R_IRQ_MASK2_RD;
1266 struct etrax_dma_descr *descr;
1267 unsigned int sentl;
1268 int handled = 0;
1269 int i;
1270
1271 for (i = 0; i < NUMBER_OF_PORTS; i++) {
1272 struct sync_port *port = &ports[i];
1273 if (!port->enabled || !port->use_dma)
1274 continue;
1275
1276 /* IRQ active for the port? */
1277 if (!(ireg & (1 << port->output_dma_bit)))
1278 continue;
1279
1280 handled = 1;
1281
1282 /* Clear IRQ */
1283 *port->output_dma_clr_irq =
1284 IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
1285 IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
1286
1287 descr = &port->out_descr;
1288 if (!(descr->status & d_stop))
1289 sentl = descr->sw_len;
1290 else
1291 /* Otherwise find amount of data sent here */
1292 sentl = descr->hw_len;
1293
1294 port->out_count -= sentl;
1295 port->outp += sentl;
1296 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1297 port->outp = port->out_buffer;
1298 if (port->out_count) {
1299 int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp;
1300 if (c > port->out_count)
1301 c = port->out_count;
1302 DEBUGTXINT(printk(KERN_DEBUG
1303 "tx_int DMAWRITE %i %i\n", sentl, c));
1304 start_dma(port, port->outp, c);
1305 } else {
1306 DEBUGTXINT(printk(KERN_DEBUG
1307 "tx_int DMA stop %i\n", sentl));
1308 port->tr_running = 0;
1309 }
1310 /* wake up the waiting process */
1311 wake_up_interruptible(&port->out_wait_q);
1312 }
1313 return IRQ_RETVAL(handled);
1314} /* tr_interrupt */
1315
1316static irqreturn_t rx_interrupt(int irq, void *dev_id)
1317{
1318 unsigned long ireg = *R_IRQ_MASK2_RD;
1319 int i;
1320 int handled = 0;
1321
1322 for (i = 0; i < NUMBER_OF_PORTS; i++) {
1323 struct sync_port *port = &ports[i];
1324
1325 if (!port->enabled || !port->use_dma)
1326 continue;
1327
1328 if (!(ireg & (1 << port->input_dma_descr_bit)))
1329 continue;
1330
1331 /* Descriptor interrupt */
1332 handled = 1;
1333 while (*port->input_dma_descr !=
1334 virt_to_phys(port->next_rx_desc)) {
1335 if (port->writep + port->inbufchunk > port->flip +
1336 port->in_buffer_size) {
1337 int first_size = port->flip +
1338 port->in_buffer_size - port->writep;
1339 memcpy(port->writep,
1340 phys_to_virt(port->next_rx_desc->buf),
1341 first_size);
1342 memcpy(port->flip,
1343 phys_to_virt(port->next_rx_desc->buf +
1344 first_size),
1345 port->inbufchunk - first_size);
1346 port->writep = port->flip +
1347 port->inbufchunk - first_size;
1348 } else {
1349 memcpy(port->writep,
1350 phys_to_virt(port->next_rx_desc->buf),
1351 port->inbufchunk);
1352 port->writep += port->inbufchunk;
1353 if (port->writep >= port->flip
1354 + port->in_buffer_size)
1355 port->writep = port->flip;
1356 }
1357 if (port->writep == port->readp)
1358 port->full = 1;
1359 prepare_rx_descriptor(port->next_rx_desc);
1360 port->next_rx_desc->ctrl |= d_eol;
1361 port->prev_rx_desc->ctrl &= ~d_eol;
1362 port->prev_rx_desc = phys_to_virt((unsigned)
1363 port->next_rx_desc);
1364 port->next_rx_desc = phys_to_virt((unsigned)
1365 port->next_rx_desc->next);
1366 /* Wake up the waiting process */
1367 wake_up_interruptible(&port->in_wait_q);
1368 *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD,
1369 cmd, restart);
1370 /* DMA has reached end of descriptor */
1371 *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR,
1372 clr_descr, do);
1373 }
1374 }
1375 return IRQ_RETVAL(handled);
1376} /* rx_interrupt */
1377#endif /* SYNC_SER_DMA */
1378
1379#ifdef SYNC_SER_MANUAL
1380static irqreturn_t manual_interrupt(int irq, void *dev_id)
1381{
1382 int i;
1383 int handled = 0;
1384
1385 for (i = 0; i < NUMBER_OF_PORTS; i++) {
1386 struct sync_port *port = &ports[i];
1387
1388 if (!port->enabled || port->use_dma)
1389 continue;
1390
1391 /* Data received? */
1392 if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) {
1393 handled = 1;
1394 /* Read data */
1395 switch (port->ctrl_data_shadow &
1396 IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) {
1397 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
1398 *port->writep++ =
1399 *(volatile char *)port->data_in;
1400 break;
1401 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
1402 {
1403 int data = *(unsigned short *)port->data_in;
1404 *port->writep = (data & 0x0ff0) >> 4;
1405 *(port->writep + 1) = data & 0x0f;
1406 port->writep += 2;
1407 break;
1408 }
1409 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
1410 *(unsigned short *)port->writep =
1411 *(volatile unsigned short *)port->data_in;
1412 port->writep += 2;
1413 break;
1414 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
1415 *(unsigned int *)port->writep = *port->data_in;
1416 port->writep += 3;
1417 break;
1418 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
1419 *(unsigned int *)port->writep = *port->data_in;
1420 port->writep += 4;
1421 break;
1422 }
1423
1424 /* Wrap? */
1425 if (port->writep >= port->flip + port->in_buffer_size)
1426 port->writep = port->flip;
1427 if (port->writep == port->readp) {
1428 /* Receive buffer overrun, discard oldest */
1429 port->readp++;
1430 /* Wrap? */
1431 if (port->readp >= port->flip +
1432 port->in_buffer_size)
1433 port->readp = port->flip;
1434 }
1435 if (sync_data_avail(port) >= port->inbufchunk) {
1436 /* Wake up application */
1437 wake_up_interruptible(&port->in_wait_q);
1438 }
1439 }
1440
1441 /* Transmitter ready? */
1442 if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) {
1443 if (port->out_count > 0) {
1444 /* More data to send */
1445 send_word(port);
1446 } else {
1447 /* Transmission finished */
1448 /* Turn off IRQ */
1449 *R_IRQ_MASK1_CLR = 1 <<
1450 port->transmitter_ready_bit;
1451 /* Wake up application */
1452 wake_up_interruptible(&port->out_wait_q);
1453 }
1454 }
1455 }
1456 return IRQ_RETVAL(handled);
1457}
1458#endif
1459
1460module_init(etrax_sync_serial_init);
Clone of davem's net-next-2.6 tree