[net-next-2.6.git] / arch / blackfin / mach-common / smp.c

/*
 * File:         arch/blackfin/kernel/smp.c
 * Author:       Philippe Gerum <rpm@xenomai.org>
 * IPI management based on arch/arm/kernel/smp.c.
 *
 *               Copyright 2007 Analog Devices Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/cache.h>
#include <linux/profile.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/cpu.h>
#include <linux/smp.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/cpu.h>
#include <linux/err.h>

/*
 * Anomaly notes:
 * 05000120 - we always define corelock as 32-bit integer in L2
 */
struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));

void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
	*init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
	*init_saved_dcplb_fault_addr_coreb;

cpumask_t cpu_possible_map;
EXPORT_SYMBOL(cpu_possible_map);

cpumask_t cpu_online_map;
EXPORT_SYMBOL(cpu_online_map);

#define BFIN_IPI_RESCHEDULE   0
#define BFIN_IPI_CALL_FUNC    1
#define BFIN_IPI_CPU_STOP     2

struct blackfin_flush_data {
	unsigned long start;
	unsigned long end;
};

void *secondary_stack;


struct smp_call_struct {
	void (*func)(void *info);
	void *info;
	int wait;
	cpumask_t pending;
	cpumask_t waitmask;
};

static struct blackfin_flush_data smp_flush_data;

static DEFINE_SPINLOCK(stop_lock);

struct ipi_message {
	struct list_head list;
	unsigned long type;
	struct smp_call_struct call_struct;
};

struct ipi_message_queue {
	struct list_head head;
	spinlock_t lock;
	unsigned long count;
};

static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);

static void ipi_cpu_stop(unsigned int cpu)
{
	spin_lock(&stop_lock);
	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	dump_stack();
	spin_unlock(&stop_lock);

	cpu_clear(cpu, cpu_online_map);

	local_irq_disable();

	while (1)
		SSYNC();
}

static void ipi_flush_icache(void *info)
{
	struct blackfin_flush_data *fdata = info;

	/* Invalidate the memory holding the bounds of the flushed region. */
	blackfin_dcache_invalidate_range((unsigned long)fdata,
					 (unsigned long)fdata + sizeof(*fdata));

	blackfin_icache_flush_range(fdata->start, fdata->end);
}

static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
{
	int wait;
	void (*func)(void *info);
	void *info;
	func = msg->call_struct.func;
	info = msg->call_struct.info;
	wait = msg->call_struct.wait;
	cpu_clear(cpu, msg->call_struct.pending);
	func(info);
	if (wait)
		cpu_clear(cpu, msg->call_struct.waitmask);
	else
		kfree(msg);
}

static irqreturn_t ipi_handler(int irq, void *dev_instance)
{
	struct ipi_message *msg, *mg;
	struct ipi_message_queue *msg_queue;
	unsigned int cpu = smp_processor_id();

	platform_clear_ipi(cpu);

	msg_queue = &__get_cpu_var(ipi_msg_queue);
	msg_queue->count++;

	spin_lock(&msg_queue->lock);
	list_for_each_entry_safe(msg, mg, &msg_queue->head, list) {
		list_del(&msg->list);
		switch (msg->type) {
		case BFIN_IPI_RESCHEDULE:
			/* That's the easiest one; leave it to
			 * return_from_int. */
			kfree(msg);
			break;
		case BFIN_IPI_CALL_FUNC:
			spin_unlock(&msg_queue->lock);
			ipi_call_function(cpu, msg);
			spin_lock(&msg_queue->lock);
			break;
		case BFIN_IPI_CPU_STOP:
			spin_unlock(&msg_queue->lock);
			ipi_cpu_stop(cpu);
			spin_lock(&msg_queue->lock);
			kfree(msg);
			break;
		default:
			printk(KERN_CRIT "CPU%u: Unknown IPI message \
			0x%lx\n", cpu, msg->type);
			kfree(msg);
			break;
		}
	}
	spin_unlock(&msg_queue->lock);
	return IRQ_HANDLED;
}

static void ipi_queue_init(void)
{
	unsigned int cpu;
	struct ipi_message_queue *msg_queue;
	for_each_possible_cpu(cpu) {
		msg_queue = &per_cpu(ipi_msg_queue, cpu);
		INIT_LIST_HEAD(&msg_queue->head);
		spin_lock_init(&msg_queue->lock);
		msg_queue->count = 0;
	}
}

int smp_call_function(void (*func)(void *info), void *info, int wait)
{
	unsigned int cpu;
	cpumask_t callmap;
	unsigned long flags;
	struct ipi_message_queue *msg_queue;
	struct ipi_message *msg;

	callmap = cpu_online_map;
	cpu_clear(smp_processor_id(), callmap);
	if (cpus_empty(callmap))
		return 0;

	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
	INIT_LIST_HEAD(&msg->list);
	msg->call_struct.func = func;
	msg->call_struct.info = info;
	msg->call_struct.wait = wait;
	msg->call_struct.pending = callmap;
	msg->call_struct.waitmask = callmap;
	msg->type = BFIN_IPI_CALL_FUNC;

	for_each_cpu_mask(cpu, callmap) {
		msg_queue = &per_cpu(ipi_msg_queue, cpu);
		spin_lock_irqsave(&msg_queue->lock, flags);
		list_add(&msg->list, &msg_queue->head);
		spin_unlock_irqrestore(&msg_queue->lock, flags);
		platform_send_ipi_cpu(cpu);
	}
	if (wait) {
		while (!cpus_empty(msg->call_struct.waitmask))
			blackfin_dcache_invalidate_range(
				(unsigned long)(&msg->call_struct.waitmask),
				(unsigned long)(&msg->call_struct.waitmask));
		kfree(msg);
	}
	return 0;
}
EXPORT_SYMBOL_GPL(smp_call_function);

int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
				int wait)
{
	unsigned int cpu = cpuid;
	cpumask_t callmap;
	unsigned long flags;
	struct ipi_message_queue *msg_queue;
	struct ipi_message *msg;

	if (cpu_is_offline(cpu))
		return 0;
	cpus_clear(callmap);
	cpu_set(cpu, callmap);

	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
	INIT_LIST_HEAD(&msg->list);
	msg->call_struct.func = func;
	msg->call_struct.info = info;
	msg->call_struct.wait = wait;
	msg->call_struct.pending = callmap;
	msg->call_struct.waitmask = callmap;
	msg->type = BFIN_IPI_CALL_FUNC;

	msg_queue = &per_cpu(ipi_msg_queue, cpu);
	spin_lock_irqsave(&msg_queue->lock, flags);
	list_add(&msg->list, &msg_queue->head);
	spin_unlock_irqrestore(&msg_queue->lock, flags);
	platform_send_ipi_cpu(cpu);

	if (wait) {
		while (!cpus_empty(msg->call_struct.waitmask))
			blackfin_dcache_invalidate_range(
				(unsigned long)(&msg->call_struct.waitmask),
				(unsigned long)(&msg->call_struct.waitmask));
		kfree(msg);
	}
	return 0;
}
EXPORT_SYMBOL_GPL(smp_call_function_single);

void smp_send_reschedule(int cpu)
{
	unsigned long flags;
	struct ipi_message_queue *msg_queue;
	struct ipi_message *msg;

	if (cpu_is_offline(cpu))
		return;

	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
	memset(msg, 0, sizeof(msg));
	INIT_LIST_HEAD(&msg->list);
	msg->type = BFIN_IPI_RESCHEDULE;

	msg_queue = &per_cpu(ipi_msg_queue, cpu);
	spin_lock_irqsave(&msg_queue->lock, flags);
	list_add(&msg->list, &msg_queue->head);
	spin_unlock_irqrestore(&msg_queue->lock, flags);
	platform_send_ipi_cpu(cpu);

	return;
}

void smp_send_stop(void)
{
	unsigned int cpu;
	cpumask_t callmap;
	unsigned long flags;
	struct ipi_message_queue *msg_queue;
	struct ipi_message *msg;

	callmap = cpu_online_map;
	cpu_clear(smp_processor_id(), callmap);
	if (cpus_empty(callmap))
		return;

	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
	memset(msg, 0, sizeof(msg));
	INIT_LIST_HEAD(&msg->list);
	msg->type = BFIN_IPI_CPU_STOP;

	for_each_cpu_mask(cpu, callmap) {
		msg_queue = &per_cpu(ipi_msg_queue, cpu);
		spin_lock_irqsave(&msg_queue->lock, flags);
		list_add(&msg->list, &msg_queue->head);
		spin_unlock_irqrestore(&msg_queue->lock, flags);
		platform_send_ipi_cpu(cpu);
	}
	return;
}

int __cpuinit __cpu_up(unsigned int cpu)
{
	struct task_struct *idle;
	int ret;

	idle = fork_idle(cpu);
	if (IS_ERR(idle)) {
		printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
		return PTR_ERR(idle);
	}

	secondary_stack = task_stack_page(idle) + THREAD_SIZE;
	smp_wmb();

	ret = platform_boot_secondary(cpu, idle);

	if (ret) {
		cpu_clear(cpu, cpu_present_map);
		printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
		free_task(idle);
	} else
		cpu_set(cpu, cpu_online_map);

	secondary_stack = NULL;

	return ret;
}

static void __cpuinit setup_secondary(unsigned int cpu)
{
#if !(defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE))
	struct irq_desc *timer_desc;
#endif
	unsigned long ilat;

	bfin_write_IMASK(0);
	CSYNC();
	ilat = bfin_read_ILAT();
	CSYNC();
	bfin_write_ILAT(ilat);
	CSYNC();

	/* Reserve the PDA space for the secondary CPU. */
	reserve_pda();

	/* Enable interrupt levels IVG7-15. IARs have been already
	 * programmed by the boot CPU.  */
	bfin_irq_flags |= IMASK_IVG15 |
	    IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
	    IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;

#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
	/* Power down the core timer, just to play safe. */
	bfin_write_TCNTL(0);

	/* system timer0 has been setup by CoreA. */
#else
	timer_desc = irq_desc + IRQ_CORETMR;
	setup_core_timer();
	timer_desc->chip->enable(IRQ_CORETMR);
#endif
}

void __cpuinit secondary_start_kernel(void)
{
	unsigned int cpu = smp_processor_id();
	struct mm_struct *mm = &init_mm;

	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
		printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
#ifdef CONFIG_DEBUG_DOUBLEFAULT
		printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
			(int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
		printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
		printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
#endif
		printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
			init_retx_coreb);
	}

	/*
	 * We want the D-cache to be enabled early, in case the atomic
	 * support code emulates cache coherence (see
	 * __ARCH_SYNC_CORE_DCACHE).
	 */
	init_exception_vectors();

	bfin_setup_caches(cpu);

	local_irq_disable();

	/* Attach the new idle task to the global mm. */
	atomic_inc(&mm->mm_users);
	atomic_inc(&mm->mm_count);
	current->active_mm = mm;
	BUG_ON(current->mm);	/* Can't be, but better be safe than sorry. */

	preempt_disable();

	setup_secondary(cpu);

	local_irq_enable();

	platform_secondary_init(cpu);

	cpu_idle();
}

void __init smp_prepare_boot_cpu(void)
{
}

void __init smp_prepare_cpus(unsigned int max_cpus)
{
	platform_prepare_cpus(max_cpus);
	ipi_queue_init();
	platform_request_ipi(&ipi_handler);
}

void __init smp_cpus_done(unsigned int max_cpus)
{
	unsigned long bogosum = 0;
	unsigned int cpu;

	for_each_online_cpu(cpu)
		bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;

	printk(KERN_INFO "SMP: Total of %d processors activated "
	       "(%lu.%02lu BogoMIPS).\n",
	       num_online_cpus(),
	       bogosum / (500000/HZ),
	       (bogosum / (5000/HZ)) % 100);
}

void smp_icache_flush_range_others(unsigned long start, unsigned long end)
{
	smp_flush_data.start = start;
	smp_flush_data.end = end;

	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
		printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
}
EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);

#ifdef __ARCH_SYNC_CORE_DCACHE
unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));

void resync_core_dcache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_dcache();
	++per_cpu(cpu_data, cpu).dcache_invld_count;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_dcache);
#endif
Commit	Line	Data
6b3087c6 GY	1	/*
	2	* File: arch/blackfin/kernel/smp.c
	3	* Author: Philippe Gerum <rpm@xenomai.org>
	4	* IPI management based on arch/arm/kernel/smp.c.
	5	*
	6	* Copyright 2007 Analog Devices Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, see the file COPYING, or write
	20	* to the Free Software Foundation, Inc.,
	21	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	22	*/
	23
	24	#include <linux/module.h>
	25	#include <linux/delay.h>
	26	#include <linux/init.h>
	27	#include <linux/spinlock.h>
	28	#include <linux/sched.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/cache.h>
	31	#include <linux/profile.h>
	32	#include <linux/errno.h>
	33	#include <linux/mm.h>
	34	#include <linux/cpu.h>
	35	#include <linux/smp.h>
	36	#include <linux/seq_file.h>
	37	#include <linux/irq.h>
	38	#include <asm/atomic.h>
	39	#include <asm/cacheflush.h>
	40	#include <asm/mmu_context.h>
	41	#include <asm/pgtable.h>
	42	#include <asm/pgalloc.h>
	43	#include <asm/processor.h>
	44	#include <asm/ptrace.h>
	45	#include <asm/cpu.h>
	46	#include <linux/err.h>
	47
555487bb GY	48	/*
	49	* Anomaly notes:
	50	* 05000120 - we always define corelock as 32-bit integer in L2
	51	*/
6b3087c6 GY	52	struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
	53
	54	void __cpuinitdata init_retx_coreb, init_saved_retx_coreb,
	55	init_saved_seqstat_coreb, init_saved_icplb_fault_addr_coreb,
	56	*init_saved_dcplb_fault_addr_coreb;
	57
	58	cpumask_t cpu_possible_map;
	59	EXPORT_SYMBOL(cpu_possible_map);
	60
	61	cpumask_t cpu_online_map;
	62	EXPORT_SYMBOL(cpu_online_map);
	63
	64	#define BFIN_IPI_RESCHEDULE 0
	65	#define BFIN_IPI_CALL_FUNC 1
	66	#define BFIN_IPI_CPU_STOP 2
	67
	68	struct blackfin_flush_data {
	69	unsigned long start;
	70	unsigned long end;
	71	};
	72
	73	void *secondary_stack;
	74
	75
	76	struct smp_call_struct {
	77	void (func)(void info);
	78	void *info;
	79	int wait;
	80	cpumask_t pending;
	81	cpumask_t waitmask;
	82	};
	83
	84	static struct blackfin_flush_data smp_flush_data;
	85
	86	static DEFINE_SPINLOCK(stop_lock);
	87
	88	struct ipi_message {
	89	struct list_head list;
	90	unsigned long type;
	91	struct smp_call_struct call_struct;
	92	};
	93
	94	struct ipi_message_queue {
	95	struct list_head head;
	96	spinlock_t lock;
	97	unsigned long count;
	98	};
	99
	100	static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
	101
	102	static void ipi_cpu_stop(unsigned int cpu)
	103	{
	104	spin_lock(&stop_lock);
	105	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	106	dump_stack();
	107	spin_unlock(&stop_lock);
	108
	109	cpu_clear(cpu, cpu_online_map);
	110
	111	local_irq_disable();
	112
	113	while (1)
	114	SSYNC();
	115	}
116
117	static void ipi_flush_icache(void *info)
118	{
119	struct blackfin_flush_data *fdata = info;
120
121	/* Invalidate the memory holding the bounds of the flushed region. */
122	blackfin_dcache_invalidate_range((unsigned long)fdata,
123	(unsigned long)fdata + sizeof(*fdata));
124
125	blackfin_icache_flush_range(fdata->start, fdata->end);
126	}
127
128	static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
129	{
130	int wait;
131	void (func)(void info);
132	void *info;
133	func = msg->call_struct.func;
134	info = msg->call_struct.info;
135	wait = msg->call_struct.wait;
136	cpu_clear(cpu, msg->call_struct.pending);
137	func(info);
138	if (wait)
139	cpu_clear(cpu, msg->call_struct.waitmask);
140	else
141	kfree(msg);
142	}
143
144	static irqreturn_t ipi_handler(int irq, void *dev_instance)
145	{
146	struct ipi_message msg, mg;
147	struct ipi_message_queue *msg_queue;
148	unsigned int cpu = smp_processor_id();
149
150	platform_clear_ipi(cpu);
151
152	msg_queue = &__get_cpu_var(ipi_msg_queue);
153	msg_queue->count++;
154
155	spin_lock(&msg_queue->lock);
156	list_for_each_entry_safe(msg, mg, &msg_queue->head, list) {
157	list_del(&msg->list);
158	switch (msg->type) {
159	case BFIN_IPI_RESCHEDULE:
160	/* That's the easiest one; leave it to
161	* return_from_int. */
162	kfree(msg);
163	break;
164	case BFIN_IPI_CALL_FUNC:
0bf3d933	165	spin_unlock(&msg_queue->lock);
6b3087c6	166	ipi_call_function(cpu, msg);
0bf3d933	167	spin_lock(&msg_queue->lock);
6b3087c6 GY	168	break;
6b3087c6 GY	169	case BFIN_IPI_CPU_STOP:
0bf3d933	170	spin_unlock(&msg_queue->lock);
6b3087c6	171	ipi_cpu_stop(cpu);
0bf3d933	172	spin_lock(&msg_queue->lock);
6b3087c6 GY	173	kfree(msg);
	174	break;
	175	default:
	176	printk(KERN_CRIT "CPU%u: Unknown IPI message \
	177	0x%lx\n", cpu, msg->type);
	178	kfree(msg);
	179	break;
	180	}
	181	}
	182	spin_unlock(&msg_queue->lock);
	183	return IRQ_HANDLED;
	184	}
	185
	186	static void ipi_queue_init(void)
	187	{
	188	unsigned int cpu;
	189	struct ipi_message_queue *msg_queue;
	190	for_each_possible_cpu(cpu) {
	191	msg_queue = &per_cpu(ipi_msg_queue, cpu);
	192	INIT_LIST_HEAD(&msg_queue->head);
	193	spin_lock_init(&msg_queue->lock);
	194	msg_queue->count = 0;
	195	}
	196	}
	197
	198	int smp_call_function(void (func)(void info), void *info, int wait)
	199	{
	200	unsigned int cpu;
	201	cpumask_t callmap;
	202	unsigned long flags;
	203	struct ipi_message_queue *msg_queue;
	204	struct ipi_message *msg;
	205
	206	callmap = cpu_online_map;
	207	cpu_clear(smp_processor_id(), callmap);
	208	if (cpus_empty(callmap))
	209	return 0;
	210
	211	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
	212	INIT_LIST_HEAD(&msg->list);
	213	msg->call_struct.func = func;
	214	msg->call_struct.info = info;
	215	msg->call_struct.wait = wait;
	216	msg->call_struct.pending = callmap;
	217	msg->call_struct.waitmask = callmap;
	218	msg->type = BFIN_IPI_CALL_FUNC;
	219
	220	for_each_cpu_mask(cpu, callmap) {
	221	msg_queue = &per_cpu(ipi_msg_queue, cpu);
	222	spin_lock_irqsave(&msg_queue->lock, flags);
	223	list_add(&msg->list, &msg_queue->head);
	224	spin_unlock_irqrestore(&msg_queue->lock, flags);
	225	platform_send_ipi_cpu(cpu);
	226	}
	227	if (wait) {
	228	while (!cpus_empty(msg->call_struct.waitmask))
	229	blackfin_dcache_invalidate_range(
	230	(unsigned long)(&msg->call_struct.waitmask),
	231	(unsigned long)(&msg->call_struct.waitmask));
	232	kfree(msg);
	233	}
	234	return 0;
	235	}
	236	EXPORT_SYMBOL_GPL(smp_call_function);
237
238	int smp_call_function_single(int cpuid, void (func) (void info), void *info,
239	int wait)
240	{
241	unsigned int cpu = cpuid;
242	cpumask_t callmap;
243	unsigned long flags;
244	struct ipi_message_queue *msg_queue;
245	struct ipi_message *msg;
246
247	if (cpu_is_offline(cpu))
248	return 0;
249	cpus_clear(callmap);
250	cpu_set(cpu, callmap);
251
252	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
253	INIT_LIST_HEAD(&msg->list);
254	msg->call_struct.func = func;
255	msg->call_struct.info = info;
256	msg->call_struct.wait = wait;
257	msg->call_struct.pending = callmap;
258	msg->call_struct.waitmask = callmap;
259	msg->type = BFIN_IPI_CALL_FUNC;
260
261	msg_queue = &per_cpu(ipi_msg_queue, cpu);
262	spin_lock_irqsave(&msg_queue->lock, flags);
263	list_add(&msg->list, &msg_queue->head);
264	spin_unlock_irqrestore(&msg_queue->lock, flags);
265	platform_send_ipi_cpu(cpu);
266
267	if (wait) {
268	while (!cpus_empty(msg->call_struct.waitmask))
269	blackfin_dcache_invalidate_range(
270	(unsigned long)(&msg->call_struct.waitmask),
271	(unsigned long)(&msg->call_struct.waitmask));
272	kfree(msg);
273	}
274	return 0;
275	}
276	EXPORT_SYMBOL_GPL(smp_call_function_single);
277
278	void smp_send_reschedule(int cpu)
279	{
280	unsigned long flags;
281	struct ipi_message_queue *msg_queue;
282	struct ipi_message *msg;
283
284	if (cpu_is_offline(cpu))
285	return;
286
287	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
288	memset(msg, 0, sizeof(msg));
289	INIT_LIST_HEAD(&msg->list);
290	msg->type = BFIN_IPI_RESCHEDULE;
291
292	msg_queue = &per_cpu(ipi_msg_queue, cpu);
293	spin_lock_irqsave(&msg_queue->lock, flags);
294	list_add(&msg->list, &msg_queue->head);
295	spin_unlock_irqrestore(&msg_queue->lock, flags);
296	platform_send_ipi_cpu(cpu);
297
298	return;
299	}
300
301	void smp_send_stop(void)
302	{
303	unsigned int cpu;
304	cpumask_t callmap;
305	unsigned long flags;
306	struct ipi_message_queue *msg_queue;
307	struct ipi_message *msg;
308
309	callmap = cpu_online_map;
310	cpu_clear(smp_processor_id(), callmap);
311	if (cpus_empty(callmap))
312	return;
313
314	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
315	memset(msg, 0, sizeof(msg));
316	INIT_LIST_HEAD(&msg->list);
317	msg->type = BFIN_IPI_CPU_STOP;
318
319	for_each_cpu_mask(cpu, callmap) {
320	msg_queue = &per_cpu(ipi_msg_queue, cpu);
321	spin_lock_irqsave(&msg_queue->lock, flags);
322	list_add(&msg->list, &msg_queue->head);
323	spin_unlock_irqrestore(&msg_queue->lock, flags);
324	platform_send_ipi_cpu(cpu);
325	}
326	return;
327	}
328
329	int __cpuinit __cpu_up(unsigned int cpu)
330	{
331	struct task_struct *idle;
332	int ret;
333
334	idle = fork_idle(cpu);
335	if (IS_ERR(idle)) {
336	printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
337	return PTR_ERR(idle);
338	}
339
340	secondary_stack = task_stack_page(idle) + THREAD_SIZE;
341	smp_wmb();
342
343	ret = platform_boot_secondary(cpu, idle);
344
345	if (ret) {
346	cpu_clear(cpu, cpu_present_map);
347	printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
348	free_task(idle);
349	} else
350	cpu_set(cpu, cpu_online_map);
351
352	secondary_stack = NULL;
353
354	return ret;
355	}
356
357	static void __cpuinit setup_secondary(unsigned int cpu)
358	{
6a01f230	359	#if !(defined(CONFIG_TICK_SOURCE_SYSTMR0) \|\| defined(CONFIG_IPIPE))
6b3087c6 GY	360	struct irq_desc *timer_desc;
	361	#endif
	362	unsigned long ilat;
	363
	364	bfin_write_IMASK(0);
	365	CSYNC();
	366	ilat = bfin_read_ILAT();
	367	CSYNC();
	368	bfin_write_ILAT(ilat);
	369	CSYNC();
	370
	371	/* Reserve the PDA space for the secondary CPU. */
	372	reserve_pda();
	373
	374	/* Enable interrupt levels IVG7-15. IARs have been already
	375	* programmed by the boot CPU. */
40059784	376	bfin_irq_flags \|= IMASK_IVG15 \|
6b3087c6 GY	377	IMASK_IVG14 \| IMASK_IVG13 \| IMASK_IVG12 \| IMASK_IVG11 \|
	378	IMASK_IVG10 \| IMASK_IVG9 \| IMASK_IVG8 \| IMASK_IVG7 \| IMASK_IVGHW;
	379
6a01f230	380	#if defined(CONFIG_TICK_SOURCE_SYSTMR0) \|\| defined(CONFIG_IPIPE)
6b3087c6 GY	381	/* Power down the core timer, just to play safe. */
	382	bfin_write_TCNTL(0);
	383
	384	/* system timer0 has been setup by CoreA. */
	385	#else
	386	timer_desc = irq_desc + IRQ_CORETMR;
	387	setup_core_timer();
	388	timer_desc->chip->enable(IRQ_CORETMR);
	389	#endif
	390	}
	391
	392	void __cpuinit secondary_start_kernel(void)
	393	{
	394	unsigned int cpu = smp_processor_id();
	395	struct mm_struct *mm = &init_mm;
	396
	397	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
	398	printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
	399	#ifdef CONFIG_DEBUG_DOUBLEFAULT
	400	printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
	401	(int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
	402	printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
	403	printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
	404	#endif
	405	printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
	406	init_retx_coreb);
	407	}
	408
	409	/*
	410	* We want the D-cache to be enabled early, in case the atomic
	411	* support code emulates cache coherence (see
	412	* __ARCH_SYNC_CORE_DCACHE).
	413	*/
	414	init_exception_vectors();
	415
	416	bfin_setup_caches(cpu);
	417
	418	local_irq_disable();
	419
	420	/* Attach the new idle task to the global mm. */
	421	atomic_inc(&mm->mm_users);
	422	atomic_inc(&mm->mm_count);
	423	current->active_mm = mm;
	424	BUG_ON(current->mm); /* Can't be, but better be safe than sorry. */
	425
	426	preempt_disable();
	427
	428	setup_secondary(cpu);
	429
	430	local_irq_enable();
	431
	432	platform_secondary_init(cpu);
	433
	434	cpu_idle();
	435	}
	436
	437	void __init smp_prepare_boot_cpu(void)
	438	{
	439	}
	440
	441	void __init smp_prepare_cpus(unsigned int max_cpus)
	442	{
	443	platform_prepare_cpus(max_cpus);
	444	ipi_queue_init();
445	platform_request_ipi(&ipi_handler);
446	}
447
448	void __init smp_cpus_done(unsigned int max_cpus)
449	{
450	unsigned long bogosum = 0;
451	unsigned int cpu;
452
453	for_each_online_cpu(cpu)
454	bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
455
456	printk(KERN_INFO "SMP: Total of %d processors activated "
457	"(%lu.%02lu BogoMIPS).\n",
458	num_online_cpus(),
459	bogosum / (500000/HZ),
460	(bogosum / (5000/HZ)) % 100);
461	}
462
463	void smp_icache_flush_range_others(unsigned long start, unsigned long end)
464	{
465	smp_flush_data.start = start;
466	smp_flush_data.end = end;
467
0bf3d933	468	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
6b3087c6 GY	469	printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
	470	}
	471	EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
	472
	473	#ifdef __ARCH_SYNC_CORE_DCACHE
	474	unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
	475
	476	void resync_core_dcache(void)
	477	{
	478	unsigned int cpu = get_cpu();
	479	blackfin_invalidate_entire_dcache();
	480	++per_cpu(cpu_data, cpu).dcache_invld_count;
	481	put_cpu();
	482	}
	483	EXPORT_SYMBOL(resync_core_dcache);
	484	#endif