[net-next-2.6.git] / arch / blackfin / mach-common / head.S

/*
 * Common Blackfin startup code
 *
 * Copyright 2004-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/thread_info.h>
#include <asm/trace.h>
#include <asm/asm-offsets.h>

__INIT

#define INITIAL_STACK	(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)

ENTRY(__start)
	/* R0: argument of command line string, passed from uboot, save it */
	R7 = R0;
	/* Enable Cycle Counter and Nesting Of Interrupts */
#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	R0 = SYSCFG_SNEN;
#else
	R0 = SYSCFG_SNEN | SYSCFG_CCEN;
#endif
	SYSCFG = R0;
	R0 = 0;

	/* Clear Out All the data and pointer Registers */
	R1 = R0;
	R2 = R0;
	R3 = R0;
	R4 = R0;
	R5 = R0;
	R6 = R0;

	P0 = R0;
	P1 = R0;
	P2 = R0;
	P3 = R0;
	P4 = R0;
	P5 = R0;

	LC0 = r0;
	LC1 = r0;
	L0 = r0;
	L1 = r0;
	L2 = r0;
	L3 = r0;

	/* Clear Out All the DAG Registers */
	B0 = r0;
	B1 = r0;
	B2 = r0;
	B3 = r0;

	I0 = r0;
	I1 = r0;
	I2 = r0;
	I3 = r0;

	M0 = r0;
	M1 = r0;
	M2 = r0;
	M3 = r0;

	/*
	 * Clear ITEST_COMMAND and DTEST_COMMAND registers,
	 * Leaving these as non-zero can confuse the emulator
	 */
	p0.L = LO(DTEST_COMMAND);
	p0.H = HI(DTEST_COMMAND);
	[p0] = R0;
	[p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0;
	CSYNC;

	trace_buffer_init(p0,r0);
	P0 = R1;
	R0 = R1;

	/* Turn off the icache */
	p0.l = LO(IMEM_CONTROL);
	p0.h = HI(IMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENICPLB;
	R0 = R0 & R1;
	[p0] = R0;
	SSYNC;

	/* Turn off the dcache */
	p0.l = LO(DMEM_CONTROL);
	p0.h = HI(DMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENDCPLB;
	R0 = R0 & R1;
	[p0] = R0;
	SSYNC;

	/* in case of double faults, save a few things */
	p0.l = _init_retx;
	p0.h = _init_retx;
	R0 = RETX;
	[P0] = R0;

#ifdef CONFIG_DEBUG_DOUBLEFAULT
	/* Only save these if we are storing them,
	 * This happens here, since L1 gets clobbered
	 * below
	 */
	GET_PDA(p0, r0);
	r7 = [p0 + PDA_RETX];
	p1.l = _init_saved_retx;
	p1.h = _init_saved_retx;
	[p1] = r7;

	r7 = [p0 + PDA_DCPLB];
	p1.l = _init_saved_dcplb_fault_addr;
	p1.h = _init_saved_dcplb_fault_addr;
	[p1] = r7;

	r7 = [p0 + PDA_ICPLB];
	p1.l = _init_saved_icplb_fault_addr;
	p1.h = _init_saved_icplb_fault_addr;
	[p1] = r7;

	r7 = [p0 + PDA_SEQSTAT];
	p1.l = _init_saved_seqstat;
	p1.h = _init_saved_seqstat;
	[p1] = r7;
#endif

	/* Initialize stack pointer */
	sp.l = lo(INITIAL_STACK);
	sp.h = hi(INITIAL_STACK);
	fp = sp;
	usp = sp;

#ifdef CONFIG_EARLY_PRINTK
	call _init_early_exception_vectors;
#endif

	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
	call _bfin_relocate_l1_mem;
#ifdef CONFIG_BFIN_KERNEL_CLOCK
	call _start_dma_code;
#endif

	/* This section keeps the processor in supervisor mode
	 * during kernel boot.  Switches to user mode at end of boot.
	 * See page 3-9 of Hardware Reference manual for documentation.
	 */

	/* EVT15 = _real_start */

	p0.l = lo(EVT15);
	p0.h = hi(EVT15);
	p1.l = _real_start;
	p1.h = _real_start;
	[p0] = p1;
	csync;

	r0 = EVT_IVG15 (z);
	sti r0;

	raise 15;
	p0.l = .LWAIT_HERE;
	p0.h = .LWAIT_HERE;
	reti = p0;
#if ANOMALY_05000281
	nop; nop; nop;
#endif
	rti;

.LWAIT_HERE:
	jump .LWAIT_HERE;
ENDPROC(__start)

/* A little BF561 glue ... */
#ifndef WDOG_CTL
# define WDOG_CTL WDOGA_CTL
#endif

ENTRY(__init_clear_bss)
	r2 = r2 - r1;
	cc = r2 == 0;
	if cc jump .L_bss_done;
	r2 >>= 2;
	p1 = r1;
	p2 = r2;
	lsetup (1f, 1f) lc0 = p2;
1:	[p1++] = r0;
.L_bss_done:
	rts;
ENDPROC(__init_clear_bss)

ENTRY(_real_start)
	/* Enable nested interrupts */
	[--sp] = reti;

	/* watchdog off for now */
	p0.l = lo(WDOG_CTL);
	p0.h = hi(WDOG_CTL);
	r0 = 0xAD6(z);
	w[p0] = r0;
	ssync;

	r0 = 0 (x);
	/* Zero out all of the fun bss regions */
#if L1_DATA_A_LENGTH > 0
	r1.l = __sbss_l1;
	r1.h = __sbss_l1;
	r2.l = __ebss_l1;
	r2.h = __ebss_l1;
	call __init_clear_bss
#endif
#if L1_DATA_B_LENGTH > 0
	r1.l = __sbss_b_l1;
	r1.h = __sbss_b_l1;
	r2.l = __ebss_b_l1;
	r2.h = __ebss_b_l1;
	call __init_clear_bss
#endif
#if L2_LENGTH > 0
	r1.l = __sbss_l2;
	r1.h = __sbss_l2;
	r2.l = __ebss_l2;
	r2.h = __ebss_l2;
	call __init_clear_bss
#endif
	r1.l = ___bss_start;
	r1.h = ___bss_start;
	r2.l = ___bss_stop;
	r2.h = ___bss_stop;
	call __init_clear_bss

	/* Pass the u-boot arguments to the global value command line */
	R0 = R7;
	call _cmdline_init;

	/* Load the current thread pointer and stack */
	sp.l = _init_thread_union;
	sp.h = _init_thread_union;
	p1 = THREAD_SIZE (z);
	sp = sp + p1;
	usp = sp;
	fp = sp;
	sp += -12;
	call _init_pda
	sp += 12;
	jump.l _start_kernel;
ENDPROC(_real_start)

__FINIT
Commit	Line	Data
09e1f70e MF	1	/*
	2	* Common Blackfin startup code
	3	*
	4	* Copyright 2004-2008 Analog Devices Inc.
	5	*
	6	* Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#include <linux/linkage.h>
	12	#include <linux/init.h>
	13	#include <asm/blackfin.h>
67618fd8	14	#include <asm/thread_info.h>
09e1f70e	15	#include <asm/trace.h>
6b3087c6	16	#include <asm/asm-offsets.h>
09e1f70e	17
17e89bcf MF	18	__INIT
	19
	20	#define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
	21
	22	ENTRY(__start)
	23	/* R0: argument of command line string, passed from uboot, save it */
	24	R7 = R0;
	25	/* Enable Cycle Counter and Nesting Of Interrupts */
	26	#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	27	R0 = SYSCFG_SNEN;
	28	#else
	29	R0 = SYSCFG_SNEN \| SYSCFG_CCEN;
	30	#endif
	31	SYSCFG = R0;
	32	R0 = 0;
	33
	34	/* Clear Out All the data and pointer Registers */
	35	R1 = R0;
	36	R2 = R0;
	37	R3 = R0;
	38	R4 = R0;
	39	R5 = R0;
	40	R6 = R0;
	41
	42	P0 = R0;
	43	P1 = R0;
	44	P2 = R0;
	45	P3 = R0;
	46	P4 = R0;
	47	P5 = R0;
	48
	49	LC0 = r0;
	50	LC1 = r0;
	51	L0 = r0;
	52	L1 = r0;
	53	L2 = r0;
	54	L3 = r0;
	55
	56	/* Clear Out All the DAG Registers */
	57	B0 = r0;
	58	B1 = r0;
	59	B2 = r0;
	60	B3 = r0;
	61
	62	I0 = r0;
	63	I1 = r0;
	64	I2 = r0;
	65	I3 = r0;
	66
	67	M0 = r0;
	68	M1 = r0;
	69	M2 = r0;
	70	M3 = r0;
	71
9df10281 RG	72	/*
	73	* Clear ITEST_COMMAND and DTEST_COMMAND registers,
	74	* Leaving these as non-zero can confuse the emulator
	75	*/
	76	p0.L = LO(DTEST_COMMAND);
	77	p0.H = HI(DTEST_COMMAND);
	78	[p0] = R0;
	79	[p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0;
	80	CSYNC;
	81
17e89bcf MF	82	trace_buffer_init(p0,r0);
	83	P0 = R1;
	84	R0 = R1;
	85
	86	/* Turn off the icache */
	87	p0.l = LO(IMEM_CONTROL);
	88	p0.h = HI(IMEM_CONTROL);
	89	R1 = [p0];
	90	R0 = ~ENICPLB;
	91	R0 = R0 & R1;
	92	[p0] = R0;
	93	SSYNC;
	94
	95	/* Turn off the dcache */
	96	p0.l = LO(DMEM_CONTROL);
	97	p0.h = HI(DMEM_CONTROL);
	98	R1 = [p0];
	99	R0 = ~ENDCPLB;
	100	R0 = R0 & R1;
	101	[p0] = R0;
	102	SSYNC;
	103
0c7a6b21 RG	104	/* in case of double faults, save a few things */
	105	p0.l = _init_retx;
	106	p0.h = _init_retx;
cd8fb8df RG	107	R0 = RETX;
	108	[P0] = R0;
	109
0c7a6b21 RG	110	#ifdef CONFIG_DEBUG_DOUBLEFAULT
	111	/* Only save these if we are storing them,
	112	* This happens here, since L1 gets clobbered
	113	* below
	114	*/
6b3087c6 GY	115	GET_PDA(p0, r0);
6b3087c6 GY	116	r7 = [p0 + PDA_RETX];
0c7a6b21 RG	117	p1.l = _init_saved_retx;
0c7a6b21 RG	118	p1.h = _init_saved_retx;
6b3087c6	119	[p1] = r7;
0c7a6b21	120
6b3087c6	121	r7 = [p0 + PDA_DCPLB];
0c7a6b21 RG	122	p1.l = _init_saved_dcplb_fault_addr;
0c7a6b21 RG	123	p1.h = _init_saved_dcplb_fault_addr;
6b3087c6	124	[p1] = r7;
0c7a6b21	125
6b3087c6	126	r7 = [p0 + PDA_ICPLB];
0c7a6b21 RG	127	p1.l = _init_saved_icplb_fault_addr;
0c7a6b21 RG	128	p1.h = _init_saved_icplb_fault_addr;
6b3087c6	129	[p1] = r7;
0c7a6b21	130
6b3087c6	131	r7 = [p0 + PDA_SEQSTAT];
0c7a6b21 RG	132	p1.l = _init_saved_seqstat;
0c7a6b21 RG	133	p1.h = _init_saved_seqstat;
6b3087c6	134	[p1] = r7;
0c7a6b21 RG	135	#endif
0c7a6b21 RG	136
17e89bcf MF	137	/* Initialize stack pointer */
	138	sp.l = lo(INITIAL_STACK);
	139	sp.h = hi(INITIAL_STACK);
	140	fp = sp;
	141	usp = sp;
	142
	143	#ifdef CONFIG_EARLY_PRINTK
	144	call _init_early_exception_vectors;
	145	#endif
	146
	147	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
5b04f271	148	call _bfin_relocate_l1_mem;
17e89bcf MF	149	#ifdef CONFIG_BFIN_KERNEL_CLOCK
	150	call _start_dma_code;
	151	#endif
	152
	153	/* This section keeps the processor in supervisor mode
	154	* during kernel boot. Switches to user mode at end of boot.
	155	* See page 3-9 of Hardware Reference manual for documentation.
	156	*/
	157
	158	/* EVT15 = _real_start */
	159
	160	p0.l = lo(EVT15);
	161	p0.h = hi(EVT15);
	162	p1.l = _real_start;
	163	p1.h = _real_start;
	164	[p0] = p1;
	165	csync;
	166
c2414bd0 MF	167	r0 = EVT_IVG15 (z);
c2414bd0 MF	168	sti r0;
17e89bcf MF	169
	170	raise 15;
	171	p0.l = .LWAIT_HERE;
	172	p0.h = .LWAIT_HERE;
	173	reti = p0;
	174	#if ANOMALY_05000281
	175	nop; nop; nop;
	176	#endif
	177	rti;
	178
	179	.LWAIT_HERE:
	180	jump .LWAIT_HERE;
	181	ENDPROC(__start)
	182
09e1f70e MF	183	/* A little BF561 glue ... */
	184	#ifndef WDOG_CTL
	185	# define WDOG_CTL WDOGA_CTL
	186	#endif
	187
f940260a MF	188	ENTRY(__init_clear_bss)
	189	r2 = r2 - r1;
	190	cc = r2 == 0;
	191	if cc jump .L_bss_done;
	192	r2 >>= 2;
	193	p1 = r1;
	194	p2 = r2;
	195	lsetup (1f, 1f) lc0 = p2;
	196	1: [p1++] = r0;
	197	.L_bss_done:
	198	rts;
	199	ENDPROC(__init_clear_bss)
	200
09e1f70e MF	201	ENTRY(_real_start)
	202	/* Enable nested interrupts */
	203	[--sp] = reti;
	204
	205	/* watchdog off for now */
	206	p0.l = lo(WDOG_CTL);
	207	p0.h = hi(WDOG_CTL);
	208	r0 = 0xAD6(z);
	209	w[p0] = r0;
	210	ssync;
	211
f940260a MF	212	r0 = 0 (x);
f940260a MF	213	/* Zero out all of the fun bss regions */
b4f5c58f GY	214	#if L1_DATA_A_LENGTH > 0
	215	r1.l = __sbss_l1;
	216	r1.h = __sbss_l1;
	217	r2.l = __ebss_l1;
	218	r2.h = __ebss_l1;
f940260a	219	call __init_clear_bss
b4f5c58f	220	#endif
b4f5c58f GY	221	#if L1_DATA_B_LENGTH > 0
	222	r1.l = __sbss_b_l1;
	223	r1.h = __sbss_b_l1;
	224	r2.l = __ebss_b_l1;
	225	r2.h = __ebss_b_l1;
f940260a	226	call __init_clear_bss
b4f5c58f	227	#endif
b4f5c58f GY	228	#if L2_LENGTH > 0
	229	r1.l = __sbss_l2;
	230	r1.h = __sbss_l2;
	231	r2.l = __ebss_l2;
	232	r2.h = __ebss_l2;
f940260a	233	call __init_clear_bss
b4f5c58f	234	#endif
09e1f70e MF	235	r1.l = ___bss_start;
	236	r1.h = ___bss_start;
	237	r2.l = ___bss_stop;
	238	r2.h = ___bss_stop;
f940260a	239	call __init_clear_bss
09e1f70e	240
09e1f70e MF	241	/* Pass the u-boot arguments to the global value command line */
	242	R0 = R7;
	243	call _cmdline_init;
	244
	245	/* Load the current thread pointer and stack */
	246	sp.l = _init_thread_union;
	247	sp.h = _init_thread_union;
	248	p1 = THREAD_SIZE (z);
	249	sp = sp + p1;
	250	usp = sp;
	251	fp = sp;
6b3087c6 GY	252	sp += -12;
	253	call _init_pda
	254	sp += 12;
09e1f70e MF	255	jump.l _start_kernel;
	256	ENDPROC(_real_start)
	257
	258	__FINIT