[net-next-2.6.git] / arch / blackfin / mach-bf561 / smp.c

/*
 * Copyright 2007-2009 Analog Devices Inc.
 *               Philippe Gerum <rpm@xenomai.org>
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <asm/smp.h>
#include <asm/dma.h>
#include <asm/time.h>

static DEFINE_SPINLOCK(boot_lock);

/*
 * platform_init_cpus() - Tell the world about how many cores we
 * have. This is called while setting up the architecture support
 * (setup_arch()), so don't be too demanding here with respect to
 * available kernel services.
 */

void __init platform_init_cpus(void)
{
	cpu_set(0, cpu_possible_map); /* CoreA */
	cpu_set(1, cpu_possible_map); /* CoreB */
}

void __init platform_prepare_cpus(unsigned int max_cpus)
{
	int len;

	len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
	BUG_ON(len > L1_CODE_LENGTH);

	dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);

	/* Both cores ought to be present on a bf561! */
	cpu_set(0, cpu_present_map); /* CoreA */
	cpu_set(1, cpu_present_map); /* CoreB */

	printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
}

int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
{
	return -EINVAL;
}

void __cpuinit platform_secondary_init(unsigned int cpu)
{
	/* Clone setup for peripheral interrupt sources from CoreA. */
	bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
	bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
	SSYNC();

	/* Clone setup for IARs from CoreA. */
	bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
	bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
	bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
	bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
	bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
	bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
	bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
	bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
	bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
	bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
	SSYNC();

	/* Store CPU-private information to the cpu_data array. */
	bfin_setup_cpudata(cpu);

	/* We are done with local CPU inits, unblock the boot CPU. */
	set_cpu_online(cpu, true);
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}

int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	unsigned long timeout;

	printk(KERN_INFO "Booting Core B.\n");

	spin_lock(&boot_lock);

	if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) {
		/* CoreB already running, sending ipi to wakeup it */
		platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
	} else {
		/* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
		bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
		SSYNC();
	}

	timeout = jiffies + 1 * HZ;
	while (time_before(jiffies, timeout)) {
		if (cpu_online(cpu))
			break;
		udelay(100);
		barrier();
	}

	if (cpu_online(cpu)) {
		/* release the lock and let coreb run */
		spin_unlock(&boot_lock);
		return 0;
	} else
		panic("CPU%u: processor failed to boot\n", cpu);
}

void __init platform_request_ipi(irq_handler_t handler)
{
	int ret;

	ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
			  "Supplemental Interrupt0", handler);
	if (ret)
		panic("Cannot request supplemental interrupt 0 for IPI service");
}

void platform_send_ipi(cpumask_t callmap)
{
	unsigned int cpu;

	for_each_cpu_mask(cpu, callmap) {
		BUG_ON(cpu >= 2);
		SSYNC();
		bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
		SSYNC();
	}
}

void platform_send_ipi_cpu(unsigned int cpu)
{
	BUG_ON(cpu >= 2);
	SSYNC();
	bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
	SSYNC();
}

void platform_clear_ipi(unsigned int cpu)
{
	BUG_ON(cpu >= 2);
	SSYNC();
	bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
	SSYNC();
}

/*
 * Setup core B's local core timer.
 * In SMP, core timer is used for clock event device.
 */
void __cpuinit bfin_local_timer_setup(void)
{
#if defined(CONFIG_TICKSOURCE_CORETMR)
	bfin_coretmr_init();
	bfin_coretmr_clockevent_init();
	get_irq_chip(IRQ_CORETMR)->unmask(IRQ_CORETMR);
#else
	/* Power down the core timer, just to play safe. */
	bfin_write_TCNTL(0);
#endif

}
Commit	Line	Data
c51b4488	1	/*
96f1050d RG	2	* Copyright 2007-2009 Analog Devices Inc.
96f1050d RG	3	* Philippe Gerum <rpm@xenomai.org>
c51b4488	4	*
96f1050d	5	* Licensed under the GPL-2 or later.
c51b4488 GY	6	*/
	7
	8	#include <linux/init.h>
	9	#include <linux/kernel.h>
	10	#include <linux/sched.h>
	11	#include <linux/delay.h>
	12	#include <asm/smp.h>
	13	#include <asm/dma.h>
0d152c27	14	#include <asm/time.h>
c51b4488	15
c51b4488 GY	16	static DEFINE_SPINLOCK(boot_lock);
c51b4488 GY	17
c51b4488 GY	18	/*
	19	* platform_init_cpus() - Tell the world about how many cores we
	20	* have. This is called while setting up the architecture support
	21	* (setup_arch()), so don't be too demanding here with respect to
	22	* available kernel services.
	23	*/
	24
	25	void __init platform_init_cpus(void)
	26	{
	27	cpu_set(0, cpu_possible_map); /* CoreA */
	28	cpu_set(1, cpu_possible_map); /* CoreB */
	29	}
	30
	31	void __init platform_prepare_cpus(unsigned int max_cpus)
	32	{
	33	int len;
	34
	35	len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
dbc895f9	36	BUG_ON(len > L1_CODE_LENGTH);
c51b4488	37
dbc895f9	38	dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
c51b4488 GY	39
	40	/* Both cores ought to be present on a bf561! */
	41	cpu_set(0, cpu_present_map); /* CoreA */
	42	cpu_set(1, cpu_present_map); /* CoreB */
	43
dbc895f9	44	printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
c51b4488 GY	45	}
	46
	47	int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
	48	{
	49	return -EINVAL;
	50	}
	51
	52	void __cpuinit platform_secondary_init(unsigned int cpu)
	53	{
c51b4488 GY	54	/* Clone setup for peripheral interrupt sources from CoreA. */
	55	bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
	56	bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
	57	SSYNC();
	58
	59	/* Clone setup for IARs from CoreA. */
	60	bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
	61	bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
	62	bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
	63	bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
	64	bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
	65	bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
	66	bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
	67	bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
0b39db28 GY	68	bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
0b39db28 GY	69	bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
c51b4488 GY	70	SSYNC();
c51b4488 GY	71
c51b4488 GY	72	/* Store CPU-private information to the cpu_data array. */
	73	bfin_setup_cpudata(cpu);
	74
	75	/* We are done with local CPU inits, unblock the boot CPU. */
682f5dc4	76	set_cpu_online(cpu, true);
c51b4488 GY	77	spin_lock(&boot_lock);
	78	spin_unlock(&boot_lock);
	79	}
	80
	81	int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
	82	{
	83	unsigned long timeout;
	84
c51b4488 GY	85	printk(KERN_INFO "Booting Core B.\n");
	86
	87	spin_lock(&boot_lock);
	88
0b39db28 GY	89	if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) {
	90	/* CoreB already running, sending ipi to wakeup it */
	91	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
	92	} else {
	93	/* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
	94	bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
	95	SSYNC();
	96	}
c51b4488 GY	97
	98	timeout = jiffies + 1 * HZ;
	99	while (time_before(jiffies, timeout)) {
682f5dc4	100	if (cpu_online(cpu))
c51b4488 GY	101	break;
	102	udelay(100);
	103	barrier();
	104	}
	105
682f5dc4	106	if (cpu_online(cpu)) {
578d36f5 YL	107	/* release the lock and let coreb run */
	108	spin_unlock(&boot_lock);
	109	return 0;
	110	} else
	111	panic("CPU%u: processor failed to boot\n", cpu);
c51b4488 GY	112	}
	113
	114	void __init platform_request_ipi(irq_handler_t handler)
	115	{
	116	int ret;
	117
	118	ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
1fa9be72	119	"Supplemental Interrupt0", handler);
c51b4488	120	if (ret)
d8804adf	121	panic("Cannot request supplemental interrupt 0 for IPI service");
c51b4488 GY	122	}
	123
	124	void platform_send_ipi(cpumask_t callmap)
	125	{
	126	unsigned int cpu;
	127
	128	for_each_cpu_mask(cpu, callmap) {
	129	BUG_ON(cpu >= 2);
	130	SSYNC();
	131	bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() \| (1 << (6 + cpu)));
	132	SSYNC();
	133	}
	134	}
	135
	136	void platform_send_ipi_cpu(unsigned int cpu)
	137	{
	138	BUG_ON(cpu >= 2);
	139	SSYNC();
	140	bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() \| (1 << (6 + cpu)));
	141	SSYNC();
	142	}
	143
	144	void platform_clear_ipi(unsigned int cpu)
	145	{
	146	BUG_ON(cpu >= 2);
	147	SSYNC();
	148	bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() \| (1 << (10 + cpu)));
	149	SSYNC();
	150	}
0d152c27 YL	151
	152	/*
	153	* Setup core B's local core timer.
	154	* In SMP, core timer is used for clock event device.
	155	*/
	156	void __cpuinit bfin_local_timer_setup(void)
	157	{
	158	#if defined(CONFIG_TICKSOURCE_CORETMR)
	159	bfin_coretmr_init();
	160	bfin_coretmr_clockevent_init();
	161	get_irq_chip(IRQ_CORETMR)->unmask(IRQ_CORETMR);
	162	#else
	163	/* Power down the core timer, just to play safe. */
	164	bfin_write_TCNTL(0);
	165	#endif
	166
	167	}