[net-next-2.6.git] / arch / blackfin / mach-bf548 / include / mach / mem_map.h

/*
 * file:         include/asm-blackfin/mach-bf548/mem_map.h
 * based on:
 * author:
 *
 * created:
 * description:
 *	Memory MAP Common header file for blackfin BF537/6/4 of processors.
 * rev:
 *
 * modified:
 *
 * bugs:         enter bugs at http://blackfin.uclinux.org/
 *
 * this program is free software; you can redistribute it and/or modify
 * it under the terms of the gnu general public license as published by
 * the free software foundation; either version 2, or (at your option)
 * any later version.
 *
 * this program is distributed in the hope that it will be useful,
 * but without any warranty; without even the implied warranty of
 * merchantability or fitness for a particular purpose.  see the
 * gnu general public license for more details.
 *
 * you should have received a copy of the gnu general public license
 * along with this program; see the file copying.
 * if not, write to the free software foundation,
 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
 */

#ifndef _MEM_MAP_548_H_
#define _MEM_MAP_548_H_

#define COREMMR_BASE           0xFFE00000	 /* Core MMRs */
#define SYSMMR_BASE            0xFFC00000	 /* System MMRs */

/* Async Memory Banks */
#define ASYNC_BANK3_BASE	0x2C000000	 /* Async Bank 3 */
#define ASYNC_BANK3_SIZE	0x04000000	/* 64M */
#define ASYNC_BANK2_BASE	0x28000000	 /* Async Bank 2 */
#define ASYNC_BANK2_SIZE	0x04000000	/* 64M */
#define ASYNC_BANK1_BASE	0x24000000	 /* Async Bank 1 */
#define ASYNC_BANK1_SIZE	0x04000000	/* 64M */
#define ASYNC_BANK0_BASE	0x20000000	 /* Async Bank 0 */
#define ASYNC_BANK0_SIZE	0x04000000	/* 64M */

/* Boot ROM Memory */

#define BOOT_ROM_START		0xEF000000
#define BOOT_ROM_LENGTH		0x1000

/* L1 Instruction ROM */

#define L1_ROM_START		0xFFA14000
#define L1_ROM_LENGTH		0x10000

/* Level 1 Memory */

/* Memory Map for ADSP-BF548 processors */
#ifdef CONFIG_BFIN_ICACHE
#define BFIN_ICACHESIZE	(16*1024)
#else
#define BFIN_ICACHESIZE	(0*1024)
#endif

#define L1_CODE_START       0xFFA00000
#define L1_DATA_A_START     0xFF800000
#define L1_DATA_B_START     0xFF900000

#define L1_CODE_LENGTH      0xC000

#ifdef CONFIG_BFIN_DCACHE

#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH      0x8000
#define BFIN_DCACHESIZE	(16*1024)
#define BFIN_DSUPBANKS	1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
#define BFIN_DCACHESIZE	(32*1024)
#define BFIN_DSUPBANKS	2
#endif

#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      0x8000
#define L1_DATA_B_LENGTH      0x8000
#define BFIN_DCACHESIZE	(0*1024)
#define BFIN_DSUPBANKS	0
#endif /*CONFIG_BFIN_DCACHE*/

/* Level 2 Memory */
#define L2_START            0xFEB00000
#if defined(CONFIG_BF542)
# define L2_LENGTH          0
#elif defined(CONFIG_BF544)
# define L2_LENGTH          0x10000
#else
# define L2_LENGTH          0x20000
#endif

/* Scratch Pad Memory */

#define L1_SCRATCH_START	0xFFB00000
#define L1_SCRATCH_LENGTH	0x1000

#define get_l1_scratch_start_cpu(cpu)		L1_SCRATCH_START
#define get_l1_code_start_cpu(cpu)		L1_CODE_START
#define get_l1_data_a_start_cpu(cpu)		L1_DATA_A_START
#define get_l1_data_b_start_cpu(cpu)		L1_DATA_B_START
#define get_l1_scratch_start()			L1_SCRATCH_START
#define get_l1_code_start()			L1_CODE_START
#define get_l1_data_a_start()			L1_DATA_A_START
#define get_l1_data_b_start()			L1_DATA_B_START

#define GET_PDA_SAFE(preg)		\
	preg.l = _cpu_pda;		\
	preg.h = _cpu_pda;

#define GET_PDA(preg, dreg)	GET_PDA_SAFE(preg)

#endif/* _MEM_MAP_548_H_ */
Commit	Line	Data
088eec11 RH	1	/*
	2	* file: include/asm-blackfin/mach-bf548/mem_map.h
	3	* based on:
	4	* author:
	5	*
	6	* created:
	7	* description:
	8	* Memory MAP Common header file for blackfin BF537/6/4 of processors.
	9	* rev:
	10	*
	11	* modified:
	12	*
	13	* bugs: enter bugs at http://blackfin.uclinux.org/
	14	*
	15	* this program is free software; you can redistribute it and/or modify
	16	* it under the terms of the gnu general public license as published by
	17	* the free software foundation; either version 2, or (at your option)
	18	* any later version.
	19	*
	20	* this program is distributed in the hope that it will be useful,
	21	* but without any warranty; without even the implied warranty of
	22	* merchantability or fitness for a particular purpose. see the
	23	* gnu general public license for more details.
	24	*
	25	* you should have received a copy of the gnu general public license
	26	* along with this program; see the file copying.
	27	* if not, write to the free software foundation,
	28	* 59 temple place - suite 330, boston, ma 02111-1307, usa.
	29	*/
	30
	31	#ifndef _MEM_MAP_548_H_
	32	#define _MEM_MAP_548_H_
	33
	34	#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
	35	#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
	36
	37	/* Async Memory Banks */
	38	#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
	39	#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
	40	#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
	41	#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
	42	#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
	43	#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
	44	#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
	45	#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
	46
	47	/* Boot ROM Memory */
	48
	49	#define BOOT_ROM_START 0xEF000000
c3a9f435	50	#define BOOT_ROM_LENGTH 0x1000
088eec11	51
b0187854 MF	52	/* L1 Instruction ROM */
	53
	54	#define L1_ROM_START 0xFFA14000
	55	#define L1_ROM_LENGTH 0x10000
	56
088eec11 RH	57	/* Level 1 Memory */
	58
	59	/* Memory Map for ADSP-BF548 processors */
3bebca2d RG	60	#ifdef CONFIG_BFIN_ICACHE
3bebca2d RG	61	#define BFIN_ICACHESIZE (16*1024)
088eec11	62	#else
3bebca2d	63	#define BFIN_ICACHESIZE (0*1024)
088eec11 RH	64	#endif
	65
	66	#define L1_CODE_START 0xFFA00000
	67	#define L1_DATA_A_START 0xFF800000
	68	#define L1_DATA_B_START 0xFF900000
	69
	70	#define L1_CODE_LENGTH 0xC000
	71
3bebca2d	72	#ifdef CONFIG_BFIN_DCACHE
088eec11	73
3bebca2d	74	#ifdef CONFIG_BFIN_DCACHE_BANKA
088eec11 RH	75	#define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0)
	76	#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
	77	#define L1_DATA_B_LENGTH 0x8000
3bebca2d RG	78	#define BFIN_DCACHESIZE (16*1024)
3bebca2d RG	79	#define BFIN_DSUPBANKS 1
088eec11 RH	80	#else
	81	#define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0)
	82	#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
	83	#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
3bebca2d RG	84	#define BFIN_DCACHESIZE (32*1024)
3bebca2d RG	85	#define BFIN_DSUPBANKS 2
088eec11 RH	86	#endif
	87
	88	#else
	89	#define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)
	90	#define L1_DATA_A_LENGTH 0x8000
	91	#define L1_DATA_B_LENGTH 0x8000
3bebca2d RG	92	#define BFIN_DCACHESIZE (0*1024)
	93	#define BFIN_DSUPBANKS 0
	94	#endif /CONFIG_BFIN_DCACHE/
088eec11	95
c3a9f435	96	/* Level 2 Memory */
ad5dd977 MF	97	#define L2_START 0xFEB00000
	98	#if defined(CONFIG_BF542)
	99	# define L2_LENGTH 0
	100	#elif defined(CONFIG_BF544)
	101	# define L2_LENGTH 0x10000
	102	#else
	103	# define L2_LENGTH 0x20000
c3a9f435 MF	104	#endif
c3a9f435 MF	105
088eec11 RH	106	/* Scratch Pad Memory */
088eec11 RH	107
088eec11 RH	108	#define L1_SCRATCH_START 0xFFB00000
088eec11 RH	109	#define L1_SCRATCH_LENGTH 0x1000
088eec11	110
46fa5eec GY	111	#define get_l1_scratch_start_cpu(cpu) L1_SCRATCH_START
	112	#define get_l1_code_start_cpu(cpu) L1_CODE_START
	113	#define get_l1_data_a_start_cpu(cpu) L1_DATA_A_START
	114	#define get_l1_data_b_start_cpu(cpu) L1_DATA_B_START
	115	#define get_l1_scratch_start() L1_SCRATCH_START
	116	#define get_l1_code_start() L1_CODE_START
	117	#define get_l1_data_a_start() L1_DATA_A_START
	118	#define get_l1_data_b_start() L1_DATA_B_START
	119
	120	#define GET_PDA_SAFE(preg) \
	121	preg.l = _cpu_pda; \
	122	preg.h = _cpu_pda;
	123
	124	#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
	125
088eec11	126	#endif/* _MEM_MAP_548_H_ */