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Blackfin: fix typo in isram_write()
[net-next-2.6.git] / arch / blackfin / mach-bf548 / boards / ezkit.c
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24a07a12
RH		 1/*
2 * File: arch/blackfin/mach-bf548/boards/ezkit.c
3 * Based on: arch/blackfin/mach-bf537/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2007 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
de8c43f2 35#include <linux/mtd/physmap.h>
24a07a12
RH		 36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
1f83b8f1 38#include <linux/irq.h>
81d9c7f2 39#include <linux/i2c.h>
24a07a12 40#include <linux/interrupt.h>
c6c4d7bb 41#include <linux/usb/musb.h>
24a07a12 42#include <asm/bfin5xx_spi.h>
c6c4d7bb
BW		 43#include <asm/dma.h>
44#include <asm/gpio.h>
45#include <asm/nand.h>
14b03204 46#include <asm/dpmc.h>
5d448dd5 47#include <asm/portmux.h>
501674a5 48#include <asm/bfin_sdh.h>
639f6571 49#include <mach/bf54x_keys.h>
c6c4d7bb
BW		 50#include <linux/input.h>
51#include <linux/spi/ad7877.h>
24a07a12
RH		 52
53/*
54 * Name the Board for the /proc/cpuinfo
55 */
fe85cad2 56const char bfin_board_name[] = "ADI BF548-EZKIT";
24a07a12
RH		 57
58/*
59 * Driver needs to know address, irq and flag pin.
60 */
61
0a6304a9 62#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 63#include <linux/usb/isp1760.h>
64static struct resource bfin_isp1760_resources[] = {
0a6304a9 65 [0] = {
0a6304a9
MH		 66 .start = 0x2C0C0000,
67 .end = 0x2C0C0000 + 0xfffff,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = IRQ_PG7,
72 .end = IRQ_PG7,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
3f375690
MH		 77static struct isp1760_platform_data isp1760_priv = {
78 .is_isp1761 = 0,
3f375690
MH		 79 .bus_width_16 = 1,
80 .port1_otg = 0,
81 .analog_oc = 0,
82 .dack_polarity_high = 0,
83 .dreq_polarity_high = 0,
0a6304a9
MH		 84};
85
3f375690
MH		 86static struct platform_device bfin_isp1760_device = {
87 .name = "isp1760-hcd",
88 .id = 0,
89 .dev = {
90 .platform_data = &isp1760_priv,
91 },
92 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
93 .resource = bfin_isp1760_resources,
0a6304a9 94};
0a6304a9
MH		 95#endif
96
c6c4d7bb
BW		 97#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
98
639f6571 99#include <mach/bf54x-lq043.h>
c6c4d7bb
BW		 100
101static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
0e101ec1
SP		 102 .width = 95,
103 .height = 54,
c6c4d7bb
BW		 104 .xres = {480, 480, 480},
105 .yres = {272, 272, 272},
106 .bpp = {24, 24, 24},
107 .disp = GPIO_PE3,
108};
109
110static struct resource bf54x_lq043_resources[] = {
111 {
112 .start = IRQ_EPPI0_ERR,
113 .end = IRQ_EPPI0_ERR,
114 .flags = IORESOURCE_IRQ,
115 },
116};
117
118static struct platform_device bf54x_lq043_device = {
119 .name = "bf54x-lq043",
120 .id = -1,
121 .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
122 .resource = bf54x_lq043_resources,
123 .dev = {
124 .platform_data = &bf54x_lq043_data,
125 },
126};
127#endif
128
129#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
8f740ef3 130static const unsigned int bf548_keymap[] = {
c6c4d7bb
BW		 131 KEYVAL(0, 0, KEY_ENTER),
132 KEYVAL(0, 1, KEY_HELP),
133 KEYVAL(0, 2, KEY_0),
134 KEYVAL(0, 3, KEY_BACKSPACE),
135 KEYVAL(1, 0, KEY_TAB),
136 KEYVAL(1, 1, KEY_9),
137 KEYVAL(1, 2, KEY_8),
138 KEYVAL(1, 3, KEY_7),
139 KEYVAL(2, 0, KEY_DOWN),
140 KEYVAL(2, 1, KEY_6),
141 KEYVAL(2, 2, KEY_5),
142 KEYVAL(2, 3, KEY_4),
143 KEYVAL(3, 0, KEY_UP),
144 KEYVAL(3, 1, KEY_3),
145 KEYVAL(3, 2, KEY_2),
146 KEYVAL(3, 3, KEY_1),
147};
148
149static struct bfin_kpad_platform_data bf54x_kpad_data = {
150 .rows = 4,
151 .cols = 4,
8f740ef3
MH		 152 .keymap = bf548_keymap,
153 .keymapsize = ARRAY_SIZE(bf548_keymap),
c6c4d7bb
BW		 154 .repeat = 0,
155 .debounce_time = 5000, /* ns (5ms) */
156 .coldrive_time = 1000, /* ns (1ms) */
157 .keyup_test_interval = 50, /* ms (50ms) */
158};
159
160static struct resource bf54x_kpad_resources[] = {
161 {
162 .start = IRQ_KEY,
163 .end = IRQ_KEY,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct platform_device bf54x_kpad_device = {
169 .name = "bf54x-keys",
170 .id = -1,
171 .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
172 .resource = bf54x_kpad_resources,
173 .dev = {
174 .platform_data = &bf54x_kpad_data,
175 },
176};
177#endif
178
aca5e4aa
MH		 179#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
180#include <asm/bfin_rotary.h>
181
182static struct bfin_rotary_platform_data bfin_rotary_data = {
183 /*.rotary_up_key = KEY_UP,*/
184 /*.rotary_down_key = KEY_DOWN,*/
185 .rotary_rel_code = REL_WHEEL,
186 .rotary_button_key = KEY_ENTER,
187 .debounce = 10, /* 0..17 */
188 .mode = ROT_QUAD_ENC | ROT_DEBE,
189};
190
191static struct resource bfin_rotary_resources[] = {
192 {
193 .start = IRQ_CNT,
194 .end = IRQ_CNT,
195 .flags = IORESOURCE_IRQ,
196 },
197};
198
199static struct platform_device bfin_rotary_device = {
200 .name = "bfin-rotary",
201 .id = -1,
202 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
203 .resource = bfin_rotary_resources,
204 .dev = {
205 .platform_data = &bfin_rotary_data,
206 },
207};
208#endif
209
ffc4d8bc
MH		 210#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
211#include <linux/input.h>
212#include <linux/spi/adxl34x.h>
213static const struct adxl34x_platform_data adxl34x_info = {
214 .x_axis_offset = 0,
215 .y_axis_offset = 0,
216 .z_axis_offset = 0,
217 .tap_threshold = 0x31,
218 .tap_duration = 0x10,
219 .tap_latency = 0x60,
220 .tap_window = 0xF0,
221 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
222 .act_axis_control = 0xFF,
223 .activity_threshold = 5,
224 .inactivity_threshold = 3,
225 .inactivity_time = 4,
226 .free_fall_threshold = 0x7,
227 .free_fall_time = 0x20,
228 .data_rate = 0x8,
229 .data_range = ADXL_FULL_RES,
230
231 .ev_type = EV_ABS,
232 .ev_code_x = ABS_X, /* EV_REL */
233 .ev_code_y = ABS_Y, /* EV_REL */
234 .ev_code_z = ABS_Z, /* EV_REL */
235
236 .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */
237 .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */
238 .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */
239
240/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
241/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
242 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
243 .fifo_mode = ADXL_FIFO_STREAM,
244};
245#endif
246
24a07a12
RH		 247#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
248static struct platform_device rtc_device = {
249 .name = "rtc-bfin",
250 .id = -1,
251};
252#endif
253
254#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
255static struct resource bfin_uart_resources[] = {
256#ifdef CONFIG_SERIAL_BFIN_UART0
257 {
258 .start = 0xFFC00400,
259 .end = 0xFFC004FF,
260 .flags = IORESOURCE_MEM,
261 },
262#endif
263#ifdef CONFIG_SERIAL_BFIN_UART1
264 {
265 .start = 0xFFC02000,
266 .end = 0xFFC020FF,
267 .flags = IORESOURCE_MEM,
268 },
269#endif
270#ifdef CONFIG_SERIAL_BFIN_UART2
271 {
272 .start = 0xFFC02100,
273 .end = 0xFFC021FF,
274 .flags = IORESOURCE_MEM,
275 },
276#endif
277#ifdef CONFIG_SERIAL_BFIN_UART3
278 {
279 .start = 0xFFC03100,
280 .end = 0xFFC031FF,
cc2e16bd 281 .flags = IORESOURCE_MEM,
24a07a12
RH		 282 },
283#endif
284};
285
286static struct platform_device bfin_uart_device = {
287 .name = "bfin-uart",
288 .id = 1,
289 .num_resources = ARRAY_SIZE(bfin_uart_resources),
290 .resource = bfin_uart_resources,
291};
292#endif
293
5be36d22 294#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 295#ifdef CONFIG_BFIN_SIR0
42bd8bcb 296static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 297 {
298 .start = 0xFFC00400,
299 .end = 0xFFC004FF,
300 .flags = IORESOURCE_MEM,
301 },
42bd8bcb
GY		 302 {
303 .start = IRQ_UART0_RX,
304 .end = IRQ_UART0_RX+1,
305 .flags = IORESOURCE_IRQ,
306 },
307 {
308 .start = CH_UART0_RX,
309 .end = CH_UART0_RX+1,
310 .flags = IORESOURCE_DMA,
311 },
312};
313static struct platform_device bfin_sir0_device = {
314 .name = "bfin_sir",
315 .id = 0,
316 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
317 .resource = bfin_sir0_resources,
318};
5be36d22
GY		 319#endif
320#ifdef CONFIG_BFIN_SIR1
42bd8bcb 321static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 322 {
323 .start = 0xFFC02000,
324 .end = 0xFFC020FF,
325 .flags = IORESOURCE_MEM,
326 },
42bd8bcb
GY		 327 {
328 .start = IRQ_UART1_RX,
329 .end = IRQ_UART1_RX+1,
330 .flags = IORESOURCE_IRQ,
331 },
332 {
333 .start = CH_UART1_RX,
334 .end = CH_UART1_RX+1,
335 .flags = IORESOURCE_DMA,
336 },
337};
338static struct platform_device bfin_sir1_device = {
339 .name = "bfin_sir",
340 .id = 1,
341 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
342 .resource = bfin_sir1_resources,
343};
5be36d22
GY		 344#endif
345#ifdef CONFIG_BFIN_SIR2
42bd8bcb 346static struct resource bfin_sir2_resources[] = {
5be36d22
GY		 347 {
348 .start = 0xFFC02100,
349 .end = 0xFFC021FF,
350 .flags = IORESOURCE_MEM,
351 },
42bd8bcb
GY		 352 {
353 .start = IRQ_UART2_RX,
354 .end = IRQ_UART2_RX+1,
355 .flags = IORESOURCE_IRQ,
356 },
357 {
358 .start = CH_UART2_RX,
359 .end = CH_UART2_RX+1,
360 .flags = IORESOURCE_DMA,
361 },
362};
363static struct platform_device bfin_sir2_device = {
364 .name = "bfin_sir",
365 .id = 2,
366 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
367 .resource = bfin_sir2_resources,
368};
5be36d22
GY		 369#endif
370#ifdef CONFIG_BFIN_SIR3
42bd8bcb 371static struct resource bfin_sir3_resources[] = {
5be36d22
GY		 372 {
373 .start = 0xFFC03100,
374 .end = 0xFFC031FF,
375 .flags = IORESOURCE_MEM,
376 },
42bd8bcb
GY		 377 {
378 .start = IRQ_UART3_RX,
379 .end = IRQ_UART3_RX+1,
380 .flags = IORESOURCE_IRQ,
381 },
382 {
383 .start = CH_UART3_RX,
384 .end = CH_UART3_RX+1,
385 .flags = IORESOURCE_DMA,
386 },
5be36d22 387};
42bd8bcb 388static struct platform_device bfin_sir3_device = {
5be36d22 389 .name = "bfin_sir",
42bd8bcb
GY		 390 .id = 3,
391 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
392 .resource = bfin_sir3_resources,
5be36d22
GY		 393};
394#endif
42bd8bcb 395#endif
5be36d22 396
c6c4d7bb 397#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
7a8b71db
MF		 398#include <linux/smsc911x.h>
399
c6c4d7bb
BW		 400static struct resource smsc911x_resources[] = {
401 {
402 .name = "smsc911x-memory",
403 .start = 0x24000000,
404 .end = 0x24000000 + 0xFF,
405 .flags = IORESOURCE_MEM,
406 },
407 {
408 .start = IRQ_PE8,
409 .end = IRQ_PE8,
410 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
411 },
412};
7a8b71db
MF		 413
414static struct smsc911x_platform_config smsc911x_config = {
415 .flags = SMSC911X_USE_32BIT,
416 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
417 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
418 .phy_interface = PHY_INTERFACE_MODE_MII,
419};
420
c6c4d7bb
BW		 421static struct platform_device smsc911x_device = {
422 .name = "smsc911x",
423 .id = 0,
424 .num_resources = ARRAY_SIZE(smsc911x_resources),
425 .resource = smsc911x_resources,
7a8b71db
MF		 426 .dev = {
427 .platform_data = &smsc911x_config,
428 },
c6c4d7bb
BW		 429};
430#endif
431
c6c4d7bb
BW		 432#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
433static struct resource musb_resources[] = {
434 [0] = {
435 .start = 0xFFC03C00,
436 .end = 0xFFC040FF,
437 .flags = IORESOURCE_MEM,
438 },
439 [1] = { /* general IRQ */
440 .start = IRQ_USB_INT0,
441 .end = IRQ_USB_INT0,
442 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
443 },
444 [2] = { /* DMA IRQ */
445 .start = IRQ_USB_DMA,
446 .end = IRQ_USB_DMA,
447 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
448 },
449};
450
50041acb
BW		 451static struct musb_hdrc_config musb_config = {
452 .multipoint = 0,
453 .dyn_fifo = 0,
454 .soft_con = 1,
455 .dma = 1,
fea05dac
BW		 456 .num_eps = 8,
457 .dma_channels = 8,
50041acb
BW		 458 .gpio_vrsel = GPIO_PE7,
459};
460
c6c4d7bb 461static struct musb_hdrc_platform_data musb_plat = {
2935077e 462#if defined(CONFIG_USB_MUSB_OTG)
c6c4d7bb 463 .mode = MUSB_OTG,
2935077e 464#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
c6c4d7bb 465 .mode = MUSB_HOST,
2935077e 466#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
c6c4d7bb
BW		 467 .mode = MUSB_PERIPHERAL,
468#endif
50041acb 469 .config = &musb_config,
c6c4d7bb
BW		 470};
471
472static u64 musb_dmamask = ~(u32)0;
473
474static struct platform_device musb_device = {
475 .name = "musb_hdrc",
476 .id = 0,
477 .dev = {
478 .dma_mask = &musb_dmamask,
479 .coherent_dma_mask = 0xffffffff,
480 .platform_data = &musb_plat,
481 },
482 .num_resources = ARRAY_SIZE(musb_resources),
483 .resource = musb_resources,
484};
485#endif
486
487#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
488static struct resource bfin_atapi_resources[] = {
489 {
490 .start = 0xFFC03800,
491 .end = 0xFFC0386F,
492 .flags = IORESOURCE_MEM,
493 },
494 {
495 .start = IRQ_ATAPI_ERR,
496 .end = IRQ_ATAPI_ERR,
497 .flags = IORESOURCE_IRQ,
498 },
499};
500
501static struct platform_device bfin_atapi_device = {
502 .name = "pata-bf54x",
503 .id = -1,
504 .num_resources = ARRAY_SIZE(bfin_atapi_resources),
505 .resource = bfin_atapi_resources,
506};
507#endif
508
509#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
510static struct mtd_partition partition_info[] = {
511 {
aa582977 512 .name = "linux kernel(nand)",
c6c4d7bb 513 .offset = 0,
f4585a08 514 .size = 4 * 1024 * 1024,
c6c4d7bb
BW		 515 },
516 {
aa582977 517 .name = "file system(nand)",
edf05641
MF		 518 .offset = MTDPART_OFS_APPEND,
519 .size = MTDPART_SIZ_FULL,
c6c4d7bb
BW		 520 },
521};
522
523static struct bf5xx_nand_platform bf5xx_nand_platform = {
524 .page_size = NFC_PG_SIZE_256,
525 .data_width = NFC_NWIDTH_8,
526 .partitions = partition_info,
527 .nr_partitions = ARRAY_SIZE(partition_info),
528 .rd_dly = 3,
529 .wr_dly = 3,
530};
531
532static struct resource bf5xx_nand_resources[] = {
533 {
534 .start = 0xFFC03B00,
535 .end = 0xFFC03B4F,
536 .flags = IORESOURCE_MEM,
537 },
538 {
539 .start = CH_NFC,
540 .end = CH_NFC,
541 .flags = IORESOURCE_IRQ,
542 },
543};
544
545static struct platform_device bf5xx_nand_device = {
546 .name = "bf5xx-nand",
547 .id = 0,
548 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
549 .resource = bf5xx_nand_resources,
550 .dev = {
551 .platform_data = &bf5xx_nand_platform,
552 },
553};
554#endif
555
3d7e6cf8 556#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
501674a5
CC		 557
558static struct bfin_sd_host bfin_sdh_data = {
559 .dma_chan = CH_SDH,
560 .irq_int0 = IRQ_SDH_MASK0,
561 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
562};
563
c6c4d7bb
BW		 564static struct platform_device bf54x_sdh_device = {
565 .name = "bfin-sdh",
566 .id = 0,
501674a5
CC		 567 .dev = {
568 .platform_data = &bfin_sdh_data,
569 },
c6c4d7bb
BW		 570};
571#endif
572
793dc27b 573#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 574static struct mtd_partition ezkit_partitions[] = {
575 {
aa582977 576 .name = "bootloader(nor)",
edf05641 577 .size = 0x40000,
de8c43f2
MF		 578 .offset = 0,
579 }, {
aa582977 580 .name = "linux kernel(nor)",
664d0403 581 .size = 0x400000,
de8c43f2
MF		 582 .offset = MTDPART_OFS_APPEND,
583 }, {
aa582977 584 .name = "file system(nor)",
de8c43f2
MF		 585 .size = MTDPART_SIZ_FULL,
586 .offset = MTDPART_OFS_APPEND,
587 }
588};
589
590static struct physmap_flash_data ezkit_flash_data = {
591 .width = 2,
592 .parts = ezkit_partitions,
593 .nr_parts = ARRAY_SIZE(ezkit_partitions),
594};
595
596static struct resource ezkit_flash_resource = {
597 .start = 0x20000000,
664d0403 598 .end = 0x21ffffff,
de8c43f2
MF		 599 .flags = IORESOURCE_MEM,
600};
601
602static struct platform_device ezkit_flash_device = {
603 .name = "physmap-flash",
604 .id = 0,
605 .dev = {
606 .platform_data = &ezkit_flash_data,
607 },
608 .num_resources = 1,
609 .resource = &ezkit_flash_resource,
610};
793dc27b 611#endif
de8c43f2 612
c6c4d7bb
BW		 613#if defined(CONFIG_MTD_M25P80) \
614 || defined(CONFIG_MTD_M25P80_MODULE)
615/* SPI flash chip (m25p16) */
616static struct mtd_partition bfin_spi_flash_partitions[] = {
617 {
aa582977 618 .name = "bootloader(spi)",
c6c4d7bb
BW		 619 .size = 0x00040000,
620 .offset = 0,
621 .mask_flags = MTD_CAP_ROM
622 }, {
aa582977 623 .name = "linux kernel(spi)",
edf05641
MF		 624 .size = MTDPART_SIZ_FULL,
625 .offset = MTDPART_OFS_APPEND,
c6c4d7bb
BW		 626 }
627};
628
629static struct flash_platform_data bfin_spi_flash_data = {
630 .name = "m25p80",
631 .parts = bfin_spi_flash_partitions,
632 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
633 .type = "m25p16",
634};
635
636static struct bfin5xx_spi_chip spi_flash_chip_info = {
637 .enable_dma = 0, /* use dma transfer with this chip*/
638 .bits_per_word = 8,
639 .cs_change_per_word = 0,
640};
641#endif
642
37fa2421
BS		 643#if defined(CONFIG_SND_BLACKFIN_AD1836) \
644 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
645static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
646 .enable_dma = 0,
647 .bits_per_word = 16,
648};
649#endif
650
c6c4d7bb
BW		 651#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
652static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
c7d48966 653 .cs_change_per_word = 0,
c6c4d7bb
BW		 654 .enable_dma = 0,
655 .bits_per_word = 16,
656};
657
658static const struct ad7877_platform_data bfin_ad7877_ts_info = {
659 .model = 7877,
660 .vref_delay_usecs = 50, /* internal, no capacitor */
661 .x_plate_ohms = 419,
662 .y_plate_ohms = 486,
663 .pressure_max = 1000,
664 .pressure_min = 0,
665 .stopacq_polarity = 1,
666 .first_conversion_delay = 3,
667 .acquisition_time = 1,
668 .averaging = 1,
669 .pen_down_acc_interval = 1,
670};
671#endif
672
6e668936
MH		 673#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
674static struct bfin5xx_spi_chip spidev_chip_info = {
675 .enable_dma = 0,
676 .bits_per_word = 8,
677};
678#endif
679
ffc4d8bc
MH		 680#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
681static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
682 .enable_dma = 0, /* use dma transfer with this chip*/
683 .bits_per_word = 8,
684 .cs_change_per_word = 0,
685};
686#endif
687
5bda2723 688static struct spi_board_info bfin_spi_board_info[] __initdata = {
c6c4d7bb
BW		 689#if defined(CONFIG_MTD_M25P80) \
690 || defined(CONFIG_MTD_M25P80_MODULE)
691 {
692 /* the modalias must be the same as spi device driver name */
693 .modalias = "m25p80", /* Name of spi_driver for this device */
694 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
695 .bus_num = 0, /* Framework bus number */
696 .chip_select = 1, /* SPI_SSEL1*/
697 .platform_data = &bfin_spi_flash_data,
698 .controller_data = &spi_flash_chip_info,
699 .mode = SPI_MODE_3,
700 },
701#endif
37fa2421
BS		 702#if defined(CONFIG_SND_BLACKFIN_AD1836) \
703 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
704 {
dac98174 705 .modalias = "ad1836",
37fa2421
BS		 706 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
707 .bus_num = 1,
708 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
709 .controller_data = &ad1836_spi_chip_info,
710 },
711#endif
c6c4d7bb 712#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
ffc4d8bc
MH		 713 {
714 .modalias = "ad7877",
715 .platform_data = &bfin_ad7877_ts_info,
716 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
717 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
718 .bus_num = 0,
719 .chip_select = 2,
720 .controller_data = &spi_ad7877_chip_info,
721 },
c6c4d7bb 722#endif
6e668936
MH		 723#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
724 {
725 .modalias = "spidev",
726 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
727 .bus_num = 0,
728 .chip_select = 1,
729 .controller_data = &spidev_chip_info,
730 },
731#endif
ffc4d8bc
MH		 732#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
733 {
734 .modalias = "adxl34x",
735 .platform_data = &adxl34x_info,
736 .irq = IRQ_PC5,
737 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
738 .bus_num = 1,
739 .chip_select = 2,
740 .controller_data = &spi_adxl34x_chip_info,
741 .mode = SPI_MODE_3,
742 },
743#endif
c6c4d7bb 744};
5bda2723 745#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb
BW		 746/* SPI (0) */
747static struct resource bfin_spi0_resource[] = {
748 [0] = {
749 .start = SPI0_REGBASE,
750 .end = SPI0_REGBASE + 0xFF,
751 .flags = IORESOURCE_MEM,
752 },
753 [1] = {
754 .start = CH_SPI0,
755 .end = CH_SPI0,
53122693
YL		 756 .flags = IORESOURCE_DMA,
757 },
758 [2] = {
759 .start = IRQ_SPI0,
760 .end = IRQ_SPI0,
c6c4d7bb
BW		 761 .flags = IORESOURCE_IRQ,
762 }
763};
764
765/* SPI (1) */
766static struct resource bfin_spi1_resource[] = {
767 [0] = {
768 .start = SPI1_REGBASE,
769 .end = SPI1_REGBASE + 0xFF,
770 .flags = IORESOURCE_MEM,
771 },
772 [1] = {
773 .start = CH_SPI1,
774 .end = CH_SPI1,
53122693
YL		 775 .flags = IORESOURCE_DMA,
776 },
777 [2] = {
778 .start = IRQ_SPI1,
779 .end = IRQ_SPI1,
c6c4d7bb
BW		 780 .flags = IORESOURCE_IRQ,
781 }
782};
783
784/* SPI controller data */
5d448dd5 785static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
c6c4d7bb
BW		 786 .num_chipselect = 8,
787 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 788 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
c6c4d7bb
BW		 789};
790
791static struct platform_device bf54x_spi_master0 = {
792 .name = "bfin-spi",
793 .id = 0, /* Bus number */
794 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
795 .resource = bfin_spi0_resource,
796 .dev = {
5d448dd5 797 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
c6c4d7bb
BW		 798 },
799};
800
5d448dd5
BW		 801static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
802 .num_chipselect = 8,
803 .enable_dma = 1, /* master has the ability to do dma transfer */
804 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
805};
806
c6c4d7bb
BW		 807static struct platform_device bf54x_spi_master1 = {
808 .name = "bfin-spi",
809 .id = 1, /* Bus number */
810 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
811 .resource = bfin_spi1_resource,
812 .dev = {
5d448dd5 813 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
c6c4d7bb
BW		 814 },
815};
816#endif /* spi master and devices */
817
818#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
819static struct resource bfin_twi0_resource[] = {
820 [0] = {
821 .start = TWI0_REGBASE,
822 .end = TWI0_REGBASE + 0xFF,
823 .flags = IORESOURCE_MEM,
824 },
825 [1] = {
826 .start = IRQ_TWI0,
827 .end = IRQ_TWI0,
828 .flags = IORESOURCE_IRQ,
829 },
830};
831
832static struct platform_device i2c_bfin_twi0_device = {
833 .name = "i2c-bfin-twi",
834 .id = 0,
835 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
836 .resource = bfin_twi0_resource,
837};
838
7160e950 839#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
c6c4d7bb
BW		 840static struct resource bfin_twi1_resource[] = {
841 [0] = {
842 .start = TWI1_REGBASE,
843 .end = TWI1_REGBASE + 0xFF,
844 .flags = IORESOURCE_MEM,
845 },
846 [1] = {
847 .start = IRQ_TWI1,
848 .end = IRQ_TWI1,
849 .flags = IORESOURCE_IRQ,
850 },
851};
852
853static struct platform_device i2c_bfin_twi1_device = {
854 .name = "i2c-bfin-twi",
855 .id = 1,
856 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
857 .resource = bfin_twi1_resource,
858};
859#endif
7160e950 860#endif
c6c4d7bb 861
81d9c7f2
BW		 862static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
863};
864
865#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
866static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
ebd58333 867#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
81d9c7f2
BW		 868 {
869 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 870 },
871#endif
204844eb 872#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
81d9c7f2
BW		 873 {
874 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
81d9c7f2
BW		 875 .irq = 212,
876 },
877#endif
ffc4d8bc
MH		 878#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
879 {
880 I2C_BOARD_INFO("adxl34x", 0x53),
881 .irq = IRQ_PC5,
882 .platform_data = (void *)&adxl34x_info,
883 },
884#endif
81d9c7f2
BW		 885};
886#endif
81d9c7f2 887
2463ef22
MH		 888#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
889#include <linux/gpio_keys.h>
890
891static struct gpio_keys_button bfin_gpio_keys_table[] = {
892 {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
893 {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
894 {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
895 {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
896};
897
898static struct gpio_keys_platform_data bfin_gpio_keys_data = {
899 .buttons = bfin_gpio_keys_table,
900 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
901};
902
903static struct platform_device bfin_device_gpiokeys = {
904 .name = "gpio-keys",
905 .dev = {
906 .platform_data = &bfin_gpio_keys_data,
907 },
908};
909#endif
910
cad2ab65
MF		 911static struct resource bfin_gpios_resources = {
912 .start = 0,
913 .end = MAX_BLACKFIN_GPIOS - 1,
914 .flags = IORESOURCE_IRQ,
915};
916
917static struct platform_device bfin_gpios_device = {
918 .name = "simple-gpio",
919 .id = -1,
920 .num_resources = 1,
921 .resource = &bfin_gpios_resources,
922};
923
14b03204
MH		 924static const unsigned int cclk_vlev_datasheet[] =
925{
926/*
927 * Internal VLEV BF54XSBBC1533
928 ****temporarily using these values until data sheet is updated
929 */
930 VRPAIR(VLEV_085, 150000000),
931 VRPAIR(VLEV_090, 250000000),
932 VRPAIR(VLEV_110, 276000000),
933 VRPAIR(VLEV_115, 301000000),
934 VRPAIR(VLEV_120, 525000000),
935 VRPAIR(VLEV_125, 550000000),
936 VRPAIR(VLEV_130, 600000000),
937};
938
939static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
940 .tuple_tab = cclk_vlev_datasheet,
941 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
942 .vr_settling_time = 25 /* us */,
943};
944
945static struct platform_device bfin_dpmc = {
946 .name = "bfin dpmc",
947 .dev = {
948 .platform_data = &bfin_dmpc_vreg_data,
949 },
950};
951
24a07a12 952static struct platform_device *ezkit_devices[] __initdata = {
14b03204
MH		 953
954 &bfin_dpmc,
955
24a07a12
RH		 956#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
957 &rtc_device,
958#endif
959
960#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
961 &bfin_uart_device,
962#endif
c6c4d7bb 963
5be36d22 964#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 965#ifdef CONFIG_BFIN_SIR0
966 &bfin_sir0_device,
967#endif
968#ifdef CONFIG_BFIN_SIR1
969 &bfin_sir1_device,
970#endif
971#ifdef CONFIG_BFIN_SIR2
972 &bfin_sir2_device,
973#endif
974#ifdef CONFIG_BFIN_SIR3
975 &bfin_sir3_device,
976#endif
5be36d22
GY		 977#endif
978
c6c4d7bb
BW		 979#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
980 &bf54x_lq043_device,
981#endif
982
983#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
984 &smsc911x_device,
985#endif
986
c6c4d7bb
BW		 987#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
988 &musb_device,
989#endif
990
3f375690
MH		 991#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
992 &bfin_isp1760_device,
993#endif
994
c6c4d7bb
BW		 995#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
996 &bfin_atapi_device,
997#endif
998
999#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1000 &bf5xx_nand_device,
1001#endif
1002
3d7e6cf8 1003#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
c6c4d7bb
BW		 1004 &bf54x_sdh_device,
1005#endif
1006
1007#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1008 &bf54x_spi_master0,
d4b1d273 1009 &bf54x_spi_master1,
c6c4d7bb
BW		 1010#endif
1011
1012#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
1013 &bf54x_kpad_device,
1014#endif
1015
aca5e4aa
MH		 1016#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
1017 &bfin_rotary_device,
1018#endif
1019
c6c4d7bb
BW		 1020#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1021 &i2c_bfin_twi0_device,
7160e950 1022#if !defined(CONFIG_BF542)
c6c4d7bb
BW		 1023 &i2c_bfin_twi1_device,
1024#endif
7160e950 1025#endif
2463ef22
MH		 1026
1027#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1028 &bfin_device_gpiokeys,
1029#endif
cad2ab65
MF		 1030
1031 &bfin_gpios_device,
793dc27b
MF		 1032
1033#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1034 &ezkit_flash_device,
793dc27b 1035#endif
24a07a12
RH		 1036};
1037
a01d7a76 1038static int __init ezkit_init(void)
24a07a12 1039{
b85d858b 1040 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2 1041
81d9c7f2
BW		 1042 i2c_register_board_info(0, bfin_i2c_board_info0,
1043 ARRAY_SIZE(bfin_i2c_board_info0));
1044#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1045 i2c_register_board_info(1, bfin_i2c_board_info1,
1046 ARRAY_SIZE(bfin_i2c_board_info1));
81d9c7f2
BW		 1047#endif
1048
24a07a12 1049 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
c6c4d7bb 1050
5bda2723 1051 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb 1052
24a07a12
RH		 1053 return 0;
1054}
1055
a01d7a76 1056arch_initcall(ezkit_init);
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