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Blackfin: bf537-stamp: ad1938: switch to GPIO CS
[net-next-2.6.git] / arch / blackfin / mach-bf548 / boards / ezkit.c
CommitLineData
24a07a12 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
24a07a12 5 *
96f1050d 6 * Licensed under the GPL-2 or later.
24a07a12
RH		 7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
de8c43f2 13#include <linux/mtd/physmap.h>
24a07a12
RH		 14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
1f83b8f1 16#include <linux/irq.h>
81d9c7f2 17#include <linux/i2c.h>
24a07a12 18#include <linux/interrupt.h>
c6c4d7bb 19#include <linux/usb/musb.h>
24a07a12 20#include <asm/bfin5xx_spi.h>
c6c4d7bb
BW		 21#include <asm/dma.h>
22#include <asm/gpio.h>
23#include <asm/nand.h>
14b03204 24#include <asm/dpmc.h>
5d448dd5 25#include <asm/portmux.h>
501674a5 26#include <asm/bfin_sdh.h>
639f6571 27#include <mach/bf54x_keys.h>
c6c4d7bb
BW		 28#include <linux/input.h>
29#include <linux/spi/ad7877.h>
24a07a12
RH		 30
31/*
32 * Name the Board for the /proc/cpuinfo
33 */
fe85cad2 34const char bfin_board_name[] = "ADI BF548-EZKIT";
24a07a12
RH		 35
36/*
37 * Driver needs to know address, irq and flag pin.
38 */
39
0a6304a9 40#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 41#include <linux/usb/isp1760.h>
42static struct resource bfin_isp1760_resources[] = {
0a6304a9 43 [0] = {
0a6304a9
MH		 44 .start = 0x2C0C0000,
45 .end = 0x2C0C0000 + 0xfffff,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = IRQ_PG7,
50 .end = IRQ_PG7,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
3f375690
MH		 55static struct isp1760_platform_data isp1760_priv = {
56 .is_isp1761 = 0,
3f375690
MH		 57 .bus_width_16 = 1,
58 .port1_otg = 0,
59 .analog_oc = 0,
60 .dack_polarity_high = 0,
61 .dreq_polarity_high = 0,
0a6304a9
MH		 62};
63
3f375690 64static struct platform_device bfin_isp1760_device = {
c6feb768 65 .name = "isp1760",
3f375690
MH		 66 .id = 0,
67 .dev = {
68 .platform_data = &isp1760_priv,
69 },
70 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
71 .resource = bfin_isp1760_resources,
0a6304a9 72};
0a6304a9
MH		 73#endif
74
c6c4d7bb
BW		 75#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
76
639f6571 77#include <mach/bf54x-lq043.h>
c6c4d7bb
BW		 78
79static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
0e101ec1
SP		 80 .width = 95,
81 .height = 54,
c6c4d7bb
BW		 82 .xres = {480, 480, 480},
83 .yres = {272, 272, 272},
84 .bpp = {24, 24, 24},
85 .disp = GPIO_PE3,
86};
87
88static struct resource bf54x_lq043_resources[] = {
89 {
90 .start = IRQ_EPPI0_ERR,
91 .end = IRQ_EPPI0_ERR,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device bf54x_lq043_device = {
97 .name = "bf54x-lq043",
98 .id = -1,
99 .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
100 .resource = bf54x_lq043_resources,
101 .dev = {
102 .platform_data = &bf54x_lq043_data,
103 },
104};
105#endif
106
107#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
8f740ef3 108static const unsigned int bf548_keymap[] = {
c6c4d7bb
BW		 109 KEYVAL(0, 0, KEY_ENTER),
110 KEYVAL(0, 1, KEY_HELP),
111 KEYVAL(0, 2, KEY_0),
112 KEYVAL(0, 3, KEY_BACKSPACE),
113 KEYVAL(1, 0, KEY_TAB),
114 KEYVAL(1, 1, KEY_9),
115 KEYVAL(1, 2, KEY_8),
116 KEYVAL(1, 3, KEY_7),
117 KEYVAL(2, 0, KEY_DOWN),
118 KEYVAL(2, 1, KEY_6),
119 KEYVAL(2, 2, KEY_5),
120 KEYVAL(2, 3, KEY_4),
121 KEYVAL(3, 0, KEY_UP),
122 KEYVAL(3, 1, KEY_3),
123 KEYVAL(3, 2, KEY_2),
124 KEYVAL(3, 3, KEY_1),
125};
126
127static struct bfin_kpad_platform_data bf54x_kpad_data = {
128 .rows = 4,
129 .cols = 4,
8f740ef3
MH		 130 .keymap = bf548_keymap,
131 .keymapsize = ARRAY_SIZE(bf548_keymap),
c6c4d7bb
BW		 132 .repeat = 0,
133 .debounce_time = 5000, /* ns (5ms) */
134 .coldrive_time = 1000, /* ns (1ms) */
135 .keyup_test_interval = 50, /* ms (50ms) */
136};
137
138static struct resource bf54x_kpad_resources[] = {
139 {
140 .start = IRQ_KEY,
141 .end = IRQ_KEY,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static struct platform_device bf54x_kpad_device = {
147 .name = "bf54x-keys",
148 .id = -1,
149 .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
150 .resource = bf54x_kpad_resources,
151 .dev = {
152 .platform_data = &bf54x_kpad_data,
153 },
154};
155#endif
156
adfc0467 157#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 158#include <asm/bfin_rotary.h>
159
160static struct bfin_rotary_platform_data bfin_rotary_data = {
161 /*.rotary_up_key = KEY_UP,*/
162 /*.rotary_down_key = KEY_DOWN,*/
163 .rotary_rel_code = REL_WHEEL,
164 .rotary_button_key = KEY_ENTER,
165 .debounce = 10, /* 0..17 */
166 .mode = ROT_QUAD_ENC | ROT_DEBE,
167};
168
169static struct resource bfin_rotary_resources[] = {
170 {
171 .start = IRQ_CNT,
172 .end = IRQ_CNT,
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct platform_device bfin_rotary_device = {
178 .name = "bfin-rotary",
179 .id = -1,
180 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
181 .resource = bfin_rotary_resources,
182 .dev = {
183 .platform_data = &bfin_rotary_data,
184 },
185};
186#endif
187
ffc4d8bc 188#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
57af8edf 189#include <linux/input/adxl34x.h>
ffc4d8bc
MH		 190static const struct adxl34x_platform_data adxl34x_info = {
191 .x_axis_offset = 0,
192 .y_axis_offset = 0,
193 .z_axis_offset = 0,
194 .tap_threshold = 0x31,
195 .tap_duration = 0x10,
196 .tap_latency = 0x60,
197 .tap_window = 0xF0,
198 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
199 .act_axis_control = 0xFF,
200 .activity_threshold = 5,
201 .inactivity_threshold = 3,
202 .inactivity_time = 4,
203 .free_fall_threshold = 0x7,
204 .free_fall_time = 0x20,
205 .data_rate = 0x8,
206 .data_range = ADXL_FULL_RES,
207
208 .ev_type = EV_ABS,
209 .ev_code_x = ABS_X, /* EV_REL */
210 .ev_code_y = ABS_Y, /* EV_REL */
211 .ev_code_z = ABS_Z, /* EV_REL */
212
57af8edf 213 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
ffc4d8bc
MH		 214
215/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
216/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
217 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
218 .fifo_mode = ADXL_FIFO_STREAM,
5db4036b
MH		 219 .orientation_enable = ADXL_EN_ORIENTATION_3D,
220 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
221 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
222 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
223 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
ffc4d8bc
MH		 224};
225#endif
226
24a07a12
RH		 227#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
228static struct platform_device rtc_device = {
229 .name = "rtc-bfin",
230 .id = -1,
231};
232#endif
233
234#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
24a07a12 235#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 236static struct resource bfin_uart0_resources[] = {
24a07a12 237 {
6bd1fbea
SZ		 238 .start = UART0_DLL,
239 .end = UART0_RBR+2,
24a07a12
RH		 240 .flags = IORESOURCE_MEM,
241 },
6bd1fbea
SZ		 242 {
243 .start = IRQ_UART0_RX,
244 .end = IRQ_UART0_RX+1,
245 .flags = IORESOURCE_IRQ,
246 },
247 {
248 .start = IRQ_UART0_ERROR,
249 .end = IRQ_UART0_ERROR,
250 .flags = IORESOURCE_IRQ,
251 },
252 {
253 .start = CH_UART0_TX,
254 .end = CH_UART0_TX,
255 .flags = IORESOURCE_DMA,
256 },
257 {
258 .start = CH_UART0_RX,
259 .end = CH_UART0_RX,
260 .flags = IORESOURCE_DMA,
261 },
262};
263
264unsigned short bfin_uart0_peripherals[] = {
265 P_UART0_TX, P_UART0_RX, 0
266};
267
268static struct platform_device bfin_uart0_device = {
269 .name = "bfin-uart",
270 .id = 0,
271 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
272 .resource = bfin_uart0_resources,
273 .dev = {
274 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
275 },
276};
24a07a12
RH		 277#endif
278#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 279static struct resource bfin_uart1_resources[] = {
24a07a12 280 {
6bd1fbea
SZ		 281 .start = UART1_DLL,
282 .end = UART1_RBR+2,
24a07a12
RH		 283 .flags = IORESOURCE_MEM,
284 },
6bd1fbea
SZ		 285 {
286 .start = IRQ_UART1_RX,
287 .end = IRQ_UART1_RX+1,
288 .flags = IORESOURCE_IRQ,
289 },
290 {
291 .start = IRQ_UART1_ERROR,
292 .end = IRQ_UART1_ERROR,
293 .flags = IORESOURCE_IRQ,
294 },
295 {
296 .start = CH_UART1_TX,
297 .end = CH_UART1_TX,
298 .flags = IORESOURCE_DMA,
299 },
300 {
301 .start = CH_UART1_RX,
302 .end = CH_UART1_RX,
303 .flags = IORESOURCE_DMA,
304 },
305#ifdef CONFIG_BFIN_UART1_CTSRTS
306 { /* CTS pin -- 0 means not supported */
307 .start = GPIO_PE10,
308 .end = GPIO_PE10,
309 .flags = IORESOURCE_IO,
310 },
311 { /* RTS pin -- 0 means not supported */
312 .start = GPIO_PE9,
313 .end = GPIO_PE9,
314 .flags = IORESOURCE_IO,
315 },
316#endif
317};
318
319unsigned short bfin_uart1_peripherals[] = {
320 P_UART1_TX, P_UART1_RX,
321#ifdef CONFIG_BFIN_UART1_CTSRTS
322 P_UART1_RTS, P_UART1_CTS,
323#endif
324 0
325};
326
327static struct platform_device bfin_uart1_device = {
328 .name = "bfin-uart",
329 .id = 1,
330 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
331 .resource = bfin_uart1_resources,
332 .dev = {
333 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
334 },
335};
24a07a12
RH		 336#endif
337#ifdef CONFIG_SERIAL_BFIN_UART2
6bd1fbea 338static struct resource bfin_uart2_resources[] = {
24a07a12 339 {
6bd1fbea
SZ		 340 .start = UART2_DLL,
341 .end = UART2_RBR+2,
24a07a12
RH		 342 .flags = IORESOURCE_MEM,
343 },
6bd1fbea
SZ		 344 {
345 .start = IRQ_UART2_RX,
346 .end = IRQ_UART2_RX+1,
347 .flags = IORESOURCE_IRQ,
348 },
349 {
350 .start = IRQ_UART2_ERROR,
351 .end = IRQ_UART2_ERROR,
352 .flags = IORESOURCE_IRQ,
353 },
354 {
355 .start = CH_UART2_TX,
356 .end = CH_UART2_TX,
357 .flags = IORESOURCE_DMA,
358 },
359 {
360 .start = CH_UART2_RX,
361 .end = CH_UART2_RX,
362 .flags = IORESOURCE_DMA,
363 },
364};
365
366unsigned short bfin_uart2_peripherals[] = {
367 P_UART2_TX, P_UART2_RX, 0
368};
369
370static struct platform_device bfin_uart2_device = {
371 .name = "bfin-uart",
372 .id = 2,
373 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
374 .resource = bfin_uart2_resources,
375 .dev = {
376 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
377 },
378};
24a07a12
RH		 379#endif
380#ifdef CONFIG_SERIAL_BFIN_UART3
6bd1fbea 381static struct resource bfin_uart3_resources[] = {
24a07a12 382 {
6bd1fbea
SZ		 383 .start = UART3_DLL,
384 .end = UART3_RBR+2,
cc2e16bd 385 .flags = IORESOURCE_MEM,
24a07a12 386 },
6bd1fbea
SZ		 387 {
388 .start = IRQ_UART3_RX,
389 .end = IRQ_UART3_RX+1,
390 .flags = IORESOURCE_IRQ,
391 },
392 {
393 .start = IRQ_UART3_ERROR,
394 .end = IRQ_UART3_ERROR,
395 .flags = IORESOURCE_IRQ,
396 },
397 {
398 .start = CH_UART3_TX,
399 .end = CH_UART3_TX,
400 .flags = IORESOURCE_DMA,
401 },
402 {
403 .start = CH_UART3_RX,
404 .end = CH_UART3_RX,
405 .flags = IORESOURCE_DMA,
406 },
407#ifdef CONFIG_BFIN_UART3_CTSRTS
408 { /* CTS pin -- 0 means not supported */
409 .start = GPIO_PB3,
410 .end = GPIO_PB3,
411 .flags = IORESOURCE_IO,
412 },
413 { /* RTS pin -- 0 means not supported */
414 .start = GPIO_PB2,
415 .end = GPIO_PB2,
416 .flags = IORESOURCE_IO,
417 },
24a07a12
RH		 418#endif
419};
420
6bd1fbea
SZ		 421unsigned short bfin_uart3_peripherals[] = {
422 P_UART3_TX, P_UART3_RX,
423#ifdef CONFIG_BFIN_UART3_CTSRTS
424 P_UART3_RTS, P_UART3_CTS,
425#endif
426 0
427};
428
429static struct platform_device bfin_uart3_device = {
24a07a12 430 .name = "bfin-uart",
6bd1fbea
SZ		 431 .id = 3,
432 .num_resources = ARRAY_SIZE(bfin_uart3_resources),
433 .resource = bfin_uart3_resources,
434 .dev = {
435 .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
436 },
24a07a12
RH		 437};
438#endif
6bd1fbea 439#endif
24a07a12 440
5be36d22 441#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 442#ifdef CONFIG_BFIN_SIR0
42bd8bcb 443static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 444 {
445 .start = 0xFFC00400,
446 .end = 0xFFC004FF,
447 .flags = IORESOURCE_MEM,
448 },
42bd8bcb
GY		 449 {
450 .start = IRQ_UART0_RX,
451 .end = IRQ_UART0_RX+1,
452 .flags = IORESOURCE_IRQ,
453 },
454 {
455 .start = CH_UART0_RX,
456 .end = CH_UART0_RX+1,
457 .flags = IORESOURCE_DMA,
458 },
459};
460static struct platform_device bfin_sir0_device = {
461 .name = "bfin_sir",
462 .id = 0,
463 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
464 .resource = bfin_sir0_resources,
465};
5be36d22
GY		 466#endif
467#ifdef CONFIG_BFIN_SIR1
42bd8bcb 468static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 469 {
470 .start = 0xFFC02000,
471 .end = 0xFFC020FF,
472 .flags = IORESOURCE_MEM,
473 },
42bd8bcb
GY		 474 {
475 .start = IRQ_UART1_RX,
476 .end = IRQ_UART1_RX+1,
477 .flags = IORESOURCE_IRQ,
478 },
479 {
480 .start = CH_UART1_RX,
481 .end = CH_UART1_RX+1,
482 .flags = IORESOURCE_DMA,
483 },
484};
485static struct platform_device bfin_sir1_device = {
486 .name = "bfin_sir",
487 .id = 1,
488 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
489 .resource = bfin_sir1_resources,
490};
5be36d22
GY		 491#endif
492#ifdef CONFIG_BFIN_SIR2
42bd8bcb 493static struct resource bfin_sir2_resources[] = {
5be36d22
GY		 494 {
495 .start = 0xFFC02100,
496 .end = 0xFFC021FF,
497 .flags = IORESOURCE_MEM,
498 },
42bd8bcb
GY		 499 {
500 .start = IRQ_UART2_RX,
501 .end = IRQ_UART2_RX+1,
502 .flags = IORESOURCE_IRQ,
503 },
504 {
505 .start = CH_UART2_RX,
506 .end = CH_UART2_RX+1,
507 .flags = IORESOURCE_DMA,
508 },
509};
510static struct platform_device bfin_sir2_device = {
511 .name = "bfin_sir",
512 .id = 2,
513 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
514 .resource = bfin_sir2_resources,
515};
5be36d22
GY		 516#endif
517#ifdef CONFIG_BFIN_SIR3
42bd8bcb 518static struct resource bfin_sir3_resources[] = {
5be36d22
GY		 519 {
520 .start = 0xFFC03100,
521 .end = 0xFFC031FF,
522 .flags = IORESOURCE_MEM,
523 },
42bd8bcb
GY		 524 {
525 .start = IRQ_UART3_RX,
526 .end = IRQ_UART3_RX+1,
527 .flags = IORESOURCE_IRQ,
528 },
529 {
530 .start = CH_UART3_RX,
531 .end = CH_UART3_RX+1,
532 .flags = IORESOURCE_DMA,
533 },
5be36d22 534};
42bd8bcb 535static struct platform_device bfin_sir3_device = {
5be36d22 536 .name = "bfin_sir",
42bd8bcb
GY		 537 .id = 3,
538 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
539 .resource = bfin_sir3_resources,
5be36d22
GY		 540};
541#endif
42bd8bcb 542#endif
5be36d22 543
c6c4d7bb 544#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
7a8b71db
MF		 545#include <linux/smsc911x.h>
546
c6c4d7bb
BW		 547static struct resource smsc911x_resources[] = {
548 {
549 .name = "smsc911x-memory",
550 .start = 0x24000000,
551 .end = 0x24000000 + 0xFF,
552 .flags = IORESOURCE_MEM,
553 },
554 {
555 .start = IRQ_PE8,
556 .end = IRQ_PE8,
557 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
558 },
559};
7a8b71db
MF		 560
561static struct smsc911x_platform_config smsc911x_config = {
562 .flags = SMSC911X_USE_32BIT,
563 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
564 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
565 .phy_interface = PHY_INTERFACE_MODE_MII,
566};
567
c6c4d7bb
BW		 568static struct platform_device smsc911x_device = {
569 .name = "smsc911x",
570 .id = 0,
571 .num_resources = ARRAY_SIZE(smsc911x_resources),
572 .resource = smsc911x_resources,
7a8b71db
MF		 573 .dev = {
574 .platform_data = &smsc911x_config,
575 },
c6c4d7bb
BW		 576};
577#endif
578
c6c4d7bb
BW		 579#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
580static struct resource musb_resources[] = {
581 [0] = {
582 .start = 0xFFC03C00,
583 .end = 0xFFC040FF,
584 .flags = IORESOURCE_MEM,
585 },
586 [1] = { /* general IRQ */
587 .start = IRQ_USB_INT0,
588 .end = IRQ_USB_INT0,
589 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
590 },
591 [2] = { /* DMA IRQ */
592 .start = IRQ_USB_DMA,
593 .end = IRQ_USB_DMA,
594 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
595 },
596};
597
50041acb
BW		 598static struct musb_hdrc_config musb_config = {
599 .multipoint = 0,
600 .dyn_fifo = 0,
601 .soft_con = 1,
602 .dma = 1,
fea05dac
BW		 603 .num_eps = 8,
604 .dma_channels = 8,
50041acb
BW		 605 .gpio_vrsel = GPIO_PE7,
606};
607
c6c4d7bb 608static struct musb_hdrc_platform_data musb_plat = {
2935077e 609#if defined(CONFIG_USB_MUSB_OTG)
c6c4d7bb 610 .mode = MUSB_OTG,
2935077e 611#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
c6c4d7bb 612 .mode = MUSB_HOST,
2935077e 613#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
c6c4d7bb
BW		 614 .mode = MUSB_PERIPHERAL,
615#endif
50041acb 616 .config = &musb_config,
c6c4d7bb
BW		 617};
618
619static u64 musb_dmamask = ~(u32)0;
620
621static struct platform_device musb_device = {
622 .name = "musb_hdrc",
623 .id = 0,
624 .dev = {
625 .dma_mask = &musb_dmamask,
626 .coherent_dma_mask = 0xffffffff,
627 .platform_data = &musb_plat,
628 },
629 .num_resources = ARRAY_SIZE(musb_resources),
630 .resource = musb_resources,
631};
632#endif
633
706a01b1
BS		 634#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
635unsigned short bfin_can_peripherals[] = {
636 P_CAN0_RX, P_CAN0_TX, 0
637};
638
639static struct resource bfin_can_resources[] = {
640 {
641 .start = 0xFFC02A00,
642 .end = 0xFFC02FFF,
643 .flags = IORESOURCE_MEM,
644 },
645 {
646 .start = IRQ_CAN0_RX,
647 .end = IRQ_CAN0_RX,
648 .flags = IORESOURCE_IRQ,
649 },
650 {
651 .start = IRQ_CAN0_TX,
652 .end = IRQ_CAN0_TX,
653 .flags = IORESOURCE_IRQ,
654 },
655 {
656 .start = IRQ_CAN0_ERROR,
657 .end = IRQ_CAN0_ERROR,
658 .flags = IORESOURCE_IRQ,
659 },
660};
661
662static struct platform_device bfin_can_device = {
663 .name = "bfin_can",
664 .num_resources = ARRAY_SIZE(bfin_can_resources),
665 .resource = bfin_can_resources,
666 .dev = {
667 .platform_data = &bfin_can_peripherals, /* Passed to driver */
668 },
669};
670#endif
671
c6c4d7bb
BW		 672#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
673static struct resource bfin_atapi_resources[] = {
674 {
675 .start = 0xFFC03800,
676 .end = 0xFFC0386F,
677 .flags = IORESOURCE_MEM,
678 },
679 {
680 .start = IRQ_ATAPI_ERR,
681 .end = IRQ_ATAPI_ERR,
682 .flags = IORESOURCE_IRQ,
683 },
684};
685
686static struct platform_device bfin_atapi_device = {
687 .name = "pata-bf54x",
688 .id = -1,
689 .num_resources = ARRAY_SIZE(bfin_atapi_resources),
690 .resource = bfin_atapi_resources,
691};
692#endif
693
694#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
695static struct mtd_partition partition_info[] = {
696 {
aa582977 697 .name = "linux kernel(nand)",
c6c4d7bb 698 .offset = 0,
f4585a08 699 .size = 4 * 1024 * 1024,
c6c4d7bb
BW		 700 },
701 {
aa582977 702 .name = "file system(nand)",
edf05641
MF		 703 .offset = MTDPART_OFS_APPEND,
704 .size = MTDPART_SIZ_FULL,
c6c4d7bb
BW		 705 },
706};
707
708static struct bf5xx_nand_platform bf5xx_nand_platform = {
709 .page_size = NFC_PG_SIZE_256,
710 .data_width = NFC_NWIDTH_8,
711 .partitions = partition_info,
712 .nr_partitions = ARRAY_SIZE(partition_info),
713 .rd_dly = 3,
714 .wr_dly = 3,
715};
716
717static struct resource bf5xx_nand_resources[] = {
718 {
719 .start = 0xFFC03B00,
720 .end = 0xFFC03B4F,
721 .flags = IORESOURCE_MEM,
722 },
723 {
724 .start = CH_NFC,
725 .end = CH_NFC,
726 .flags = IORESOURCE_IRQ,
727 },
728};
729
730static struct platform_device bf5xx_nand_device = {
731 .name = "bf5xx-nand",
732 .id = 0,
733 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
734 .resource = bf5xx_nand_resources,
735 .dev = {
736 .platform_data = &bf5xx_nand_platform,
737 },
738};
739#endif
740
3d7e6cf8 741#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
501674a5
CC		 742
743static struct bfin_sd_host bfin_sdh_data = {
744 .dma_chan = CH_SDH,
745 .irq_int0 = IRQ_SDH_MASK0,
746 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
747};
748
c6c4d7bb
BW		 749static struct platform_device bf54x_sdh_device = {
750 .name = "bfin-sdh",
751 .id = 0,
501674a5
CC		 752 .dev = {
753 .platform_data = &bfin_sdh_data,
754 },
c6c4d7bb
BW		 755};
756#endif
757
793dc27b 758#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 759static struct mtd_partition ezkit_partitions[] = {
760 {
aa582977 761 .name = "bootloader(nor)",
edf05641 762 .size = 0x40000,
de8c43f2
MF		 763 .offset = 0,
764 }, {
aa582977 765 .name = "linux kernel(nor)",
664d0403 766 .size = 0x400000,
de8c43f2
MF		 767 .offset = MTDPART_OFS_APPEND,
768 }, {
aa582977 769 .name = "file system(nor)",
de8c43f2
MF		 770 .size = MTDPART_SIZ_FULL,
771 .offset = MTDPART_OFS_APPEND,
772 }
773};
774
775static struct physmap_flash_data ezkit_flash_data = {
776 .width = 2,
777 .parts = ezkit_partitions,
778 .nr_parts = ARRAY_SIZE(ezkit_partitions),
779};
780
781static struct resource ezkit_flash_resource = {
782 .start = 0x20000000,
664d0403 783 .end = 0x21ffffff,
de8c43f2
MF		 784 .flags = IORESOURCE_MEM,
785};
786
787static struct platform_device ezkit_flash_device = {
788 .name = "physmap-flash",
789 .id = 0,
790 .dev = {
791 .platform_data = &ezkit_flash_data,
792 },
793 .num_resources = 1,
794 .resource = &ezkit_flash_resource,
795};
793dc27b 796#endif
de8c43f2 797
c6c4d7bb
BW		 798#if defined(CONFIG_MTD_M25P80) \
799 || defined(CONFIG_MTD_M25P80_MODULE)
800/* SPI flash chip (m25p16) */
801static struct mtd_partition bfin_spi_flash_partitions[] = {
802 {
aa582977 803 .name = "bootloader(spi)",
c6c4d7bb
BW		 804 .size = 0x00040000,
805 .offset = 0,
806 .mask_flags = MTD_CAP_ROM
807 }, {
aa582977 808 .name = "linux kernel(spi)",
edf05641
MF		 809 .size = MTDPART_SIZ_FULL,
810 .offset = MTDPART_OFS_APPEND,
c6c4d7bb
BW		 811 }
812};
813
814static struct flash_platform_data bfin_spi_flash_data = {
815 .name = "m25p80",
816 .parts = bfin_spi_flash_partitions,
817 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
818 .type = "m25p16",
819};
820
821static struct bfin5xx_spi_chip spi_flash_chip_info = {
822 .enable_dma = 0, /* use dma transfer with this chip*/
823 .bits_per_word = 8,
c6c4d7bb
BW		 824};
825#endif
826
37fa2421
BS		 827#if defined(CONFIG_SND_BLACKFIN_AD1836) \
828 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
829static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
830 .enable_dma = 0,
831 .bits_per_word = 16,
832};
833#endif
834
c6c4d7bb
BW		 835#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
836static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
c6c4d7bb
BW		 837 .enable_dma = 0,
838 .bits_per_word = 16,
839};
840
841static const struct ad7877_platform_data bfin_ad7877_ts_info = {
842 .model = 7877,
843 .vref_delay_usecs = 50, /* internal, no capacitor */
844 .x_plate_ohms = 419,
845 .y_plate_ohms = 486,
846 .pressure_max = 1000,
847 .pressure_min = 0,
848 .stopacq_polarity = 1,
849 .first_conversion_delay = 3,
850 .acquisition_time = 1,
851 .averaging = 1,
852 .pen_down_acc_interval = 1,
853};
854#endif
855
6e668936
MH		 856#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
857static struct bfin5xx_spi_chip spidev_chip_info = {
858 .enable_dma = 0,
859 .bits_per_word = 8,
860};
861#endif
862
ffc4d8bc
MH		 863#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
864static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
865 .enable_dma = 0, /* use dma transfer with this chip*/
866 .bits_per_word = 8,
ffc4d8bc
MH		 867};
868#endif
869
5bda2723 870static struct spi_board_info bfin_spi_board_info[] __initdata = {
c6c4d7bb
BW		 871#if defined(CONFIG_MTD_M25P80) \
872 || defined(CONFIG_MTD_M25P80_MODULE)
873 {
874 /* the modalias must be the same as spi device driver name */
875 .modalias = "m25p80", /* Name of spi_driver for this device */
876 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
877 .bus_num = 0, /* Framework bus number */
878 .chip_select = 1, /* SPI_SSEL1*/
879 .platform_data = &bfin_spi_flash_data,
880 .controller_data = &spi_flash_chip_info,
881 .mode = SPI_MODE_3,
882 },
883#endif
37fa2421
BS		 884#if defined(CONFIG_SND_BLACKFIN_AD1836) \
885 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
886 {
dac98174 887 .modalias = "ad1836",
37fa2421
BS		 888 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
889 .bus_num = 1,
890 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
891 .controller_data = &ad1836_spi_chip_info,
892 },
893#endif
c6c4d7bb 894#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
ffc4d8bc
MH		 895 {
896 .modalias = "ad7877",
897 .platform_data = &bfin_ad7877_ts_info,
898 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
899 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
900 .bus_num = 0,
901 .chip_select = 2,
902 .controller_data = &spi_ad7877_chip_info,
903 },
c6c4d7bb 904#endif
6e668936
MH		 905#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
906 {
907 .modalias = "spidev",
908 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
909 .bus_num = 0,
910 .chip_select = 1,
911 .controller_data = &spidev_chip_info,
912 },
913#endif
ffc4d8bc
MH		 914#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
915 {
916 .modalias = "adxl34x",
917 .platform_data = &adxl34x_info,
918 .irq = IRQ_PC5,
919 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
920 .bus_num = 1,
921 .chip_select = 2,
922 .controller_data = &spi_adxl34x_chip_info,
923 .mode = SPI_MODE_3,
924 },
925#endif
c6c4d7bb 926};
5bda2723 927#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb
BW		 928/* SPI (0) */
929static struct resource bfin_spi0_resource[] = {
930 [0] = {
931 .start = SPI0_REGBASE,
932 .end = SPI0_REGBASE + 0xFF,
933 .flags = IORESOURCE_MEM,
934 },
935 [1] = {
936 .start = CH_SPI0,
937 .end = CH_SPI0,
53122693
YL		 938 .flags = IORESOURCE_DMA,
939 },
940 [2] = {
941 .start = IRQ_SPI0,
942 .end = IRQ_SPI0,
c6c4d7bb
BW		 943 .flags = IORESOURCE_IRQ,
944 }
945};
946
947/* SPI (1) */
948static struct resource bfin_spi1_resource[] = {
949 [0] = {
950 .start = SPI1_REGBASE,
951 .end = SPI1_REGBASE + 0xFF,
952 .flags = IORESOURCE_MEM,
953 },
954 [1] = {
955 .start = CH_SPI1,
956 .end = CH_SPI1,
53122693
YL		 957 .flags = IORESOURCE_DMA,
958 },
959 [2] = {
960 .start = IRQ_SPI1,
961 .end = IRQ_SPI1,
c6c4d7bb
BW		 962 .flags = IORESOURCE_IRQ,
963 }
964};
965
966/* SPI controller data */
5d448dd5 967static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
4e4d496e 968 .num_chipselect = 3,
c6c4d7bb 969 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 970 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
c6c4d7bb
BW		 971};
972
973static struct platform_device bf54x_spi_master0 = {
974 .name = "bfin-spi",
975 .id = 0, /* Bus number */
976 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
977 .resource = bfin_spi0_resource,
978 .dev = {
5d448dd5 979 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
c6c4d7bb
BW		 980 },
981};
982
5d448dd5 983static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
4e4d496e 984 .num_chipselect = 3,
5d448dd5
BW		 985 .enable_dma = 1, /* master has the ability to do dma transfer */
986 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
987};
988
c6c4d7bb
BW		 989static struct platform_device bf54x_spi_master1 = {
990 .name = "bfin-spi",
991 .id = 1, /* Bus number */
992 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
993 .resource = bfin_spi1_resource,
994 .dev = {
5d448dd5 995 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
c6c4d7bb
BW		 996 },
997};
998#endif /* spi master and devices */
999
1000#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1001static struct resource bfin_twi0_resource[] = {
1002 [0] = {
1003 .start = TWI0_REGBASE,
1004 .end = TWI0_REGBASE + 0xFF,
1005 .flags = IORESOURCE_MEM,
1006 },
1007 [1] = {
1008 .start = IRQ_TWI0,
1009 .end = IRQ_TWI0,
1010 .flags = IORESOURCE_IRQ,
1011 },
1012};
1013
1014static struct platform_device i2c_bfin_twi0_device = {
1015 .name = "i2c-bfin-twi",
1016 .id = 0,
1017 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1018 .resource = bfin_twi0_resource,
1019};
1020
7160e950 1021#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
c6c4d7bb
BW		 1022static struct resource bfin_twi1_resource[] = {
1023 [0] = {
1024 .start = TWI1_REGBASE,
1025 .end = TWI1_REGBASE + 0xFF,
1026 .flags = IORESOURCE_MEM,
1027 },
1028 [1] = {
1029 .start = IRQ_TWI1,
1030 .end = IRQ_TWI1,
1031 .flags = IORESOURCE_IRQ,
1032 },
1033};
1034
1035static struct platform_device i2c_bfin_twi1_device = {
1036 .name = "i2c-bfin-twi",
1037 .id = 1,
1038 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1039 .resource = bfin_twi1_resource,
1040};
1041#endif
7160e950 1042#endif
c6c4d7bb 1043
81d9c7f2
BW		 1044static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1045};
1046
1047#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1048static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
ebd58333 1049#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
81d9c7f2
BW		 1050 {
1051 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 1052 },
1053#endif
204844eb 1054#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
81d9c7f2
BW		 1055 {
1056 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
81d9c7f2
BW		 1057 .irq = 212,
1058 },
1059#endif
ffc4d8bc
MH		 1060#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1061 {
1062 I2C_BOARD_INFO("adxl34x", 0x53),
1063 .irq = IRQ_PC5,
1064 .platform_data = (void *)&adxl34x_info,
1065 },
1066#endif
81d9c7f2
BW		 1067};
1068#endif
81d9c7f2 1069
2463ef22
MH		 1070#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1071#include <linux/gpio_keys.h>
1072
1073static struct gpio_keys_button bfin_gpio_keys_table[] = {
1074 {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
1075 {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
1076 {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
1077 {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
1078};
1079
1080static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1081 .buttons = bfin_gpio_keys_table,
1082 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1083};
1084
1085static struct platform_device bfin_device_gpiokeys = {
1086 .name = "gpio-keys",
1087 .dev = {
1088 .platform_data = &bfin_gpio_keys_data,
1089 },
1090};
1091#endif
1092
14b03204
MH		 1093static const unsigned int cclk_vlev_datasheet[] =
1094{
1095/*
1096 * Internal VLEV BF54XSBBC1533
1097 ****temporarily using these values until data sheet is updated
1098 */
1099 VRPAIR(VLEV_085, 150000000),
1100 VRPAIR(VLEV_090, 250000000),
1101 VRPAIR(VLEV_110, 276000000),
1102 VRPAIR(VLEV_115, 301000000),
1103 VRPAIR(VLEV_120, 525000000),
1104 VRPAIR(VLEV_125, 550000000),
1105 VRPAIR(VLEV_130, 600000000),
1106};
1107
1108static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1109 .tuple_tab = cclk_vlev_datasheet,
1110 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1111 .vr_settling_time = 25 /* us */,
1112};
1113
1114static struct platform_device bfin_dpmc = {
1115 .name = "bfin dpmc",
1116 .dev = {
1117 .platform_data = &bfin_dmpc_vreg_data,
1118 },
1119};
1120
24a07a12 1121static struct platform_device *ezkit_devices[] __initdata = {
14b03204
MH		 1122
1123 &bfin_dpmc,
1124
24a07a12
RH		 1125#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1126 &rtc_device,
1127#endif
1128
1129#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 1130#ifdef CONFIG_SERIAL_BFIN_UART0
1131 &bfin_uart0_device,
1132#endif
1133#ifdef CONFIG_SERIAL_BFIN_UART1
1134 &bfin_uart1_device,
1135#endif
1136#ifdef CONFIG_SERIAL_BFIN_UART2
1137 &bfin_uart2_device,
1138#endif
1139#ifdef CONFIG_SERIAL_BFIN_UART3
1140 &bfin_uart3_device,
1141#endif
24a07a12 1142#endif
c6c4d7bb 1143
5be36d22 1144#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 1145#ifdef CONFIG_BFIN_SIR0
1146 &bfin_sir0_device,
1147#endif
1148#ifdef CONFIG_BFIN_SIR1
1149 &bfin_sir1_device,
1150#endif
1151#ifdef CONFIG_BFIN_SIR2
1152 &bfin_sir2_device,
1153#endif
1154#ifdef CONFIG_BFIN_SIR3
1155 &bfin_sir3_device,
1156#endif
5be36d22
GY		 1157#endif
1158
c6c4d7bb
BW		 1159#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
1160 &bf54x_lq043_device,
1161#endif
1162
1163#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
1164 &smsc911x_device,
1165#endif
1166
c6c4d7bb
BW		 1167#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1168 &musb_device,
1169#endif
1170
3f375690
MH		 1171#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1172 &bfin_isp1760_device,
1173#endif
1174
706a01b1
BS		 1175#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1176 &bfin_can_device,
1177#endif
1178
c6c4d7bb
BW		 1179#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
1180 &bfin_atapi_device,
1181#endif
1182
1183#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1184 &bf5xx_nand_device,
1185#endif
1186
3d7e6cf8 1187#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
c6c4d7bb
BW		 1188 &bf54x_sdh_device,
1189#endif
1190
1191#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1192 &bf54x_spi_master0,
d4b1d273 1193 &bf54x_spi_master1,
c6c4d7bb
BW		 1194#endif
1195
1196#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
1197 &bf54x_kpad_device,
1198#endif
1199
adfc0467 1200#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 1201 &bfin_rotary_device,
1202#endif
1203
c6c4d7bb
BW		 1204#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1205 &i2c_bfin_twi0_device,
7160e950 1206#if !defined(CONFIG_BF542)
c6c4d7bb
BW		 1207 &i2c_bfin_twi1_device,
1208#endif
7160e950 1209#endif
2463ef22
MH		 1210
1211#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1212 &bfin_device_gpiokeys,
1213#endif
cad2ab65 1214
793dc27b 1215#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1216 &ezkit_flash_device,
793dc27b 1217#endif
24a07a12
RH		 1218};
1219
a01d7a76 1220static int __init ezkit_init(void)
24a07a12 1221{
b85d858b 1222 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2 1223
81d9c7f2
BW		 1224 i2c_register_board_info(0, bfin_i2c_board_info0,
1225 ARRAY_SIZE(bfin_i2c_board_info0));
1226#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1227 i2c_register_board_info(1, bfin_i2c_board_info1,
1228 ARRAY_SIZE(bfin_i2c_board_info1));
81d9c7f2
BW		 1229#endif
1230
24a07a12 1231 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
c6c4d7bb 1232
5bda2723 1233 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb 1234
24a07a12
RH		 1235 return 0;
1236}
1237
a01d7a76 1238arch_initcall(ezkit_init);
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