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db68254f | 1 | /* |
96f1050d RG |
2 | * Copyright 2004-2009 Analog Devices Inc. |
3 | * 2008-2009 Bluetechnix | |
4 | * 2005 National ICT Australia (NICTA) | |
5 | * Aidan Williams <aidan@nicta.com.au> | |
db68254f | 6 | * |
96f1050d | 7 | * Licensed under the GPL-2 or later. |
db68254f MH |
8 | */ |
9 | ||
10 | #include <linux/device.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/mtd/mtd.h> | |
13 | #include <linux/mtd/partitions.h> | |
2de73e71 | 14 | #include <linux/mtd/physmap.h> |
db68254f MH |
15 | #include <linux/spi/spi.h> |
16 | #include <linux/spi/flash.h> | |
17 | #include <linux/irq.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/usb/musb.h> | |
20 | #include <asm/bfin5xx_spi.h> | |
db68254f MH |
21 | #include <asm/dma.h> |
22 | #include <asm/gpio.h> | |
23 | #include <asm/nand.h> | |
24 | #include <asm/portmux.h> | |
8d8921a2 | 25 | #include <asm/bfin_sdh.h> |
639f6571 | 26 | #include <mach/bf54x_keys.h> |
14b03204 | 27 | #include <asm/dpmc.h> |
db68254f MH |
28 | #include <linux/input.h> |
29 | #include <linux/spi/ad7877.h> | |
30 | ||
31 | /* | |
32 | * Name the Board for the /proc/cpuinfo | |
33 | */ | |
34 | const char bfin_board_name[] = "Bluetechnix CM-BF548"; | |
35 | ||
36 | /* | |
37 | * Driver needs to know address, irq and flag pin. | |
38 | */ | |
39 | ||
40 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) | |
41 | ||
639f6571 | 42 | #include <mach/bf54x-lq043.h> |
db68254f MH |
43 | |
44 | static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { | |
45 | .width = 480, | |
46 | .height = 272, | |
47 | .xres = {480, 480, 480}, | |
48 | .yres = {272, 272, 272}, | |
49 | .bpp = {24, 24, 24}, | |
50 | .disp = GPIO_PE3, | |
51 | }; | |
52 | ||
53 | static struct resource bf54x_lq043_resources[] = { | |
54 | { | |
55 | .start = IRQ_EPPI0_ERR, | |
56 | .end = IRQ_EPPI0_ERR, | |
57 | .flags = IORESOURCE_IRQ, | |
58 | }, | |
59 | }; | |
60 | ||
61 | static struct platform_device bf54x_lq043_device = { | |
62 | .name = "bf54x-lq043", | |
63 | .id = -1, | |
64 | .num_resources = ARRAY_SIZE(bf54x_lq043_resources), | |
65 | .resource = bf54x_lq043_resources, | |
66 | .dev = { | |
67 | .platform_data = &bf54x_lq043_data, | |
68 | }, | |
69 | }; | |
70 | #endif | |
71 | ||
72 | #if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE) | |
73 | static unsigned int bf548_keymap[] = { | |
74 | KEYVAL(0, 0, KEY_ENTER), | |
75 | KEYVAL(0, 1, KEY_HELP), | |
76 | KEYVAL(0, 2, KEY_0), | |
77 | KEYVAL(0, 3, KEY_BACKSPACE), | |
78 | KEYVAL(1, 0, KEY_TAB), | |
79 | KEYVAL(1, 1, KEY_9), | |
80 | KEYVAL(1, 2, KEY_8), | |
81 | KEYVAL(1, 3, KEY_7), | |
82 | KEYVAL(2, 0, KEY_DOWN), | |
83 | KEYVAL(2, 1, KEY_6), | |
84 | KEYVAL(2, 2, KEY_5), | |
85 | KEYVAL(2, 3, KEY_4), | |
86 | KEYVAL(3, 0, KEY_UP), | |
87 | KEYVAL(3, 1, KEY_3), | |
88 | KEYVAL(3, 2, KEY_2), | |
89 | KEYVAL(3, 3, KEY_1), | |
90 | }; | |
91 | ||
92 | static struct bfin_kpad_platform_data bf54x_kpad_data = { | |
93 | .rows = 4, | |
94 | .cols = 4, | |
95 | .keymap = bf548_keymap, | |
96 | .keymapsize = ARRAY_SIZE(bf548_keymap), | |
97 | .repeat = 0, | |
98 | .debounce_time = 5000, /* ns (5ms) */ | |
99 | .coldrive_time = 1000, /* ns (1ms) */ | |
100 | .keyup_test_interval = 50, /* ms (50ms) */ | |
101 | }; | |
102 | ||
103 | static struct resource bf54x_kpad_resources[] = { | |
104 | { | |
105 | .start = IRQ_KEY, | |
106 | .end = IRQ_KEY, | |
107 | .flags = IORESOURCE_IRQ, | |
108 | }, | |
109 | }; | |
110 | ||
111 | static struct platform_device bf54x_kpad_device = { | |
112 | .name = "bf54x-keys", | |
113 | .id = -1, | |
114 | .num_resources = ARRAY_SIZE(bf54x_kpad_resources), | |
115 | .resource = bf54x_kpad_resources, | |
116 | .dev = { | |
117 | .platform_data = &bf54x_kpad_data, | |
118 | }, | |
119 | }; | |
120 | #endif | |
121 | ||
122 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | |
123 | static struct platform_device rtc_device = { | |
124 | .name = "rtc-bfin", | |
125 | .id = -1, | |
126 | }; | |
127 | #endif | |
128 | ||
129 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
db68254f | 130 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
6bd1fbea | 131 | static struct resource bfin_uart0_resources[] = { |
db68254f | 132 | { |
6bd1fbea SZ |
133 | .start = UART0_DLL, |
134 | .end = UART0_RBR+2, | |
db68254f MH |
135 | .flags = IORESOURCE_MEM, |
136 | }, | |
6bd1fbea SZ |
137 | { |
138 | .start = IRQ_UART0_RX, | |
139 | .end = IRQ_UART0_RX+1, | |
140 | .flags = IORESOURCE_IRQ, | |
141 | }, | |
142 | { | |
143 | .start = IRQ_UART0_ERROR, | |
144 | .end = IRQ_UART0_ERROR, | |
145 | .flags = IORESOURCE_IRQ, | |
146 | }, | |
147 | { | |
148 | .start = CH_UART0_TX, | |
149 | .end = CH_UART0_TX, | |
150 | .flags = IORESOURCE_DMA, | |
151 | }, | |
152 | { | |
153 | .start = CH_UART0_RX, | |
154 | .end = CH_UART0_RX, | |
155 | .flags = IORESOURCE_DMA, | |
156 | }, | |
157 | }; | |
158 | ||
159 | unsigned short bfin_uart0_peripherals[] = { | |
160 | P_UART0_TX, P_UART0_RX, 0 | |
161 | }; | |
162 | ||
163 | static struct platform_device bfin_uart0_device = { | |
164 | .name = "bfin-uart", | |
165 | .id = 0, | |
166 | .num_resources = ARRAY_SIZE(bfin_uart0_resources), | |
167 | .resource = bfin_uart0_resources, | |
168 | .dev = { | |
169 | .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ | |
170 | }, | |
171 | }; | |
db68254f MH |
172 | #endif |
173 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
6bd1fbea | 174 | static struct resource bfin_uart1_resources[] = { |
db68254f | 175 | { |
6bd1fbea SZ |
176 | .start = UART1_DLL, |
177 | .end = UART1_RBR+2, | |
db68254f MH |
178 | .flags = IORESOURCE_MEM, |
179 | }, | |
6bd1fbea SZ |
180 | { |
181 | .start = IRQ_UART1_RX, | |
182 | .end = IRQ_UART1_RX+1, | |
183 | .flags = IORESOURCE_IRQ, | |
184 | }, | |
185 | { | |
186 | .start = IRQ_UART1_ERROR, | |
187 | .end = IRQ_UART1_ERROR, | |
188 | .flags = IORESOURCE_IRQ, | |
189 | }, | |
190 | { | |
191 | .start = CH_UART1_TX, | |
192 | .end = CH_UART1_TX, | |
193 | .flags = IORESOURCE_DMA, | |
194 | }, | |
195 | { | |
196 | .start = CH_UART1_RX, | |
197 | .end = CH_UART1_RX, | |
198 | .flags = IORESOURCE_DMA, | |
199 | }, | |
200 | #ifdef CONFIG_BFIN_UART1_CTSRTS | |
201 | { /* CTS pin -- 0 means not supported */ | |
202 | .start = GPIO_PE10, | |
203 | .end = GPIO_PE10, | |
204 | .flags = IORESOURCE_IO, | |
205 | }, | |
206 | { /* RTS pin -- 0 means not supported */ | |
207 | .start = GPIO_PE9, | |
208 | .end = GPIO_PE9, | |
209 | .flags = IORESOURCE_IO, | |
210 | }, | |
211 | #endif | |
212 | }; | |
213 | ||
214 | unsigned short bfin_uart1_peripherals[] = { | |
215 | P_UART1_TX, P_UART1_RX, | |
216 | #ifdef CONFIG_BFIN_UART1_CTSRTS | |
217 | P_UART1_RTS, P_UART1_CTS, | |
218 | #endif | |
219 | 0 | |
220 | }; | |
221 | ||
222 | static struct platform_device bfin_uart1_device = { | |
223 | .name = "bfin-uart", | |
224 | .id = 1, | |
225 | .num_resources = ARRAY_SIZE(bfin_uart1_resources), | |
226 | .resource = bfin_uart1_resources, | |
227 | .dev = { | |
228 | .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ | |
229 | }, | |
230 | }; | |
db68254f MH |
231 | #endif |
232 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
6bd1fbea | 233 | static struct resource bfin_uart2_resources[] = { |
db68254f | 234 | { |
6bd1fbea SZ |
235 | .start = UART2_DLL, |
236 | .end = UART2_RBR+2, | |
db68254f MH |
237 | .flags = IORESOURCE_MEM, |
238 | }, | |
6bd1fbea SZ |
239 | { |
240 | .start = IRQ_UART2_RX, | |
241 | .end = IRQ_UART2_RX+1, | |
242 | .flags = IORESOURCE_IRQ, | |
243 | }, | |
244 | { | |
245 | .start = IRQ_UART2_ERROR, | |
246 | .end = IRQ_UART2_ERROR, | |
247 | .flags = IORESOURCE_IRQ, | |
248 | }, | |
249 | { | |
250 | .start = CH_UART2_TX, | |
251 | .end = CH_UART2_TX, | |
252 | .flags = IORESOURCE_DMA, | |
253 | }, | |
254 | { | |
255 | .start = CH_UART2_RX, | |
256 | .end = CH_UART2_RX, | |
257 | .flags = IORESOURCE_DMA, | |
258 | }, | |
259 | }; | |
260 | ||
261 | unsigned short bfin_uart2_peripherals[] = { | |
262 | P_UART2_TX, P_UART2_RX, 0 | |
263 | }; | |
264 | ||
265 | static struct platform_device bfin_uart2_device = { | |
266 | .name = "bfin-uart", | |
267 | .id = 2, | |
268 | .num_resources = ARRAY_SIZE(bfin_uart2_resources), | |
269 | .resource = bfin_uart2_resources, | |
270 | .dev = { | |
271 | .platform_data = &bfin_uart2_peripherals, /* Passed to driver */ | |
272 | }, | |
273 | }; | |
db68254f MH |
274 | #endif |
275 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
6bd1fbea | 276 | static struct resource bfin_uart3_resources[] = { |
db68254f | 277 | { |
6bd1fbea SZ |
278 | .start = UART3_DLL, |
279 | .end = UART3_RBR+2, | |
8606801b | 280 | .flags = IORESOURCE_MEM, |
db68254f | 281 | }, |
6bd1fbea SZ |
282 | { |
283 | .start = IRQ_UART3_RX, | |
284 | .end = IRQ_UART3_RX+1, | |
285 | .flags = IORESOURCE_IRQ, | |
286 | }, | |
287 | { | |
288 | .start = IRQ_UART3_ERROR, | |
289 | .end = IRQ_UART3_ERROR, | |
290 | .flags = IORESOURCE_IRQ, | |
291 | }, | |
292 | { | |
293 | .start = CH_UART3_TX, | |
294 | .end = CH_UART3_TX, | |
295 | .flags = IORESOURCE_DMA, | |
296 | }, | |
297 | { | |
298 | .start = CH_UART3_RX, | |
299 | .end = CH_UART3_RX, | |
300 | .flags = IORESOURCE_DMA, | |
301 | }, | |
302 | #ifdef CONFIG_BFIN_UART3_CTSRTS | |
303 | { /* CTS pin -- 0 means not supported */ | |
304 | .start = GPIO_PB3, | |
305 | .end = GPIO_PB3, | |
306 | .flags = IORESOURCE_IO, | |
307 | }, | |
308 | { /* RTS pin -- 0 means not supported */ | |
309 | .start = GPIO_PB2, | |
310 | .end = GPIO_PB2, | |
311 | .flags = IORESOURCE_IO, | |
312 | }, | |
db68254f MH |
313 | #endif |
314 | }; | |
315 | ||
6bd1fbea SZ |
316 | unsigned short bfin_uart3_peripherals[] = { |
317 | P_UART3_TX, P_UART3_RX, | |
318 | #ifdef CONFIG_BFIN_UART3_CTSRTS | |
319 | P_UART3_RTS, P_UART3_CTS, | |
320 | #endif | |
321 | 0 | |
322 | }; | |
323 | ||
324 | static struct platform_device bfin_uart3_device = { | |
db68254f | 325 | .name = "bfin-uart", |
6bd1fbea SZ |
326 | .id = 3, |
327 | .num_resources = ARRAY_SIZE(bfin_uart3_resources), | |
328 | .resource = bfin_uart3_resources, | |
329 | .dev = { | |
330 | .platform_data = &bfin_uart3_peripherals, /* Passed to driver */ | |
331 | }, | |
db68254f MH |
332 | }; |
333 | #endif | |
6bd1fbea | 334 | #endif |
db68254f | 335 | |
5be36d22 | 336 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
5be36d22 | 337 | #ifdef CONFIG_BFIN_SIR0 |
42bd8bcb | 338 | static struct resource bfin_sir0_resources[] = { |
5be36d22 GY |
339 | { |
340 | .start = 0xFFC00400, | |
341 | .end = 0xFFC004FF, | |
342 | .flags = IORESOURCE_MEM, | |
343 | }, | |
42bd8bcb GY |
344 | { |
345 | .start = IRQ_UART0_RX, | |
346 | .end = IRQ_UART0_RX+1, | |
347 | .flags = IORESOURCE_IRQ, | |
348 | }, | |
349 | { | |
350 | .start = CH_UART0_RX, | |
351 | .end = CH_UART0_RX+1, | |
352 | .flags = IORESOURCE_DMA, | |
353 | }, | |
354 | }; | |
355 | static struct platform_device bfin_sir0_device = { | |
356 | .name = "bfin_sir", | |
357 | .id = 0, | |
358 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | |
359 | .resource = bfin_sir0_resources, | |
360 | }; | |
5be36d22 GY |
361 | #endif |
362 | #ifdef CONFIG_BFIN_SIR1 | |
42bd8bcb | 363 | static struct resource bfin_sir1_resources[] = { |
5be36d22 GY |
364 | { |
365 | .start = 0xFFC02000, | |
366 | .end = 0xFFC020FF, | |
367 | .flags = IORESOURCE_MEM, | |
368 | }, | |
42bd8bcb GY |
369 | { |
370 | .start = IRQ_UART1_RX, | |
371 | .end = IRQ_UART1_RX+1, | |
372 | .flags = IORESOURCE_IRQ, | |
373 | }, | |
374 | { | |
375 | .start = CH_UART1_RX, | |
376 | .end = CH_UART1_RX+1, | |
377 | .flags = IORESOURCE_DMA, | |
378 | }, | |
379 | }; | |
380 | static struct platform_device bfin_sir1_device = { | |
381 | .name = "bfin_sir", | |
382 | .id = 1, | |
383 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | |
384 | .resource = bfin_sir1_resources, | |
385 | }; | |
5be36d22 GY |
386 | #endif |
387 | #ifdef CONFIG_BFIN_SIR2 | |
42bd8bcb | 388 | static struct resource bfin_sir2_resources[] = { |
5be36d22 GY |
389 | { |
390 | .start = 0xFFC02100, | |
391 | .end = 0xFFC021FF, | |
392 | .flags = IORESOURCE_MEM, | |
393 | }, | |
42bd8bcb GY |
394 | { |
395 | .start = IRQ_UART2_RX, | |
396 | .end = IRQ_UART2_RX+1, | |
397 | .flags = IORESOURCE_IRQ, | |
398 | }, | |
399 | { | |
400 | .start = CH_UART2_RX, | |
401 | .end = CH_UART2_RX+1, | |
402 | .flags = IORESOURCE_DMA, | |
403 | }, | |
404 | }; | |
405 | static struct platform_device bfin_sir2_device = { | |
406 | .name = "bfin_sir", | |
407 | .id = 2, | |
408 | .num_resources = ARRAY_SIZE(bfin_sir2_resources), | |
409 | .resource = bfin_sir2_resources, | |
410 | }; | |
5be36d22 GY |
411 | #endif |
412 | #ifdef CONFIG_BFIN_SIR3 | |
42bd8bcb | 413 | static struct resource bfin_sir3_resources[] = { |
5be36d22 GY |
414 | { |
415 | .start = 0xFFC03100, | |
416 | .end = 0xFFC031FF, | |
417 | .flags = IORESOURCE_MEM, | |
418 | }, | |
42bd8bcb GY |
419 | { |
420 | .start = IRQ_UART3_RX, | |
421 | .end = IRQ_UART3_RX+1, | |
422 | .flags = IORESOURCE_IRQ, | |
423 | }, | |
424 | { | |
425 | .start = CH_UART3_RX, | |
426 | .end = CH_UART3_RX+1, | |
427 | .flags = IORESOURCE_DMA, | |
428 | }, | |
5be36d22 | 429 | }; |
42bd8bcb | 430 | static struct platform_device bfin_sir3_device = { |
5be36d22 | 431 | .name = "bfin_sir", |
42bd8bcb GY |
432 | .id = 3, |
433 | .num_resources = ARRAY_SIZE(bfin_sir3_resources), | |
434 | .resource = bfin_sir3_resources, | |
5be36d22 GY |
435 | }; |
436 | #endif | |
42bd8bcb | 437 | #endif |
5be36d22 | 438 | |
db68254f | 439 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
9c21453e HK |
440 | #include <linux/smsc911x.h> |
441 | ||
db68254f MH |
442 | static struct resource smsc911x_resources[] = { |
443 | { | |
444 | .name = "smsc911x-memory", | |
445 | .start = 0x24000000, | |
446 | .end = 0x24000000 + 0xFF, | |
447 | .flags = IORESOURCE_MEM, | |
448 | }, | |
449 | { | |
450 | .start = IRQ_PE6, | |
451 | .end = IRQ_PE6, | |
452 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | |
453 | }, | |
454 | }; | |
9c21453e HK |
455 | |
456 | static struct smsc911x_platform_config smsc911x_config = { | |
457 | .flags = SMSC911X_USE_16BIT, | |
458 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | |
459 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | |
460 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
461 | }; | |
462 | ||
db68254f MH |
463 | static struct platform_device smsc911x_device = { |
464 | .name = "smsc911x", | |
465 | .id = 0, | |
466 | .num_resources = ARRAY_SIZE(smsc911x_resources), | |
467 | .resource = smsc911x_resources, | |
9c21453e HK |
468 | .dev = { |
469 | .platform_data = &smsc911x_config, | |
470 | }, | |
db68254f MH |
471 | }; |
472 | #endif | |
473 | ||
474 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) | |
475 | static struct resource musb_resources[] = { | |
476 | [0] = { | |
477 | .start = 0xFFC03C00, | |
478 | .end = 0xFFC040FF, | |
479 | .flags = IORESOURCE_MEM, | |
480 | }, | |
481 | [1] = { /* general IRQ */ | |
482 | .start = IRQ_USB_INT0, | |
483 | .end = IRQ_USB_INT0, | |
484 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
485 | }, | |
486 | [2] = { /* DMA IRQ */ | |
487 | .start = IRQ_USB_DMA, | |
488 | .end = IRQ_USB_DMA, | |
489 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
490 | }, | |
491 | }; | |
492 | ||
50041acb BW |
493 | static struct musb_hdrc_config musb_config = { |
494 | .multipoint = 0, | |
495 | .dyn_fifo = 0, | |
496 | .soft_con = 1, | |
497 | .dma = 1, | |
fea05dac BW |
498 | .num_eps = 8, |
499 | .dma_channels = 8, | |
50041acb | 500 | .gpio_vrsel = GPIO_PH6, |
85eb0e4b CC |
501 | /* Some custom boards need to be active low, just set it to "0" |
502 | * if it is the case. | |
503 | */ | |
504 | .gpio_vrsel_active = 1, | |
50041acb BW |
505 | }; |
506 | ||
db68254f MH |
507 | static struct musb_hdrc_platform_data musb_plat = { |
508 | #if defined(CONFIG_USB_MUSB_OTG) | |
509 | .mode = MUSB_OTG, | |
510 | #elif defined(CONFIG_USB_MUSB_HDRC_HCD) | |
511 | .mode = MUSB_HOST, | |
512 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) | |
513 | .mode = MUSB_PERIPHERAL, | |
514 | #endif | |
50041acb | 515 | .config = &musb_config, |
db68254f MH |
516 | }; |
517 | ||
518 | static u64 musb_dmamask = ~(u32)0; | |
519 | ||
520 | static struct platform_device musb_device = { | |
521 | .name = "musb_hdrc", | |
522 | .id = 0, | |
523 | .dev = { | |
524 | .dma_mask = &musb_dmamask, | |
525 | .coherent_dma_mask = 0xffffffff, | |
526 | .platform_data = &musb_plat, | |
527 | }, | |
528 | .num_resources = ARRAY_SIZE(musb_resources), | |
529 | .resource = musb_resources, | |
530 | }; | |
531 | #endif | |
532 | ||
df5de261 SZ |
533 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
534 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART | |
535 | static struct resource bfin_sport0_uart_resources[] = { | |
536 | { | |
537 | .start = SPORT0_TCR1, | |
538 | .end = SPORT0_MRCS3+4, | |
539 | .flags = IORESOURCE_MEM, | |
540 | }, | |
541 | { | |
542 | .start = IRQ_SPORT0_RX, | |
543 | .end = IRQ_SPORT0_RX+1, | |
544 | .flags = IORESOURCE_IRQ, | |
545 | }, | |
546 | { | |
547 | .start = IRQ_SPORT0_ERROR, | |
548 | .end = IRQ_SPORT0_ERROR, | |
549 | .flags = IORESOURCE_IRQ, | |
550 | }, | |
551 | }; | |
552 | ||
553 | unsigned short bfin_sport0_peripherals[] = { | |
554 | P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, | |
555 | P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 | |
556 | }; | |
557 | ||
558 | static struct platform_device bfin_sport0_uart_device = { | |
559 | .name = "bfin-sport-uart", | |
560 | .id = 0, | |
561 | .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), | |
562 | .resource = bfin_sport0_uart_resources, | |
563 | .dev = { | |
564 | .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ | |
565 | }, | |
566 | }; | |
567 | #endif | |
568 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART | |
569 | static struct resource bfin_sport1_uart_resources[] = { | |
570 | { | |
571 | .start = SPORT1_TCR1, | |
572 | .end = SPORT1_MRCS3+4, | |
573 | .flags = IORESOURCE_MEM, | |
574 | }, | |
575 | { | |
576 | .start = IRQ_SPORT1_RX, | |
577 | .end = IRQ_SPORT1_RX+1, | |
578 | .flags = IORESOURCE_IRQ, | |
579 | }, | |
580 | { | |
581 | .start = IRQ_SPORT1_ERROR, | |
582 | .end = IRQ_SPORT1_ERROR, | |
583 | .flags = IORESOURCE_IRQ, | |
584 | }, | |
585 | }; | |
586 | ||
587 | unsigned short bfin_sport1_peripherals[] = { | |
588 | P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, | |
589 | P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 | |
590 | }; | |
591 | ||
592 | static struct platform_device bfin_sport1_uart_device = { | |
593 | .name = "bfin-sport-uart", | |
594 | .id = 1, | |
595 | .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), | |
596 | .resource = bfin_sport1_uart_resources, | |
597 | .dev = { | |
598 | .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ | |
599 | }, | |
600 | }; | |
601 | #endif | |
602 | #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART | |
603 | static struct resource bfin_sport2_uart_resources[] = { | |
604 | { | |
605 | .start = SPORT2_TCR1, | |
606 | .end = SPORT2_MRCS3+4, | |
607 | .flags = IORESOURCE_MEM, | |
608 | }, | |
609 | { | |
610 | .start = IRQ_SPORT2_RX, | |
611 | .end = IRQ_SPORT2_RX+1, | |
612 | .flags = IORESOURCE_IRQ, | |
613 | }, | |
614 | { | |
615 | .start = IRQ_SPORT2_ERROR, | |
616 | .end = IRQ_SPORT2_ERROR, | |
617 | .flags = IORESOURCE_IRQ, | |
618 | }, | |
619 | }; | |
620 | ||
621 | unsigned short bfin_sport2_peripherals[] = { | |
622 | P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, | |
623 | P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 | |
624 | }; | |
625 | ||
626 | static struct platform_device bfin_sport2_uart_device = { | |
627 | .name = "bfin-sport-uart", | |
628 | .id = 2, | |
629 | .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources), | |
630 | .resource = bfin_sport2_uart_resources, | |
631 | .dev = { | |
632 | .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ | |
633 | }, | |
634 | }; | |
635 | #endif | |
636 | #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART | |
637 | static struct resource bfin_sport3_uart_resources[] = { | |
638 | { | |
639 | .start = SPORT3_TCR1, | |
640 | .end = SPORT3_MRCS3+4, | |
641 | .flags = IORESOURCE_MEM, | |
642 | }, | |
643 | { | |
644 | .start = IRQ_SPORT3_RX, | |
645 | .end = IRQ_SPORT3_RX+1, | |
646 | .flags = IORESOURCE_IRQ, | |
647 | }, | |
648 | { | |
649 | .start = IRQ_SPORT3_ERROR, | |
650 | .end = IRQ_SPORT3_ERROR, | |
651 | .flags = IORESOURCE_IRQ, | |
652 | }, | |
653 | }; | |
654 | ||
655 | unsigned short bfin_sport3_peripherals[] = { | |
656 | P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, | |
657 | P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 | |
658 | }; | |
659 | ||
660 | static struct platform_device bfin_sport3_uart_device = { | |
661 | .name = "bfin-sport-uart", | |
662 | .id = 3, | |
663 | .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources), | |
664 | .resource = bfin_sport3_uart_resources, | |
665 | .dev = { | |
666 | .platform_data = &bfin_sport3_peripherals, /* Passed to driver */ | |
667 | }, | |
668 | }; | |
669 | #endif | |
670 | #endif | |
671 | ||
db68254f MH |
672 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) |
673 | static struct resource bfin_atapi_resources[] = { | |
674 | { | |
675 | .start = 0xFFC03800, | |
676 | .end = 0xFFC0386F, | |
677 | .flags = IORESOURCE_MEM, | |
678 | }, | |
679 | { | |
680 | .start = IRQ_ATAPI_ERR, | |
681 | .end = IRQ_ATAPI_ERR, | |
682 | .flags = IORESOURCE_IRQ, | |
683 | }, | |
684 | }; | |
685 | ||
686 | static struct platform_device bfin_atapi_device = { | |
687 | .name = "pata-bf54x", | |
688 | .id = -1, | |
689 | .num_resources = ARRAY_SIZE(bfin_atapi_resources), | |
690 | .resource = bfin_atapi_resources, | |
691 | }; | |
692 | #endif | |
693 | ||
694 | #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) | |
695 | static struct mtd_partition partition_info[] = { | |
696 | { | |
aa582977 | 697 | .name = "linux kernel(nand)", |
db68254f | 698 | .offset = 0, |
f4585a08 | 699 | .size = 4 * 1024 * 1024, |
db68254f MH |
700 | }, |
701 | { | |
aa582977 | 702 | .name = "file system(nand)", |
f4585a08 MF |
703 | .offset = 4 * 1024 * 1024, |
704 | .size = (256 - 4) * 1024 * 1024, | |
db68254f MH |
705 | }, |
706 | }; | |
707 | ||
708 | static struct bf5xx_nand_platform bf5xx_nand_platform = { | |
db68254f MH |
709 | .data_width = NFC_NWIDTH_8, |
710 | .partitions = partition_info, | |
711 | .nr_partitions = ARRAY_SIZE(partition_info), | |
712 | .rd_dly = 3, | |
713 | .wr_dly = 3, | |
714 | }; | |
715 | ||
716 | static struct resource bf5xx_nand_resources[] = { | |
717 | { | |
718 | .start = 0xFFC03B00, | |
719 | .end = 0xFFC03B4F, | |
720 | .flags = IORESOURCE_MEM, | |
721 | }, | |
722 | { | |
723 | .start = CH_NFC, | |
724 | .end = CH_NFC, | |
725 | .flags = IORESOURCE_IRQ, | |
726 | }, | |
727 | }; | |
728 | ||
729 | static struct platform_device bf5xx_nand_device = { | |
730 | .name = "bf5xx-nand", | |
731 | .id = 0, | |
732 | .num_resources = ARRAY_SIZE(bf5xx_nand_resources), | |
733 | .resource = bf5xx_nand_resources, | |
734 | .dev = { | |
735 | .platform_data = &bf5xx_nand_platform, | |
736 | }, | |
737 | }; | |
738 | #endif | |
739 | ||
740 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) | |
8d8921a2 MF |
741 | static struct bfin_sd_host bfin_sdh_data = { |
742 | .dma_chan = CH_SDH, | |
743 | .irq_int0 = IRQ_SDH_MASK0, | |
744 | .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, | |
745 | }; | |
746 | ||
db68254f MH |
747 | static struct platform_device bf54x_sdh_device = { |
748 | .name = "bfin-sdh", | |
749 | .id = 0, | |
8d8921a2 MF |
750 | .dev = { |
751 | .platform_data = &bfin_sdh_data, | |
752 | }, | |
db68254f MH |
753 | }; |
754 | #endif | |
755 | ||
bf80caf4 MH |
756 | #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) |
757 | unsigned short bfin_can_peripherals[] = { | |
758 | P_CAN0_RX, P_CAN0_TX, 0 | |
759 | }; | |
760 | ||
761 | static struct resource bfin_can_resources[] = { | |
762 | { | |
763 | .start = 0xFFC02A00, | |
764 | .end = 0xFFC02FFF, | |
765 | .flags = IORESOURCE_MEM, | |
766 | }, | |
767 | { | |
768 | .start = IRQ_CAN0_RX, | |
769 | .end = IRQ_CAN0_RX, | |
770 | .flags = IORESOURCE_IRQ, | |
771 | }, | |
772 | { | |
773 | .start = IRQ_CAN0_TX, | |
774 | .end = IRQ_CAN0_TX, | |
775 | .flags = IORESOURCE_IRQ, | |
776 | }, | |
777 | { | |
778 | .start = IRQ_CAN0_ERROR, | |
779 | .end = IRQ_CAN0_ERROR, | |
780 | .flags = IORESOURCE_IRQ, | |
781 | }, | |
782 | }; | |
783 | ||
784 | static struct platform_device bfin_can_device = { | |
785 | .name = "bfin_can", | |
786 | .num_resources = ARRAY_SIZE(bfin_can_resources), | |
787 | .resource = bfin_can_resources, | |
788 | .dev = { | |
789 | .platform_data = &bfin_can_peripherals, /* Passed to driver */ | |
790 | }, | |
791 | }; | |
792 | #endif | |
793 | ||
2de73e71 MF |
794 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
795 | static struct mtd_partition para_partitions[] = { | |
796 | { | |
797 | .name = "bootloader(nor)", | |
798 | .size = 0x40000, | |
799 | .offset = 0, | |
800 | }, { | |
801 | .name = "linux kernel(nor)", | |
9c21453e | 802 | .size = 0x100000, |
2de73e71 MF |
803 | .offset = MTDPART_OFS_APPEND, |
804 | }, { | |
805 | .name = "file system(nor)", | |
806 | .size = MTDPART_SIZ_FULL, | |
807 | .offset = MTDPART_OFS_APPEND, | |
808 | } | |
809 | }; | |
810 | ||
811 | static struct physmap_flash_data para_flash_data = { | |
812 | .width = 2, | |
813 | .parts = para_partitions, | |
814 | .nr_parts = ARRAY_SIZE(para_partitions), | |
815 | }; | |
816 | ||
817 | static struct resource para_flash_resource = { | |
818 | .start = 0x20000000, | |
819 | .end = 0x207fffff, | |
820 | .flags = IORESOURCE_MEM, | |
821 | }; | |
822 | ||
823 | static struct platform_device para_flash_device = { | |
824 | .name = "physmap-flash", | |
825 | .id = 0, | |
826 | .dev = { | |
827 | .platform_data = ¶_flash_data, | |
828 | }, | |
829 | .num_resources = 1, | |
830 | .resource = ¶_flash_resource, | |
831 | }; | |
832 | #endif | |
833 | ||
db68254f MH |
834 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
835 | /* all SPI peripherals info goes here */ | |
836 | #if defined(CONFIG_MTD_M25P80) \ | |
837 | || defined(CONFIG_MTD_M25P80_MODULE) | |
838 | /* SPI flash chip (m25p16) */ | |
839 | static struct mtd_partition bfin_spi_flash_partitions[] = { | |
840 | { | |
aa582977 | 841 | .name = "bootloader(spi)", |
db68254f MH |
842 | .size = 0x00040000, |
843 | .offset = 0, | |
844 | .mask_flags = MTD_CAP_ROM | |
845 | }, { | |
aa582977 | 846 | .name = "linux kernel(spi)", |
db68254f MH |
847 | .size = 0x1c0000, |
848 | .offset = 0x40000 | |
849 | } | |
850 | }; | |
851 | ||
852 | static struct flash_platform_data bfin_spi_flash_data = { | |
853 | .name = "m25p80", | |
854 | .parts = bfin_spi_flash_partitions, | |
855 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
856 | .type = "m25p16", | |
857 | }; | |
858 | ||
859 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
860 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
861 | .bits_per_word = 8, | |
db68254f MH |
862 | }; |
863 | #endif | |
864 | ||
865 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | |
866 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { | |
db68254f MH |
867 | .enable_dma = 0, |
868 | .bits_per_word = 16, | |
869 | }; | |
870 | ||
871 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { | |
872 | .model = 7877, | |
873 | .vref_delay_usecs = 50, /* internal, no capacitor */ | |
874 | .x_plate_ohms = 419, | |
875 | .y_plate_ohms = 486, | |
876 | .pressure_max = 1000, | |
877 | .pressure_min = 0, | |
878 | .stopacq_polarity = 1, | |
879 | .first_conversion_delay = 3, | |
880 | .acquisition_time = 1, | |
881 | .averaging = 1, | |
882 | .pen_down_acc_interval = 1, | |
883 | }; | |
884 | #endif | |
885 | ||
886 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | |
887 | static struct bfin5xx_spi_chip spidev_chip_info = { | |
888 | .enable_dma = 0, | |
889 | .bits_per_word = 8, | |
890 | }; | |
891 | #endif | |
892 | ||
893 | static struct spi_board_info bf54x_spi_board_info[] __initdata = { | |
894 | #if defined(CONFIG_MTD_M25P80) \ | |
895 | || defined(CONFIG_MTD_M25P80_MODULE) | |
896 | { | |
897 | /* the modalias must be the same as spi device driver name */ | |
898 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
899 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
900 | .bus_num = 0, /* Framework bus number */ | |
901 | .chip_select = 1, /* SPI_SSEL1*/ | |
902 | .platform_data = &bfin_spi_flash_data, | |
903 | .controller_data = &spi_flash_chip_info, | |
904 | .mode = SPI_MODE_3, | |
905 | }, | |
906 | #endif | |
907 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | |
908 | { | |
909 | .modalias = "ad7877", | |
910 | .platform_data = &bfin_ad7877_ts_info, | |
911 | .irq = IRQ_PJ11, | |
912 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | |
913 | .bus_num = 0, | |
914 | .chip_select = 2, | |
915 | .controller_data = &spi_ad7877_chip_info, | |
916 | }, | |
917 | #endif | |
918 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | |
919 | { | |
920 | .modalias = "spidev", | |
921 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
922 | .bus_num = 0, | |
923 | .chip_select = 1, | |
924 | .controller_data = &spidev_chip_info, | |
925 | }, | |
926 | #endif | |
927 | }; | |
928 | ||
929 | /* SPI (0) */ | |
930 | static struct resource bfin_spi0_resource[] = { | |
931 | [0] = { | |
932 | .start = SPI0_REGBASE, | |
933 | .end = SPI0_REGBASE + 0xFF, | |
934 | .flags = IORESOURCE_MEM, | |
935 | }, | |
936 | [1] = { | |
937 | .start = CH_SPI0, | |
938 | .end = CH_SPI0, | |
53122693 YL |
939 | .flags = IORESOURCE_DMA, |
940 | }, | |
941 | [2] = { | |
942 | .start = IRQ_SPI0, | |
943 | .end = IRQ_SPI0, | |
db68254f MH |
944 | .flags = IORESOURCE_IRQ, |
945 | } | |
946 | }; | |
947 | ||
948 | /* SPI (1) */ | |
949 | static struct resource bfin_spi1_resource[] = { | |
950 | [0] = { | |
951 | .start = SPI1_REGBASE, | |
952 | .end = SPI1_REGBASE + 0xFF, | |
953 | .flags = IORESOURCE_MEM, | |
954 | }, | |
955 | [1] = { | |
956 | .start = CH_SPI1, | |
957 | .end = CH_SPI1, | |
53122693 YL |
958 | .flags = IORESOURCE_DMA, |
959 | }, | |
960 | [2] = { | |
961 | .start = IRQ_SPI1, | |
962 | .end = IRQ_SPI1, | |
db68254f MH |
963 | .flags = IORESOURCE_IRQ, |
964 | } | |
965 | }; | |
966 | ||
967 | /* SPI controller data */ | |
968 | static struct bfin5xx_spi_master bf54x_spi_master_info0 = { | |
c5af5451 | 969 | .num_chipselect = 4, |
db68254f MH |
970 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
971 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | |
972 | }; | |
973 | ||
974 | static struct platform_device bf54x_spi_master0 = { | |
975 | .name = "bfin-spi", | |
976 | .id = 0, /* Bus number */ | |
977 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
978 | .resource = bfin_spi0_resource, | |
979 | .dev = { | |
980 | .platform_data = &bf54x_spi_master_info0, /* Passed to driver */ | |
981 | }, | |
982 | }; | |
983 | ||
984 | static struct bfin5xx_spi_master bf54x_spi_master_info1 = { | |
c5af5451 | 985 | .num_chipselect = 4, |
db68254f MH |
986 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
987 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | |
988 | }; | |
989 | ||
990 | static struct platform_device bf54x_spi_master1 = { | |
991 | .name = "bfin-spi", | |
992 | .id = 1, /* Bus number */ | |
993 | .num_resources = ARRAY_SIZE(bfin_spi1_resource), | |
994 | .resource = bfin_spi1_resource, | |
995 | .dev = { | |
996 | .platform_data = &bf54x_spi_master_info1, /* Passed to driver */ | |
997 | }, | |
998 | }; | |
999 | #endif /* spi master and devices */ | |
1000 | ||
1001 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | |
1002 | static struct resource bfin_twi0_resource[] = { | |
1003 | [0] = { | |
1004 | .start = TWI0_REGBASE, | |
1005 | .end = TWI0_REGBASE + 0xFF, | |
1006 | .flags = IORESOURCE_MEM, | |
1007 | }, | |
1008 | [1] = { | |
1009 | .start = IRQ_TWI0, | |
1010 | .end = IRQ_TWI0, | |
1011 | .flags = IORESOURCE_IRQ, | |
1012 | }, | |
1013 | }; | |
1014 | ||
1015 | static struct platform_device i2c_bfin_twi0_device = { | |
1016 | .name = "i2c-bfin-twi", | |
1017 | .id = 0, | |
1018 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), | |
1019 | .resource = bfin_twi0_resource, | |
1020 | }; | |
1021 | ||
1022 | #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ | |
1023 | static struct resource bfin_twi1_resource[] = { | |
1024 | [0] = { | |
1025 | .start = TWI1_REGBASE, | |
1026 | .end = TWI1_REGBASE + 0xFF, | |
1027 | .flags = IORESOURCE_MEM, | |
1028 | }, | |
1029 | [1] = { | |
1030 | .start = IRQ_TWI1, | |
1031 | .end = IRQ_TWI1, | |
1032 | .flags = IORESOURCE_IRQ, | |
1033 | }, | |
1034 | }; | |
1035 | ||
1036 | static struct platform_device i2c_bfin_twi1_device = { | |
1037 | .name = "i2c-bfin-twi", | |
1038 | .id = 1, | |
1039 | .num_resources = ARRAY_SIZE(bfin_twi1_resource), | |
1040 | .resource = bfin_twi1_resource, | |
1041 | }; | |
1042 | #endif | |
1043 | #endif | |
1044 | ||
1045 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | |
1046 | #include <linux/gpio_keys.h> | |
1047 | ||
1048 | static struct gpio_keys_button bfin_gpio_keys_table[] = { | |
1049 | {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"}, | |
1050 | }; | |
1051 | ||
1052 | static struct gpio_keys_platform_data bfin_gpio_keys_data = { | |
1053 | .buttons = bfin_gpio_keys_table, | |
1054 | .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), | |
1055 | }; | |
1056 | ||
1057 | static struct platform_device bfin_device_gpiokeys = { | |
1058 | .name = "gpio-keys", | |
1059 | .dev = { | |
1060 | .platform_data = &bfin_gpio_keys_data, | |
1061 | }, | |
1062 | }; | |
1063 | #endif | |
1064 | ||
14b03204 MH |
1065 | static const unsigned int cclk_vlev_datasheet[] = |
1066 | { | |
1067 | /* | |
1068 | * Internal VLEV BF54XSBBC1533 | |
1069 | ****temporarily using these values until data sheet is updated | |
1070 | */ | |
1071 | VRPAIR(VLEV_085, 150000000), | |
1072 | VRPAIR(VLEV_090, 250000000), | |
1073 | VRPAIR(VLEV_110, 276000000), | |
1074 | VRPAIR(VLEV_115, 301000000), | |
1075 | VRPAIR(VLEV_120, 525000000), | |
1076 | VRPAIR(VLEV_125, 550000000), | |
1077 | VRPAIR(VLEV_130, 600000000), | |
1078 | }; | |
1079 | ||
1080 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | |
1081 | .tuple_tab = cclk_vlev_datasheet, | |
1082 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | |
1083 | .vr_settling_time = 25 /* us */, | |
1084 | }; | |
1085 | ||
1086 | static struct platform_device bfin_dpmc = { | |
1087 | .name = "bfin dpmc", | |
1088 | .dev = { | |
1089 | .platform_data = &bfin_dmpc_vreg_data, | |
1090 | }, | |
1091 | }; | |
1092 | ||
db68254f | 1093 | static struct platform_device *cm_bf548_devices[] __initdata = { |
14b03204 MH |
1094 | |
1095 | &bfin_dpmc, | |
1096 | ||
db68254f MH |
1097 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
1098 | &rtc_device, | |
1099 | #endif | |
1100 | ||
1101 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
6bd1fbea SZ |
1102 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
1103 | &bfin_uart0_device, | |
1104 | #endif | |
1105 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
1106 | &bfin_uart1_device, | |
1107 | #endif | |
1108 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
1109 | &bfin_uart2_device, | |
1110 | #endif | |
1111 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
1112 | &bfin_uart3_device, | |
1113 | #endif | |
db68254f MH |
1114 | #endif |
1115 | ||
5be36d22 | 1116 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
42bd8bcb GY |
1117 | #ifdef CONFIG_BFIN_SIR0 |
1118 | &bfin_sir0_device, | |
1119 | #endif | |
1120 | #ifdef CONFIG_BFIN_SIR1 | |
1121 | &bfin_sir1_device, | |
1122 | #endif | |
1123 | #ifdef CONFIG_BFIN_SIR2 | |
1124 | &bfin_sir2_device, | |
1125 | #endif | |
1126 | #ifdef CONFIG_BFIN_SIR3 | |
1127 | &bfin_sir3_device, | |
1128 | #endif | |
5be36d22 GY |
1129 | #endif |
1130 | ||
db68254f MH |
1131 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) |
1132 | &bf54x_lq043_device, | |
1133 | #endif | |
1134 | ||
1135 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | |
1136 | &smsc911x_device, | |
1137 | #endif | |
1138 | ||
1139 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) | |
1140 | &musb_device, | |
1141 | #endif | |
1142 | ||
df5de261 SZ |
1143 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
1144 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART | |
1145 | &bfin_sport0_uart_device, | |
1146 | #endif | |
1147 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART | |
1148 | &bfin_sport1_uart_device, | |
1149 | #endif | |
1150 | #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART | |
1151 | &bfin_sport2_uart_device, | |
1152 | #endif | |
1153 | #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART | |
1154 | &bfin_sport3_uart_device, | |
1155 | #endif | |
1156 | #endif | |
1157 | ||
db68254f MH |
1158 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) |
1159 | &bfin_atapi_device, | |
1160 | #endif | |
1161 | ||
1162 | #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) | |
1163 | &bf5xx_nand_device, | |
1164 | #endif | |
1165 | ||
1166 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) | |
1167 | &bf54x_sdh_device, | |
1168 | #endif | |
1169 | ||
1170 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
1171 | &bf54x_spi_master0, | |
1172 | &bf54x_spi_master1, | |
1173 | #endif | |
1174 | ||
1175 | #if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE) | |
1176 | &bf54x_kpad_device, | |
1177 | #endif | |
1178 | ||
1179 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | |
10a88a2b | 1180 | &i2c_bfin_twi0_device, |
db68254f MH |
1181 | #if !defined(CONFIG_BF542) |
1182 | &i2c_bfin_twi1_device, | |
1183 | #endif | |
1184 | #endif | |
1185 | ||
1186 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | |
1187 | &bfin_device_gpiokeys, | |
1188 | #endif | |
2de73e71 MF |
1189 | |
1190 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | |
1191 | ¶_flash_device, | |
1192 | #endif | |
bf80caf4 MH |
1193 | |
1194 | #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) | |
1195 | &bfin_can_device, | |
1196 | #endif | |
1197 | ||
db68254f MH |
1198 | }; |
1199 | ||
1200 | static int __init cm_bf548_init(void) | |
1201 | { | |
f086f234 | 1202 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
db68254f MH |
1203 | platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices)); |
1204 | ||
1205 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
1206 | spi_register_board_info(bf54x_spi_board_info, | |
1207 | ARRAY_SIZE(bf54x_spi_board_info)); | |
1208 | #endif | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | arch_initcall(cm_bf548_init); | |
c13ce9fd SZ |
1214 | |
1215 | static struct platform_device *cm_bf548_early_devices[] __initdata = { | |
1216 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) | |
1217 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
1218 | &bfin_uart0_device, | |
1219 | #endif | |
1220 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
1221 | &bfin_uart1_device, | |
1222 | #endif | |
1223 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
1224 | &bfin_uart2_device, | |
1225 | #endif | |
1226 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
1227 | &bfin_uart3_device, | |
1228 | #endif | |
1229 | #endif | |
1230 | ||
1231 | #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) | |
1232 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART | |
1233 | &bfin_sport0_uart_device, | |
1234 | #endif | |
1235 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART | |
1236 | &bfin_sport1_uart_device, | |
1237 | #endif | |
1238 | #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART | |
1239 | &bfin_sport2_uart_device, | |
1240 | #endif | |
1241 | #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART | |
1242 | &bfin_sport3_uart_device, | |
1243 | #endif | |
1244 | #endif | |
1245 | }; | |
1246 | ||
1247 | void __init native_machine_early_platform_add_devices(void) | |
1248 | { | |
1249 | printk(KERN_INFO "register early platform devices\n"); | |
1250 | early_platform_add_devices(cm_bf548_early_devices, | |
1251 | ARRAY_SIZE(cm_bf548_early_devices)); | |
1252 | } |