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Blackfin: move on-chip UART resources to boards files
[net-next-2.6.git] / arch / blackfin / mach-bf538 / boards / ezkit.c
CommitLineData
dc26aec2 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
dc26aec2 5 *
96f1050d 6 * Licensed under the GPL-2
dc26aec2
MH		 7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
f1cb6462 12#include <linux/mtd/physmap.h>
dc26aec2
MH		 13#include <linux/mtd/partitions.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/irq.h>
17#include <linux/interrupt.h>
18#include <asm/bfin5xx_spi.h>
19#include <asm/dma.h>
20#include <asm/gpio.h>
21#include <asm/nand.h>
22#include <asm/portmux.h>
23#include <asm/dpmc.h>
24#include <linux/input.h>
25
26/*
27 * Name the Board for the /proc/cpuinfo
28 */
fe85cad2 29const char bfin_board_name[] = "ADI BF538-EZKIT";
dc26aec2
MH		 30
31/*
32 * Driver needs to know address, irq and flag pin.
33 */
34
35
36#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
37static struct platform_device rtc_device = {
38 .name = "rtc-bfin",
39 .id = -1,
40};
41#endif
42
43#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
dc26aec2 44#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 45static struct resource bfin_uart0_resources[] = {
dc26aec2 46 {
6bd1fbea
SZ		 47 .start = UART0_THR,
48 .end = UART0_GCTL+2,
dc26aec2
MH		 49 .flags = IORESOURCE_MEM,
50 },
6bd1fbea
SZ		 51 {
52 .start = IRQ_UART0_RX,
53 .end = IRQ_UART0_RX+1,
54 .flags = IORESOURCE_IRQ,
55 },
56 {
57 .start = IRQ_UART0_ERROR,
58 .end = IRQ_UART0_ERROR,
59 .flags = IORESOURCE_IRQ,
60 },
61 {
62 .start = CH_UART0_TX,
63 .end = CH_UART0_TX,
64 .flags = IORESOURCE_DMA,
65 },
66 {
67 .start = CH_UART0_RX,
68 .end = CH_UART0_RX,
69 .flags = IORESOURCE_DMA,
70 },
71#ifdef CONFIG_BFIN_UART0_CTSRTS
72 { /* CTS pin */
73 .start = GPIO_PG7,
74 .end = GPIO_PG7,
75 .flags = IORESOURCE_IO,
76 },
77 { /* RTS pin */
78 .start = GPIO_PG6,
79 .end = GPIO_PG6,
80 .flags = IORESOURCE_IO,
81 },
82#endif
83};
84
85unsigned short bfin_uart0_peripherals[] = {
86 P_UART0_TX, P_UART0_RX, 0
87};
88
89static struct platform_device bfin_uart0_device = {
90 .name = "bfin-uart",
91 .id = 0,
92 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
93 .resource = bfin_uart0_resources,
94 .dev = {
95 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
96 },
97};
dc26aec2
MH		 98#endif
99#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 100static struct resource bfin_uart1_resources[] = {
dc26aec2 101 {
6bd1fbea
SZ		 102 .start = UART1_THR,
103 .end = UART1_GCTL+2,
dc26aec2
MH		 104 .flags = IORESOURCE_MEM,
105 },
6bd1fbea
SZ		 106 {
107 .start = IRQ_UART1_RX,
108 .end = IRQ_UART1_RX+1,
109 .flags = IORESOURCE_IRQ,
110 },
111 {
112 .start = IRQ_UART1_ERROR,
113 .end = IRQ_UART1_ERROR,
114 .flags = IORESOURCE_IRQ,
115 },
116 {
117 .start = CH_UART1_TX,
118 .end = CH_UART1_TX,
119 .flags = IORESOURCE_DMA,
120 },
121 {
122 .start = CH_UART1_RX,
123 .end = CH_UART1_RX,
124 .flags = IORESOURCE_DMA,
125 },
126};
127
128unsigned short bfin_uart1_peripherals[] = {
129 P_UART1_TX, P_UART1_RX, 0
130};
131
132static struct platform_device bfin_uart1_device = {
133 .name = "bfin-uart",
134 .id = 1,
135 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
136 .resource = bfin_uart1_resources,
137 .dev = {
138 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
139 },
140};
dc26aec2
MH		 141#endif
142#ifdef CONFIG_SERIAL_BFIN_UART2
6bd1fbea 143static struct resource bfin_uart2_resources[] = {
dc26aec2 144 {
6bd1fbea
SZ		 145 .start = UART2_THR,
146 .end = UART2_GCTL+2,
dc26aec2
MH		 147 .flags = IORESOURCE_MEM,
148 },
6bd1fbea
SZ		 149 {
150 .start = IRQ_UART2_RX,
151 .end = IRQ_UART2_RX+1,
152 .flags = IORESOURCE_IRQ,
153 },
154 {
155 .start = IRQ_UART2_ERROR,
156 .end = IRQ_UART2_ERROR,
157 .flags = IORESOURCE_IRQ,
158 },
159 {
160 .start = CH_UART2_TX,
161 .end = CH_UART2_TX,
162 .flags = IORESOURCE_DMA,
163 },
164 {
165 .start = CH_UART2_RX,
166 .end = CH_UART2_RX,
167 .flags = IORESOURCE_DMA,
168 },
dc26aec2
MH		 169};
170
6bd1fbea
SZ		 171unsigned short bfin_uart2_peripherals[] = {
172 P_UART2_TX, P_UART2_RX, 0
173};
174
175static struct platform_device bfin_uart2_device = {
dc26aec2 176 .name = "bfin-uart",
6bd1fbea
SZ		 177 .id = 2,
178 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
179 .resource = bfin_uart2_resources,
180 .dev = {
181 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
182 },
dc26aec2
MH		 183};
184#endif
6bd1fbea 185#endif
dc26aec2
MH		 186
187#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
dc26aec2 188#ifdef CONFIG_BFIN_SIR0
42bd8bcb 189static struct resource bfin_sir0_resources[] = {
dc26aec2
MH		 190 {
191 .start = 0xFFC00400,
192 .end = 0xFFC004FF,
193 .flags = IORESOURCE_MEM,
194 },
42bd8bcb
GY		 195 {
196 .start = IRQ_UART0_RX,
197 .end = IRQ_UART0_RX+1,
198 .flags = IORESOURCE_IRQ,
199 },
200 {
201 .start = CH_UART0_RX,
202 .end = CH_UART0_RX+1,
203 .flags = IORESOURCE_DMA,
204 },
205};
206static struct platform_device bfin_sir0_device = {
207 .name = "bfin_sir",
208 .id = 0,
209 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
210 .resource = bfin_sir0_resources,
211};
dc26aec2
MH		 212#endif
213#ifdef CONFIG_BFIN_SIR1
42bd8bcb 214static struct resource bfin_sir1_resources[] = {
dc26aec2
MH		 215 {
216 .start = 0xFFC02000,
217 .end = 0xFFC020FF,
218 .flags = IORESOURCE_MEM,
219 },
42bd8bcb
GY		 220 {
221 .start = IRQ_UART1_RX,
222 .end = IRQ_UART1_RX+1,
223 .flags = IORESOURCE_IRQ,
224 },
225 {
226 .start = CH_UART1_RX,
227 .end = CH_UART1_RX+1,
228 .flags = IORESOURCE_DMA,
229 },
230};
231static struct platform_device bfin_sir1_device = {
232 .name = "bfin_sir",
233 .id = 1,
234 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
235 .resource = bfin_sir1_resources,
236};
dc26aec2
MH		 237#endif
238#ifdef CONFIG_BFIN_SIR2
42bd8bcb 239static struct resource bfin_sir2_resources[] = {
dc26aec2
MH		 240 {
241 .start = 0xFFC02100,
242 .end = 0xFFC021FF,
243 .flags = IORESOURCE_MEM,
244 },
42bd8bcb
GY		 245 {
246 .start = IRQ_UART2_RX,
247 .end = IRQ_UART2_RX+1,
248 .flags = IORESOURCE_IRQ,
249 },
250 {
251 .start = CH_UART2_RX,
252 .end = CH_UART2_RX+1,
253 .flags = IORESOURCE_DMA,
254 },
dc26aec2 255};
42bd8bcb 256static struct platform_device bfin_sir2_device = {
dc26aec2 257 .name = "bfin_sir",
42bd8bcb
GY		 258 .id = 2,
259 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
260 .resource = bfin_sir2_resources,
dc26aec2
MH		 261};
262#endif
42bd8bcb 263#endif
dc26aec2 264
706a01b1
BS		 265#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
266unsigned short bfin_can_peripherals[] = {
267 P_CAN0_RX, P_CAN0_TX, 0
268};
269
270static struct resource bfin_can_resources[] = {
271 {
272 .start = 0xFFC02A00,
273 .end = 0xFFC02FFF,
274 .flags = IORESOURCE_MEM,
275 },
276 {
277 .start = IRQ_CAN_RX,
278 .end = IRQ_CAN_RX,
279 .flags = IORESOURCE_IRQ,
280 },
281 {
282 .start = IRQ_CAN_TX,
283 .end = IRQ_CAN_TX,
284 .flags = IORESOURCE_IRQ,
285 },
286 {
287 .start = IRQ_CAN_ERROR,
288 .end = IRQ_CAN_ERROR,
289 .flags = IORESOURCE_IRQ,
290 },
291};
292
293static struct platform_device bfin_can_device = {
294 .name = "bfin_can",
295 .num_resources = ARRAY_SIZE(bfin_can_resources),
296 .resource = bfin_can_resources,
297 .dev = {
298 .platform_data = &bfin_can_peripherals, /* Passed to driver */
299 },
300};
301#endif
302
dc26aec2
MH		 303/*
304 * USB-LAN EzExtender board
305 * Driver needs to know address, irq and flag pin.
306 */
307#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 308#include <linux/smc91x.h>
309
310static struct smc91x_platdata smc91x_info = {
311 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
312 .leda = RPC_LED_100_10,
313 .ledb = RPC_LED_TX_RX,
314};
315
dc26aec2
MH		 316static struct resource smc91x_resources[] = {
317 {
318 .name = "smc91x-regs",
319 .start = 0x20310300,
320 .end = 0x20310300 + 16,
321 .flags = IORESOURCE_MEM,
322 }, {
323 .start = IRQ_PF0,
324 .end = IRQ_PF0,
325 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
326 },
327};
328static struct platform_device smc91x_device = {
329 .name = "smc91x",
330 .id = 0,
331 .num_resources = ARRAY_SIZE(smc91x_resources),
332 .resource = smc91x_resources,
61f09b5a
MH		 333 .dev = {
334 .platform_data = &smc91x_info,
335 },
dc26aec2
MH		 336};
337#endif
338
339#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
340/* all SPI peripherals info goes here */
341#if defined(CONFIG_MTD_M25P80) \
342 || defined(CONFIG_MTD_M25P80_MODULE)
343/* SPI flash chip (m25p16) */
344static struct mtd_partition bfin_spi_flash_partitions[] = {
345 {
346 .name = "bootloader(spi)",
347 .size = 0x00040000,
348 .offset = 0,
349 .mask_flags = MTD_CAP_ROM
350 }, {
351 .name = "linux kernel(spi)",
352 .size = 0x1c0000,
353 .offset = 0x40000
354 }
355};
356
357static struct flash_platform_data bfin_spi_flash_data = {
358 .name = "m25p80",
359 .parts = bfin_spi_flash_partitions,
360 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
361 .type = "m25p16",
362};
363
364static struct bfin5xx_spi_chip spi_flash_chip_info = {
365 .enable_dma = 0, /* use dma transfer with this chip*/
366 .bits_per_word = 8,
dc26aec2
MH		 367};
368#endif
369
370#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
371#include <linux/spi/ad7879.h>
372static const struct ad7879_platform_data bfin_ad7879_ts_info = {
373 .model = 7879, /* Model = AD7879 */
374 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
375 .pressure_max = 10000,
376 .pressure_min = 0,
377 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
378 .acquisition_time = 1, /* 4us acquisition time per sample */
379 .median = 2, /* do 8 measurements */
380 .averaging = 1, /* take the average of 4 middle samples */
381 .pen_down_acc_interval = 255, /* 9.4 ms */
382 .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
383 .gpio_default = 1, /* During initialization set GPIO = HIGH */
384};
385#endif
386
387#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
388static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
389 .enable_dma = 0,
390 .bits_per_word = 16,
391};
392#endif
393
394#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
395#include <asm/bfin-lq035q1.h>
396
397static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
398 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
399 .use_bl = 0, /* let something else control the LCD Blacklight */
400 .gpio_bl = GPIO_PF7,
401};
402
403static struct resource bfin_lq035q1_resources[] = {
404 {
405 .start = IRQ_PPI_ERROR,
406 .end = IRQ_PPI_ERROR,
407 .flags = IORESOURCE_IRQ,
408 },
409};
410
411static struct platform_device bfin_lq035q1_device = {
412 .name = "bfin-lq035q1",
413 .id = -1,
414 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
415 .resource = bfin_lq035q1_resources,
416 .dev = {
417 .platform_data = &bfin_lq035q1_data,
418 },
419};
420#endif
421
422#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
423static struct bfin5xx_spi_chip spidev_chip_info = {
424 .enable_dma = 0,
425 .bits_per_word = 8,
426};
427#endif
428
429#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
430static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
431 .enable_dma = 0,
432 .bits_per_word = 8,
433};
434#endif
435
436static struct spi_board_info bf538_spi_board_info[] __initdata = {
437#if defined(CONFIG_MTD_M25P80) \
438 || defined(CONFIG_MTD_M25P80_MODULE)
439 {
440 /* the modalias must be the same as spi device driver name */
441 .modalias = "m25p80", /* Name of spi_driver for this device */
442 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
443 .bus_num = 0, /* Framework bus number */
444 .chip_select = 1, /* SPI_SSEL1*/
445 .platform_data = &bfin_spi_flash_data,
446 .controller_data = &spi_flash_chip_info,
447 .mode = SPI_MODE_3,
448 },
449#endif
450#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
451 {
452 .modalias = "ad7879",
453 .platform_data = &bfin_ad7879_ts_info,
454 .irq = IRQ_PF3,
455 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
456 .bus_num = 0,
457 .chip_select = 1,
458 .controller_data = &spi_ad7879_chip_info,
459 .mode = SPI_CPHA | SPI_CPOL,
460 },
461#endif
462#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
463 {
464 .modalias = "bfin-lq035q1-spi",
465 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
466 .bus_num = 0,
467 .chip_select = 2,
468 .controller_data = &lq035q1_spi_chip_info,
469 .mode = SPI_CPHA | SPI_CPOL,
470 },
471#endif
472#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
473 {
474 .modalias = "spidev",
475 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
476 .bus_num = 0,
477 .chip_select = 1,
478 .controller_data = &spidev_chip_info,
479 },
480#endif
481};
482
483/* SPI (0) */
484static struct resource bfin_spi0_resource[] = {
485 [0] = {
486 .start = SPI0_REGBASE,
487 .end = SPI0_REGBASE + 0xFF,
488 .flags = IORESOURCE_MEM,
489 },
490 [1] = {
491 .start = CH_SPI0,
492 .end = CH_SPI0,
53122693
YL		 493 .flags = IORESOURCE_DMA,
494 },
495 [2] = {
496 .start = IRQ_SPI0,
497 .end = IRQ_SPI0,
dc26aec2
MH		 498 .flags = IORESOURCE_IRQ,
499 }
500};
501
502/* SPI (1) */
503static struct resource bfin_spi1_resource[] = {
504 [0] = {
505 .start = SPI1_REGBASE,
506 .end = SPI1_REGBASE + 0xFF,
507 .flags = IORESOURCE_MEM,
508 },
509 [1] = {
510 .start = CH_SPI1,
511 .end = CH_SPI1,
53122693
YL		 512 .flags = IORESOURCE_DMA,
513 },
514 [2] = {
515 .start = IRQ_SPI1,
516 .end = IRQ_SPI1,
dc26aec2
MH		 517 .flags = IORESOURCE_IRQ,
518 }
519};
520
521/* SPI (2) */
522static struct resource bfin_spi2_resource[] = {
523 [0] = {
524 .start = SPI2_REGBASE,
525 .end = SPI2_REGBASE + 0xFF,
526 .flags = IORESOURCE_MEM,
527 },
528 [1] = {
529 .start = CH_SPI2,
530 .end = CH_SPI2,
769cfc0d
BS		 531 .flags = IORESOURCE_DMA,
532 },
533 [2] = {
534 .start = IRQ_SPI2,
535 .end = IRQ_SPI2,
dc26aec2
MH		 536 .flags = IORESOURCE_IRQ,
537 }
538};
539
540/* SPI controller data */
541static struct bfin5xx_spi_master bf538_spi_master_info0 = {
542 .num_chipselect = 8,
543 .enable_dma = 1, /* master has the ability to do dma transfer */
544 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
545};
546
547static struct platform_device bf538_spi_master0 = {
548 .name = "bfin-spi",
549 .id = 0, /* Bus number */
550 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
551 .resource = bfin_spi0_resource,
552 .dev = {
553 .platform_data = &bf538_spi_master_info0, /* Passed to driver */
554 },
555};
556
557static struct bfin5xx_spi_master bf538_spi_master_info1 = {
558 .num_chipselect = 8,
559 .enable_dma = 1, /* master has the ability to do dma transfer */
560 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
561};
562
563static struct platform_device bf538_spi_master1 = {
564 .name = "bfin-spi",
565 .id = 1, /* Bus number */
566 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
567 .resource = bfin_spi1_resource,
568 .dev = {
569 .platform_data = &bf538_spi_master_info1, /* Passed to driver */
570 },
571};
572
573static struct bfin5xx_spi_master bf538_spi_master_info2 = {
574 .num_chipselect = 8,
575 .enable_dma = 1, /* master has the ability to do dma transfer */
576 .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
577};
578
579static struct platform_device bf538_spi_master2 = {
580 .name = "bfin-spi",
581 .id = 2, /* Bus number */
582 .num_resources = ARRAY_SIZE(bfin_spi2_resource),
583 .resource = bfin_spi2_resource,
584 .dev = {
585 .platform_data = &bf538_spi_master_info2, /* Passed to driver */
586 },
587};
588
589#endif /* spi master and devices */
590
591#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
592static struct resource bfin_twi0_resource[] = {
593 [0] = {
594 .start = TWI0_REGBASE,
595 .end = TWI0_REGBASE + 0xFF,
596 .flags = IORESOURCE_MEM,
597 },
598 [1] = {
599 .start = IRQ_TWI0,
600 .end = IRQ_TWI0,
601 .flags = IORESOURCE_IRQ,
602 },
603};
604
605static struct platform_device i2c_bfin_twi0_device = {
606 .name = "i2c-bfin-twi",
607 .id = 0,
608 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
609 .resource = bfin_twi0_resource,
610};
611
612#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
613static struct resource bfin_twi1_resource[] = {
614 [0] = {
615 .start = TWI1_REGBASE,
616 .end = TWI1_REGBASE + 0xFF,
617 .flags = IORESOURCE_MEM,
618 },
619 [1] = {
620 .start = IRQ_TWI1,
621 .end = IRQ_TWI1,
622 .flags = IORESOURCE_IRQ,
623 },
624};
625
626static struct platform_device i2c_bfin_twi1_device = {
627 .name = "i2c-bfin-twi",
628 .id = 1,
629 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
630 .resource = bfin_twi1_resource,
631};
632#endif
633#endif
634
635#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
636#include <linux/gpio_keys.h>
637
638static struct gpio_keys_button bfin_gpio_keys_table[] = {
639 {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
640};
641
642static struct gpio_keys_platform_data bfin_gpio_keys_data = {
643 .buttons = bfin_gpio_keys_table,
644 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
645};
646
647static struct platform_device bfin_device_gpiokeys = {
648 .name = "gpio-keys",
649 .dev = {
650 .platform_data = &bfin_gpio_keys_data,
651 },
652};
653#endif
654
655static const unsigned int cclk_vlev_datasheet[] =
656{
657/*
658 * Internal VLEV BF538SBBC1533
659 ****temporarily using these values until data sheet is updated
660 */
661 VRPAIR(VLEV_100, 150000000),
662 VRPAIR(VLEV_100, 250000000),
663 VRPAIR(VLEV_110, 276000000),
664 VRPAIR(VLEV_115, 301000000),
665 VRPAIR(VLEV_120, 525000000),
666 VRPAIR(VLEV_125, 550000000),
667 VRPAIR(VLEV_130, 600000000),
668};
669
670static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
671 .tuple_tab = cclk_vlev_datasheet,
672 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
673 .vr_settling_time = 25 /* us */,
674};
675
676static struct platform_device bfin_dpmc = {
677 .name = "bfin dpmc",
678 .dev = {
679 .platform_data = &bfin_dmpc_vreg_data,
680 },
681};
682
f1cb6462
BS		 683#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
684static struct mtd_partition ezkit_partitions[] = {
685 {
686 .name = "bootloader(nor)",
687 .size = 0x40000,
688 .offset = 0,
689 }, {
690 .name = "linux kernel(nor)",
691 .size = 0x180000,
692 .offset = MTDPART_OFS_APPEND,
693 }, {
694 .name = "file system(nor)",
695 .size = MTDPART_SIZ_FULL,
696 .offset = MTDPART_OFS_APPEND,
697 }
698};
699
700static struct physmap_flash_data ezkit_flash_data = {
701 .width = 2,
702 .parts = ezkit_partitions,
703 .nr_parts = ARRAY_SIZE(ezkit_partitions),
704};
705
706static struct resource ezkit_flash_resource = {
707 .start = 0x20000000,
708#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
709 .end = 0x202fffff,
710#else
711 .end = 0x203fffff,
712#endif
713 .flags = IORESOURCE_MEM,
714};
715
716static struct platform_device ezkit_flash_device = {
717 .name = "physmap-flash",
718 .id = 0,
719 .dev = {
720 .platform_data = &ezkit_flash_data,
721 },
722 .num_resources = 1,
723 .resource = &ezkit_flash_resource,
724};
725#endif
726
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MH		 727static struct platform_device *cm_bf538_devices[] __initdata = {
728
729 &bfin_dpmc,
730
731#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
732 &rtc_device,
733#endif
734
735#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 736#ifdef CONFIG_SERIAL_BFIN_UART0
737 &bfin_uart0_device,
738#endif
739#ifdef CONFIG_SERIAL_BFIN_UART1
740 &bfin_uart1_device,
741#endif
742#ifdef CONFIG_SERIAL_BFIN_UART2
743 &bfin_uart2_device,
744#endif
dc26aec2
MH		 745#endif
746
747#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
748 &bf538_spi_master0,
749 &bf538_spi_master1,
750 &bf538_spi_master2,
751#endif
752
753#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
754 &i2c_bfin_twi0_device,
755 &i2c_bfin_twi1_device,
756#endif
757
758#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 759#ifdef CONFIG_BFIN_SIR0
760 &bfin_sir0_device,
761#endif
762#ifdef CONFIG_BFIN_SIR1
763 &bfin_sir1_device,
764#endif
765#ifdef CONFIG_BFIN_SIR2
766 &bfin_sir2_device,
767#endif
dc26aec2
MH		 768#endif
769
706a01b1
BS		 770#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
771 &bfin_can_device,
772#endif
773
dc26aec2
MH		 774#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
775 &smc91x_device,
776#endif
777
778#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
779 &bfin_lq035q1_device,
780#endif
781
782#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
783 &bfin_device_gpiokeys,
784#endif
c97618d3 785
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BS		 786#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
787 &ezkit_flash_device,
788#endif
dc26aec2
MH		 789};
790
791static int __init ezkit_init(void)
792{
793 printk(KERN_INFO "%s(): registering device resources\n", __func__);
794 platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
795
796#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
797 spi_register_board_info(bf538_spi_board_info,
798 ARRAY_SIZE(bf538_spi_board_info));
799#endif
800
801 return 0;
802}
803
804arch_initcall(ezkit_init);
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