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Blackfin: bf537-stamp: move ADF7021 MAC storage into platform resources
[net-next-2.6.git] / arch / blackfin / mach-bf537 / boards / stamp.c
CommitLineData
1394f032 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
1394f032 5 *
96f1050d 6 * Licensed under the GPL-2 or later.
1394f032
BW		 7 */
8
9#include <linux/device.h>
fc68911e 10#include <linux/kernel.h>
1394f032 11#include <linux/platform_device.h>
6e364755 12#include <linux/io.h>
1394f032 13#include <linux/mtd/mtd.h>
fc68911e 14#include <linux/mtd/nand.h>
1394f032 15#include <linux/mtd/partitions.h>
fc68911e 16#include <linux/mtd/plat-ram.h>
de8c43f2 17#include <linux/mtd/physmap.h>
1394f032
BW		 18#include <linux/spi/spi.h>
19#include <linux/spi/flash.h>
20#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 21#include <linux/usb/isp1362.h>
1394f032 22#endif
7a9cc489
SZ		 23#include <linux/i2c.h>
24#include <linux/i2c/adp5588.h>
0531c467 25#include <linux/etherdevice.h>
0a87e3e9 26#include <linux/ata_platform.h>
1394f032
BW		 27#include <linux/irq.h>
28#include <linux/interrupt.h>
27f5d75a 29#include <linux/usb/sl811.h>
f79ea4cb 30#include <linux/spi/mmc_spi.h>
78756c62
MH		 31#include <linux/leds.h>
32#include <linux/input.h>
c6c4d7bb 33#include <asm/dma.h>
1f83b8f1 34#include <asm/bfin5xx_spi.h>
c6c4d7bb 35#include <asm/reboot.h>
5d448dd5 36#include <asm/portmux.h>
14b03204 37#include <asm/dpmc.h>
1394f032
BW		 38
39/*
40 * Name the Board for the /proc/cpuinfo
41 */
fe85cad2 42const char bfin_board_name[] = "ADI BF537-STAMP";
1394f032
BW		 43
44/*
45 * Driver needs to know address, irq and flag pin.
46 */
47
1394f032 48#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 49#include <linux/usb/isp1760.h>
50static struct resource bfin_isp1760_resources[] = {
1394f032 51 [0] = {
3f375690
MH		 52 .start = 0x203C0000,
53 .end = 0x203C0000 + 0x000fffff,
1394f032
BW		 54 .flags = IORESOURCE_MEM,
55 },
56 [1] = {
3f375690
MH		 57 .start = IRQ_PF7,
58 .end = IRQ_PF7,
6a6be3d1 59 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1394f032
BW		 60 },
61};
62
3f375690
MH		 63static struct isp1760_platform_data isp1760_priv = {
64 .is_isp1761 = 0,
3f375690
MH		 65 .bus_width_16 = 1,
66 .port1_otg = 0,
67 .analog_oc = 0,
68 .dack_polarity_high = 0,
69 .dreq_polarity_high = 0,
1394f032
BW		 70};
71
3f375690 72static struct platform_device bfin_isp1760_device = {
c6feb768 73 .name = "isp1760",
3f375690
MH		 74 .id = 0,
75 .dev = {
76 .platform_data = &isp1760_priv,
77 },
78 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
79 .resource = bfin_isp1760_resources,
1394f032 80};
1394f032
BW		 81#endif
82
2463ef22 83#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
2463ef22
MH		 84#include <linux/gpio_keys.h>
85
86static struct gpio_keys_button bfin_gpio_keys_table[] = {
87 {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
88 {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
89 {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
90 {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
91};
92
93static struct gpio_keys_platform_data bfin_gpio_keys_data = {
94 .buttons = bfin_gpio_keys_table,
95 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
96};
97
98static struct platform_device bfin_device_gpiokeys = {
99 .name = "gpio-keys",
100 .dev = {
101 .platform_data = &bfin_gpio_keys_data,
102 },
103};
104#endif
105
1394f032
BW		 106#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
107static struct resource bfin_pcmcia_cf_resources[] = {
108 {
109 .start = 0x20310000, /* IO PORT */
110 .end = 0x20312000,
111 .flags = IORESOURCE_MEM,
1f83b8f1 112 }, {
d2d50aa9 113 .start = 0x20311000, /* Attribute Memory */
1394f032
BW		 114 .end = 0x20311FFF,
115 .flags = IORESOURCE_MEM,
1f83b8f1 116 }, {
1394f032
BW		 117 .start = IRQ_PF4,
118 .end = IRQ_PF4,
119 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1f83b8f1 120 }, {
1394f032
BW		 121 .start = 6, /* Card Detect PF6 */
122 .end = 6,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127static struct platform_device bfin_pcmcia_cf_device = {
128 .name = "bfin_cf_pcmcia",
129 .id = -1,
130 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
131 .resource = bfin_pcmcia_cf_resources,
132};
133#endif
134
135#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
136static struct platform_device rtc_device = {
137 .name = "rtc-bfin",
138 .id = -1,
139};
140#endif
141
142#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 143#include <linux/smc91x.h>
144
145static struct smc91x_platdata smc91x_info = {
146 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
147 .leda = RPC_LED_100_10,
148 .ledb = RPC_LED_TX_RX,
149};
150
1394f032
BW		 151static struct resource smc91x_resources[] = {
152 {
153 .name = "smc91x-regs",
154 .start = 0x20300300,
155 .end = 0x20300300 + 16,
156 .flags = IORESOURCE_MEM,
1f83b8f1 157 }, {
1394f032
BW		 158
159 .start = IRQ_PF7,
160 .end = IRQ_PF7,
161 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
162 },
163};
164static struct platform_device smc91x_device = {
165 .name = "smc91x",
166 .id = 0,
167 .num_resources = ARRAY_SIZE(smc91x_resources),
168 .resource = smc91x_resources,
61f09b5a
MH		 169 .dev = {
170 .platform_data = &smc91x_info,
171 },
1394f032
BW		 172};
173#endif
174
f40d24d9
AL		 175#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
176static struct resource dm9000_resources[] = {
177 [0] = {
178 .start = 0x203FB800,
b3dec4a4 179 .end = 0x203FB800 + 1,
f40d24d9
AL		 180 .flags = IORESOURCE_MEM,
181 },
182 [1] = {
b3dec4a4
BS		 183 .start = 0x203FB804,
184 .end = 0x203FB804 + 1,
185 .flags = IORESOURCE_MEM,
186 },
187 [2] = {
f40d24d9
AL		 188 .start = IRQ_PF9,
189 .end = IRQ_PF9,
190 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
191 },
192};
193
194static struct platform_device dm9000_device = {
195 .name = "dm9000",
196 .id = -1,
197 .num_resources = ARRAY_SIZE(dm9000_resources),
198 .resource = dm9000_resources,
199};
200#endif
201
1394f032
BW		 202#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
203static struct resource sl811_hcd_resources[] = {
204 {
205 .start = 0x20340000,
206 .end = 0x20340000,
207 .flags = IORESOURCE_MEM,
1f83b8f1 208 }, {
1394f032
BW		 209 .start = 0x20340004,
210 .end = 0x20340004,
211 .flags = IORESOURCE_MEM,
1f83b8f1 212 }, {
01218654
MF		 213 .start = IRQ_PF4,
214 .end = IRQ_PF4,
1394f032
BW		 215 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
216 },
217};
218
219#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
220void sl811_port_power(struct device *dev, int is_on)
221{
c6c4d7bb 222 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
acbcd263 223 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
1394f032
BW		 224}
225#endif
226
227static struct sl811_platform_data sl811_priv = {
228 .potpg = 10,
229 .power = 250, /* == 500mA */
230#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
231 .port_power = &sl811_port_power,
232#endif
233};
234
235static struct platform_device sl811_hcd_device = {
236 .name = "sl811-hcd",
237 .id = 0,
238 .dev = {
239 .platform_data = &sl811_priv,
240 },
241 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
242 .resource = sl811_hcd_resources,
243};
244#endif
245
246#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
247static struct resource isp1362_hcd_resources[] = {
248 {
249 .start = 0x20360000,
250 .end = 0x20360000,
251 .flags = IORESOURCE_MEM,
1f83b8f1 252 }, {
1394f032
BW		 253 .start = 0x20360004,
254 .end = 0x20360004,
255 .flags = IORESOURCE_MEM,
1f83b8f1 256 }, {
21b03cfe
MF		 257 .start = IRQ_PF3,
258 .end = IRQ_PF3,
1394f032
BW		 259 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
260 },
261};
262
263static struct isp1362_platform_data isp1362_priv = {
264 .sel15Kres = 1,
265 .clknotstop = 0,
266 .oc_enable = 0,
267 .int_act_high = 0,
268 .int_edge_triggered = 0,
269 .remote_wakeup_connected = 0,
270 .no_power_switching = 1,
271 .power_switching_mode = 0,
272};
273
274static struct platform_device isp1362_hcd_device = {
275 .name = "isp1362-hcd",
276 .id = 0,
277 .dev = {
278 .platform_data = &isp1362_priv,
279 },
280 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
281 .resource = isp1362_hcd_resources,
282};
283#endif
284
706a01b1
BS		 285#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
286unsigned short bfin_can_peripherals[] = {
287 P_CAN0_RX, P_CAN0_TX, 0
288};
289
290static struct resource bfin_can_resources[] = {
291 {
292 .start = 0xFFC02A00,
293 .end = 0xFFC02FFF,
294 .flags = IORESOURCE_MEM,
295 },
296 {
297 .start = IRQ_CAN_RX,
298 .end = IRQ_CAN_RX,
299 .flags = IORESOURCE_IRQ,
300 },
301 {
302 .start = IRQ_CAN_TX,
303 .end = IRQ_CAN_TX,
304 .flags = IORESOURCE_IRQ,
305 },
306 {
307 .start = IRQ_CAN_ERROR,
308 .end = IRQ_CAN_ERROR,
309 .flags = IORESOURCE_IRQ,
310 },
311};
312
313static struct platform_device bfin_can_device = {
314 .name = "bfin_can",
315 .num_resources = ARRAY_SIZE(bfin_can_resources),
316 .resource = bfin_can_resources,
317 .dev = {
318 .platform_data = &bfin_can_peripherals, /* Passed to driver */
319 },
320};
321#endif
322
1394f032 323#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 324static struct platform_device bfin_mii_bus = {
325 .name = "bfin_mii_bus",
326};
327
1394f032
BW		 328static struct platform_device bfin_mac_device = {
329 .name = "bfin_mac",
65319628 330 .dev.platform_data = &bfin_mii_bus,
1394f032
BW		 331};
332#endif
333
334#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
335static struct resource net2272_bfin_resources[] = {
336 {
337 .start = 0x20300000,
338 .end = 0x20300000 + 0x100,
339 .flags = IORESOURCE_MEM,
1f83b8f1 340 }, {
1394f032
BW		 341 .start = IRQ_PF7,
342 .end = IRQ_PF7,
343 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
344 },
345};
346
347static struct platform_device net2272_bfin_device = {
348 .name = "net2272",
349 .id = -1,
350 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
351 .resource = net2272_bfin_resources,
352};
353#endif
354
fc68911e
MF		 355#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
356#ifdef CONFIG_MTD_PARTITIONS
357const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
358
359static struct mtd_partition bfin_plat_nand_partitions[] = {
360 {
aa582977 361 .name = "linux kernel(nand)",
fc68911e
MF		 362 .size = 0x400000,
363 .offset = 0,
364 }, {
aa582977 365 .name = "file system(nand)",
fc68911e
MF		 366 .size = MTDPART_SIZ_FULL,
367 .offset = MTDPART_OFS_APPEND,
368 },
369};
370#endif
371
372#define BFIN_NAND_PLAT_CLE 2
373#define BFIN_NAND_PLAT_ALE 1
374static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
375{
376 struct nand_chip *this = mtd->priv;
377
378 if (cmd == NAND_CMD_NONE)
379 return;
380
381 if (ctrl & NAND_CLE)
382 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
383 else
384 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
385}
386
387#define BFIN_NAND_PLAT_READY GPIO_PF3
388static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
389{
390 return gpio_get_value(BFIN_NAND_PLAT_READY);
391}
392
393static struct platform_nand_data bfin_plat_nand_data = {
394 .chip = {
395 .chip_delay = 30,
396#ifdef CONFIG_MTD_PARTITIONS
397 .part_probe_types = part_probes,
398 .partitions = bfin_plat_nand_partitions,
399 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
400#endif
401 },
402 .ctrl = {
403 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
404 .dev_ready = bfin_plat_nand_dev_ready,
405 },
406};
407
408#define MAX(x, y) (x > y ? x : y)
409static struct resource bfin_plat_nand_resources = {
410 .start = 0x20212000,
411 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
412 .flags = IORESOURCE_IO,
413};
414
415static struct platform_device bfin_async_nand_device = {
416 .name = "gen_nand",
417 .id = -1,
418 .num_resources = 1,
419 .resource = &bfin_plat_nand_resources,
420 .dev = {
421 .platform_data = &bfin_plat_nand_data,
422 },
423};
424
425static void bfin_plat_nand_init(void)
426{
427 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
428}
429#else
430static void bfin_plat_nand_init(void) {}
431#endif
432
793dc27b 433#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 434static struct mtd_partition stamp_partitions[] = {
435 {
aa582977 436 .name = "bootloader(nor)",
edf05641 437 .size = 0x40000,
de8c43f2
MF		 438 .offset = 0,
439 }, {
aa582977 440 .name = "linux kernel(nor)",
6ecb5b6d 441 .size = 0x180000,
de8c43f2
MF		 442 .offset = MTDPART_OFS_APPEND,
443 }, {
aa582977 444 .name = "file system(nor)",
6ecb5b6d 445 .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
de8c43f2
MF		 446 .offset = MTDPART_OFS_APPEND,
447 }, {
aa582977 448 .name = "MAC Address(nor)",
de8c43f2
MF		 449 .size = MTDPART_SIZ_FULL,
450 .offset = 0x3F0000,
451 .mask_flags = MTD_WRITEABLE,
452 }
453};
454
455static struct physmap_flash_data stamp_flash_data = {
456 .width = 2,
457 .parts = stamp_partitions,
458 .nr_parts = ARRAY_SIZE(stamp_partitions),
38e7673f
BS		 459#ifdef CONFIG_ROMKERNEL
460 .probe_type = "map_rom",
461#endif
de8c43f2
MF		 462};
463
464static struct resource stamp_flash_resource = {
465 .start = 0x20000000,
466 .end = 0x203fffff,
467 .flags = IORESOURCE_MEM,
468};
469
470static struct platform_device stamp_flash_device = {
471 .name = "physmap-flash",
472 .id = 0,
473 .dev = {
474 .platform_data = &stamp_flash_data,
475 },
476 .num_resources = 1,
477 .resource = &stamp_flash_resource,
478};
793dc27b 479#endif
de8c43f2 480
1394f032
BW		 481#if defined(CONFIG_MTD_M25P80) \
482 || defined(CONFIG_MTD_M25P80_MODULE)
483static struct mtd_partition bfin_spi_flash_partitions[] = {
484 {
aa582977 485 .name = "bootloader(spi)",
edf05641 486 .size = 0x00040000,
1394f032
BW		 487 .offset = 0,
488 .mask_flags = MTD_CAP_ROM
1f83b8f1 489 }, {
aa582977 490 .name = "linux kernel(spi)",
6ecb5b6d 491 .size = 0x180000,
edf05641 492 .offset = MTDPART_OFS_APPEND,
1f83b8f1 493 }, {
aa582977 494 .name = "file system(spi)",
edf05641
MF		 495 .size = MTDPART_SIZ_FULL,
496 .offset = MTDPART_OFS_APPEND,
1394f032
BW		 497 }
498};
499
500static struct flash_platform_data bfin_spi_flash_data = {
501 .name = "m25p80",
502 .parts = bfin_spi_flash_partitions,
503 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
88a8078b 504 /* .type = "m25p64", */
1394f032
BW		 505};
506
507/* SPI flash chip (m25p64) */
508static struct bfin5xx_spi_chip spi_flash_chip_info = {
509 .enable_dma = 0, /* use dma transfer with this chip*/
510 .bits_per_word = 8,
511};
512#endif
513
a261eec0
MF		 514#if defined(CONFIG_BFIN_SPI_ADC) \
515 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
1394f032
BW		 516/* SPI ADC chip */
517static struct bfin5xx_spi_chip spi_adc_chip_info = {
518 .enable_dma = 1, /* use dma transfer with this chip*/
519 .bits_per_word = 16,
520};
521#endif
522
8312440e
BS		 523#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
524 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
1394f032
BW		 525static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
526 .enable_dma = 0,
527 .bits_per_word = 16,
528};
529#endif
530
d4b834c1
BS		 531#if defined(CONFIG_SND_BF5XX_SOC_AD1938) \
532 || defined(CONFIG_SND_BF5XX_SOC_AD1938_MODULE)
533static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
534 .enable_dma = 0,
535 .bits_per_word = 8,
d4b834c1
BS		 536};
537#endif
538
5b7c5775 539#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
427f277e
BS		 540#include <linux/input/ad714x.h>
541static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
542 .enable_dma = 0,
543 .bits_per_word = 16,
544};
545
5b7c5775 546static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
427f277e
BS		 547 {
548 .start_stage = 0,
549 .end_stage = 7,
550 .max_coord = 128,
551 },
552};
553
5b7c5775 554static struct ad714x_button_plat ad7147_spi_button_plat[] = {
427f277e
BS		 555 {
556 .keycode = BTN_FORWARD,
557 .l_mask = 0,
558 .h_mask = 0x600,
559 },
560 {
561 .keycode = BTN_LEFT,
562 .l_mask = 0,
563 .h_mask = 0x500,
564 },
565 {
566 .keycode = BTN_MIDDLE,
567 .l_mask = 0,
568 .h_mask = 0x800,
569 },
570 {
571 .keycode = BTN_RIGHT,
572 .l_mask = 0x100,
573 .h_mask = 0x400,
574 },
575 {
576 .keycode = BTN_BACK,
577 .l_mask = 0x200,
578 .h_mask = 0x400,
579 },
580};
5b7c5775 581static struct ad714x_platform_data ad7147_spi_platform_data = {
427f277e
BS		 582 .slider_num = 1,
583 .button_num = 5,
5b7c5775
MF		 584 .slider = ad7147_spi_slider_plat,
585 .button = ad7147_spi_button_plat,
427f277e
BS		 586 .stage_cfg_reg = {
587 {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
588 {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
589 {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650},
590 {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650},
591 {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650},
592 {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650},
593 {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650},
594 {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600},
595 {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150},
596 {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150},
597 {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300},
598 {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150},
599 },
600 .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0},
601};
602#endif
603
5b7c5775 604#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
427f277e 605#include <linux/input/ad714x.h>
5b7c5775 606static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
427f277e
BS		 607 {
608 .keycode = BTN_1,
609 .l_mask = 0,
610 .h_mask = 0x1,
611 },
612 {
613 .keycode = BTN_2,
614 .l_mask = 0,
615 .h_mask = 0x2,
616 },
617 {
618 .keycode = BTN_3,
619 .l_mask = 0,
620 .h_mask = 0x4,
621 },
622 {
623 .keycode = BTN_4,
624 .l_mask = 0x0,
625 .h_mask = 0x8,
626 },
627};
5b7c5775 628static struct ad714x_platform_data ad7142_i2c_platform_data = {
427f277e 629 .button_num = 4,
5b7c5775 630 .button = ad7142_i2c_button_plat,
427f277e
BS		 631 .stage_cfg_reg = {
632 /* fixme: figure out right setting for all comoponent according
633 * to hardware feature of EVAL-AD7142EB board */
634 {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
635 {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
636 {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
637 {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
638 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
639 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
640 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
641 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
642 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
643 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
644 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
645 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
646 },
647 .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0},
648};
649#endif
650
f79ea4cb
YL		 651#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
652#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
653
654static int bfin_mmc_spi_init(struct device *dev,
655 irqreturn_t (*detect_int)(int, void *), void *data)
656{
657 return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
658 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
659}
660
661static void bfin_mmc_spi_exit(struct device *dev, void *data)
662{
663 free_irq(MMC_SPI_CARD_DETECT_INT, data);
664}
665
666static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
667 .init = bfin_mmc_spi_init,
668 .exit = bfin_mmc_spi_exit,
669 .detect_delay = 100, /* msecs */
670};
671
672static struct bfin5xx_spi_chip mmc_spi_chip_info = {
673 .enable_dma = 0,
674 .bits_per_word = 8,
e68d1ebc 675 .pio_interrupt = 0,
f79ea4cb
YL		 676};
677#endif
678
1394f032 679#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
46aa04f9 680#include <linux/spi/ad7877.h>
1394f032 681static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
1394f032
BW		 682 .enable_dma = 0,
683 .bits_per_word = 16,
684};
685
686static const struct ad7877_platform_data bfin_ad7877_ts_info = {
687 .model = 7877,
688 .vref_delay_usecs = 50, /* internal, no capacitor */
689 .x_plate_ohms = 419,
690 .y_plate_ohms = 486,
691 .pressure_max = 1000,
692 .pressure_min = 0,
693 .stopacq_polarity = 1,
694 .first_conversion_delay = 3,
695 .acquisition_time = 1,
696 .averaging = 1,
697 .pen_down_acc_interval = 1,
698};
699#endif
700
46aa04f9
MH		 701#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
702#include <linux/spi/ad7879.h>
46aa04f9
MH		 703static const struct ad7879_platform_data bfin_ad7879_ts_info = {
704 .model = 7879, /* Model = AD7879 */
705 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
706 .pressure_max = 10000,
707 .pressure_min = 0,
708 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
709 .acquisition_time = 1, /* 4us acquisition time per sample */
710 .median = 2, /* do 8 measurements */
711 .averaging = 1, /* take the average of 4 middle samples */
712 .pen_down_acc_interval = 255, /* 9.4 ms */
244d3423
MH		 713 .gpio_export = 1, /* Export GPIO to gpiolib */
714 .gpio_base = -1, /* Dynamic allocation */
46aa04f9
MH		 715};
716#endif
717
ffc4d8bc 718#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
57af8edf 719#include <linux/input/adxl34x.h>
ffc4d8bc
MH		 720static const struct adxl34x_platform_data adxl34x_info = {
721 .x_axis_offset = 0,
722 .y_axis_offset = 0,
723 .z_axis_offset = 0,
724 .tap_threshold = 0x31,
725 .tap_duration = 0x10,
726 .tap_latency = 0x60,
727 .tap_window = 0xF0,
728 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
729 .act_axis_control = 0xFF,
730 .activity_threshold = 5,
731 .inactivity_threshold = 3,
732 .inactivity_time = 4,
733 .free_fall_threshold = 0x7,
734 .free_fall_time = 0x20,
735 .data_rate = 0x8,
736 .data_range = ADXL_FULL_RES,
737
738 .ev_type = EV_ABS,
739 .ev_code_x = ABS_X, /* EV_REL */
740 .ev_code_y = ABS_Y, /* EV_REL */
741 .ev_code_z = ABS_Z, /* EV_REL */
742
57af8edf 743 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
ffc4d8bc
MH		 744
745/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
746/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
747 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
748 .fifo_mode = ADXL_FIFO_STREAM,
749};
750#endif
751
f5150155
MH		 752#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
753static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
754 .enable_dma = 0,
755 .bits_per_word = 16,
756};
757#endif
758
6e668936
MH		 759#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
760static struct bfin5xx_spi_chip spidev_chip_info = {
761 .enable_dma = 0,
762 .bits_per_word = 8,
763};
764#endif
765
2043f3f7
MH		 766#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
767static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
768 .enable_dma = 0,
769 .bits_per_word = 8,
770};
771#endif
772
85a192e9
MH		 773#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
774static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
775 .enable_dma = 1,
776 .bits_per_word = 8,
777 .cs_gpio = GPIO_PF10,
778};
779#endif
780
efaf7cd9
MH		 781#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
782static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
783 .bits_per_word = 16,
784 .cs_gpio = GPIO_PF10,
785};
786
787#include <linux/spi/adf702x.h>
788#define TXREG 0x0160A470
789static const u32 adf7021_regs[] = {
790 0x09608FA0,
791 0x00575011,
792 0x00A7F092,
793 0x2B141563,
794 0x81F29E94,
795 0x00003155,
796 0x050A4F66,
797 0x00000007,
798 0x00000008,
799 0x000231E9,
800 0x3296354A,
801 0x891A2B3B,
802 0x00000D9C,
803 0x0000000D,
804 0x0000000E,
805 0x0000000F,
806};
807
808static struct adf702x_platform_data adf7021_platform_data = {
809 .regs_base = (void *)SPORT1_TCR1,
810 .dma_ch_rx = CH_SPORT1_RX,
811 .dma_ch_tx = CH_SPORT1_TX,
812 .irq_sport_err = IRQ_SPORT1_ERROR,
813 .gpio_int_rfs = GPIO_PF8,
814 .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
815 P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
816 .adf702x_model = MODEL_ADF7021,
817 .adf702x_regs = adf7021_regs,
818 .tx_reg = TXREG,
819};
0531c467
MF		 820static inline void adf702x_mac_init(void)
821{
822 random_ether_addr(adf7021_platform_data.mac_addr);
823}
824#else
825static inline void adf702x_mac_init(void) {}
efaf7cd9
MH		 826#endif
827
8e9d5c7d
MH		 828#if defined(CONFIG_MTD_DATAFLASH) \
829 || defined(CONFIG_MTD_DATAFLASH_MODULE)
ceac2651
MH		 830
831static struct mtd_partition bfin_spi_dataflash_partitions[] = {
832 {
833 .name = "bootloader(spi)",
834 .size = 0x00040000,
835 .offset = 0,
836 .mask_flags = MTD_CAP_ROM
837 }, {
838 .name = "linux kernel(spi)",
6ecb5b6d 839 .size = 0x180000,
ceac2651
MH		 840 .offset = MTDPART_OFS_APPEND,
841 }, {
842 .name = "file system(spi)",
843 .size = MTDPART_SIZ_FULL,
844 .offset = MTDPART_OFS_APPEND,
845 }
846};
847
848static struct flash_platform_data bfin_spi_dataflash_data = {
849 .name = "SPI Dataflash",
850 .parts = bfin_spi_dataflash_partitions,
851 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
852};
853
8e9d5c7d
MH		 854/* DataFlash chip */
855static struct bfin5xx_spi_chip data_flash_chip_info = {
856 .enable_dma = 0, /* use dma transfer with this chip*/
857 .bits_per_word = 8,
858};
859#endif
860
57af8edf
MH		 861#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
862static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
863 .enable_dma = 0, /* use dma transfer with this chip*/
864 .bits_per_word = 8,
865};
866#endif
867
1394f032
BW		 868static struct spi_board_info bfin_spi_board_info[] __initdata = {
869#if defined(CONFIG_MTD_M25P80) \
870 || defined(CONFIG_MTD_M25P80_MODULE)
871 {
872 /* the modalias must be the same as spi device driver name */
873 .modalias = "m25p80", /* Name of spi_driver for this device */
874 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 875 .bus_num = 0, /* Framework bus number */
1394f032
BW		 876 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
877 .platform_data = &bfin_spi_flash_data,
878 .controller_data = &spi_flash_chip_info,
879 .mode = SPI_MODE_3,
880 },
881#endif
8e9d5c7d
MH		 882#if defined(CONFIG_MTD_DATAFLASH) \
883 || defined(CONFIG_MTD_DATAFLASH_MODULE)
884 { /* DataFlash chip */
885 .modalias = "mtd_dataflash",
ceac2651 886 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
8e9d5c7d
MH		 887 .bus_num = 0, /* Framework bus number */
888 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
ceac2651 889 .platform_data = &bfin_spi_dataflash_data,
8e9d5c7d
MH		 890 .controller_data = &data_flash_chip_info,
891 .mode = SPI_MODE_3,
892 },
893#endif
a261eec0
MF		 894#if defined(CONFIG_BFIN_SPI_ADC) \
895 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
1394f032
BW		 896 {
897 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
898 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 899 .bus_num = 0, /* Framework bus number */
1394f032
BW		 900 .chip_select = 1, /* Framework chip select. */
901 .platform_data = NULL, /* No spi_driver specific config */
902 .controller_data = &spi_adc_chip_info,
903 },
904#endif
905
8312440e
BS		 906#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
907 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
1394f032 908 {
dac98174 909 .modalias = "ad1836",
1394f032 910 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 911 .bus_num = 0,
8312440e 912 .chip_select = 4,/* CONFIG_SND_BLACKFIN_SPI_PFBIT */
1394f032 913 .controller_data = &ad1836_spi_chip_info,
8312440e 914 .mode = SPI_MODE_3,
1394f032
BW		 915 },
916#endif
d4b834c1
BS		 917
918#if defined(CONFIG_SND_BF5XX_SOC_AD1938) || defined(CONFIG_SND_BF5XX_SOC_AD1938_MODULE)
919 {
dac98174 920 .modalias = "ad1938",
d4b834c1
BS		 921 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
922 .bus_num = 0,
08a54bff 923 .chip_select = 5,
d4b834c1
BS		 924 .controller_data = &ad1938_spi_chip_info,
925 .mode = SPI_MODE_3,
926 },
927#endif
928
5b7c5775 929#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
427f277e
BS		 930 {
931 .modalias = "ad714x_captouch",
932 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
933 .irq = IRQ_PF4,
934 .bus_num = 0,
935 .chip_select = 5,
936 .mode = SPI_MODE_3,
5b7c5775 937 .platform_data = &ad7147_spi_platform_data,
427f277e
BS		 938 .controller_data = &ad7147_spi_chip_info,
939 },
940#endif
941
f79ea4cb
YL		 942#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
943 {
944 .modalias = "mmc_spi",
945 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
946 .bus_num = 0,
947 .chip_select = 4,
948 .platform_data = &bfin_mmc_spi_pdata,
949 .controller_data = &mmc_spi_chip_info,
950 .mode = SPI_MODE_3,
951 },
952#endif
1394f032
BW		 953#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
954 {
955 .modalias = "ad7877",
956 .platform_data = &bfin_ad7877_ts_info,
957 .irq = IRQ_PF6,
958 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c7d48966 959 .bus_num = 0,
1394f032
BW		 960 .chip_select = 1,
961 .controller_data = &spi_ad7877_chip_info,
962 },
963#endif
f5150155 964#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
46aa04f9
MH		 965 {
966 .modalias = "ad7879",
967 .platform_data = &bfin_ad7879_ts_info,
968 .irq = IRQ_PF7,
969 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
970 .bus_num = 0,
971 .chip_select = 1,
972 .controller_data = &spi_ad7879_chip_info,
973 .mode = SPI_CPHA | SPI_CPOL,
974 },
975#endif
6e668936
MH		 976#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
977 {
978 .modalias = "spidev",
979 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
980 .bus_num = 0,
981 .chip_select = 1,
982 .controller_data = &spidev_chip_info,
983 },
984#endif
2043f3f7
MH		 985#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
986 {
987 .modalias = "bfin-lq035q1-spi",
988 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
989 .bus_num = 0,
46aa04f9 990 .chip_select = 2,
2043f3f7
MH		 991 .controller_data = &lq035q1_spi_chip_info,
992 .mode = SPI_CPHA | SPI_CPOL,
993 },
994#endif
85a192e9
MH		 995#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
996 {
997 .modalias = "enc28j60",
998 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
999 .irq = IRQ_PF6,
1000 .bus_num = 0,
1001 .chip_select = 0, /* GPIO controlled SSEL */
1002 .controller_data = &enc28j60_spi_chip_info,
1003 .mode = SPI_MODE_0,
1004 },
1005#endif
57af8edf
MH		 1006#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1007 {
1008 .modalias = "adxl34x",
1009 .platform_data = &adxl34x_info,
1010 .irq = IRQ_PF6,
1011 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1012 .bus_num = 0,
1013 .chip_select = 2,
1014 .controller_data = &spi_adxl34x_chip_info,
1015 .mode = SPI_MODE_3,
1016 },
1017#endif
efaf7cd9
MH		 1018#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
1019 {
1020 .modalias = "adf702x",
1021 .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
1022 .bus_num = 0,
1023 .chip_select = 0, /* GPIO controlled SSEL */
1024 .controller_data = &adf7021_spi_chip_info,
1025 .platform_data = &adf7021_platform_data,
1026 .mode = SPI_MODE_0,
1027 },
1028#endif
1029
1394f032
BW		 1030};
1031
5bda2723 1032#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1394f032 1033/* SPI controller data */
c6c4d7bb 1034static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW		 1035 .num_chipselect = 8,
1036 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 1037 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 1038};
1039
c6c4d7bb
BW		 1040/* SPI (0) */
1041static struct resource bfin_spi0_resource[] = {
1042 [0] = {
1043 .start = SPI0_REGBASE,
1044 .end = SPI0_REGBASE + 0xFF,
1045 .flags = IORESOURCE_MEM,
1046 },
1047 [1] = {
1048 .start = CH_SPI,
1049 .end = CH_SPI,
e68d1ebc
YL		 1050 .flags = IORESOURCE_DMA,
1051 },
1052 [2] = {
1053 .start = IRQ_SPI,
1054 .end = IRQ_SPI,
c6c4d7bb
BW		 1055 .flags = IORESOURCE_IRQ,
1056 },
1057};
1058
1059static struct platform_device bfin_spi0_device = {
1060 .name = "bfin-spi",
1061 .id = 0, /* Bus number */
1062 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1063 .resource = bfin_spi0_resource,
1394f032 1064 .dev = {
c6c4d7bb 1065 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 1066 },
1067};
1068#endif /* spi master and devices */
1069
1e9aa955
CC		 1070#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
1071
1072/* SPORT SPI controller data */
1073static struct bfin5xx_spi_master bfin_sport_spi0_info = {
1074 .num_chipselect = 1, /* master only supports one device */
1075 .enable_dma = 0, /* master don't support DMA */
1076 .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
1077 P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
1078};
1079
1080static struct resource bfin_sport_spi0_resource[] = {
1081 [0] = {
1082 .start = SPORT0_TCR1,
1083 .end = SPORT0_TCR1 + 0xFF,
1084 .flags = IORESOURCE_MEM,
1085 },
1086 [1] = {
1087 .start = IRQ_SPORT0_ERROR,
1088 .end = IRQ_SPORT0_ERROR,
1089 .flags = IORESOURCE_IRQ,
1090 },
1091};
1092
1093static struct platform_device bfin_sport_spi0_device = {
1094 .name = "bfin-sport-spi",
1095 .id = 1, /* Bus number */
1096 .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
1097 .resource = bfin_sport_spi0_resource,
1098 .dev = {
1099 .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
1100 },
1101};
1102
1103static struct bfin5xx_spi_master bfin_sport_spi1_info = {
1104 .num_chipselect = 1, /* master only supports one device */
1105 .enable_dma = 0, /* master don't support DMA */
1106 .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
1107 P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
1108};
1109
1110static struct resource bfin_sport_spi1_resource[] = {
1111 [0] = {
1112 .start = SPORT1_TCR1,
1113 .end = SPORT1_TCR1 + 0xFF,
1114 .flags = IORESOURCE_MEM,
1115 },
1116 [1] = {
1117 .start = IRQ_SPORT1_ERROR,
1118 .end = IRQ_SPORT1_ERROR,
1119 .flags = IORESOURCE_IRQ,
1120 },
1121};
1122
1123static struct platform_device bfin_sport_spi1_device = {
1124 .name = "bfin-sport-spi",
1125 .id = 2, /* Bus number */
1126 .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
1127 .resource = bfin_sport_spi1_resource,
1128 .dev = {
1129 .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
1130 },
1131};
1132
1133#endif /* sport spi master and devices */
1134
1394f032
BW		 1135#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1136static struct platform_device bfin_fb_device = {
c6c4d7bb
BW		 1137 .name = "bf537-lq035",
1138};
1139#endif
1140
2043f3f7
MH		 1141#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1142#include <asm/bfin-lq035q1.h>
1143
1144static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
d94a1aa4
MH		 1145 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
1146 .ppi_mode = USE_RGB565_16_BIT_PPI,
1147 .use_bl = 0, /* let something else control the LCD Blacklight */
1148 .gpio_bl = GPIO_PF7,
2043f3f7
MH		 1149};
1150
1151static struct resource bfin_lq035q1_resources[] = {
1152 {
1153 .start = IRQ_PPI_ERROR,
1154 .end = IRQ_PPI_ERROR,
1155 .flags = IORESOURCE_IRQ,
1156 },
1157};
1158
1159static struct platform_device bfin_lq035q1_device = {
1160 .name = "bfin-lq035q1",
1161 .id = -1,
d94a1aa4
MH		 1162 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
1163 .resource = bfin_lq035q1_resources,
2043f3f7
MH		 1164 .dev = {
1165 .platform_data = &bfin_lq035q1_data,
1166 },
1167};
1168#endif
1169
1394f032 1170#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
233b28a9 1171#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 1172static struct resource bfin_uart0_resources[] = {
1394f032 1173 {
6bd1fbea
SZ		 1174 .start = UART0_THR,
1175 .end = UART0_GCTL+2,
1394f032 1176 .flags = IORESOURCE_MEM,
233b28a9 1177 },
6bd1fbea
SZ		 1178 {
1179 .start = IRQ_UART0_RX,
1180 .end = IRQ_UART0_RX+1,
1181 .flags = IORESOURCE_IRQ,
1182 },
1183 {
1184 .start = IRQ_UART0_ERROR,
1185 .end = IRQ_UART0_ERROR,
1186 .flags = IORESOURCE_IRQ,
1187 },
1188 {
1189 .start = CH_UART0_TX,
1190 .end = CH_UART0_TX,
1191 .flags = IORESOURCE_DMA,
1192 },
1193 {
1194 .start = CH_UART0_RX,
1195 .end = CH_UART0_RX,
1196 .flags = IORESOURCE_DMA,
1197 },
1198#ifdef CONFIG_BFIN_UART0_CTSRTS
1199 { /* CTS pin */
1200 .start = GPIO_PG7,
1201 .end = GPIO_PG7,
1202 .flags = IORESOURCE_IO,
1203 },
1204 { /* RTS pin */
1205 .start = GPIO_PG6,
1206 .end = GPIO_PG6,
1207 .flags = IORESOURCE_IO,
1208 },
1209#endif
1210};
1211
1212unsigned short bfin_uart0_peripherals[] = {
1213 P_UART0_TX, P_UART0_RX, 0
1214};
1215
1216static struct platform_device bfin_uart0_device = {
1217 .name = "bfin-uart",
1218 .id = 0,
1219 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
1220 .resource = bfin_uart0_resources,
1221 .dev = {
1222 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
1223 },
1224};
233b28a9
SZ		 1225#endif
1226#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 1227static struct resource bfin_uart1_resources[] = {
233b28a9 1228 {
6bd1fbea
SZ		 1229 .start = UART1_THR,
1230 .end = UART1_GCTL+2,
1394f032
BW		 1231 .flags = IORESOURCE_MEM,
1232 },
6bd1fbea
SZ		 1233 {
1234 .start = IRQ_UART1_RX,
1235 .end = IRQ_UART1_RX+1,
1236 .flags = IORESOURCE_IRQ,
1237 },
1238 {
1239 .start = IRQ_UART1_ERROR,
1240 .end = IRQ_UART1_ERROR,
1241 .flags = IORESOURCE_IRQ,
1242 },
1243 {
1244 .start = CH_UART1_TX,
1245 .end = CH_UART1_TX,
1246 .flags = IORESOURCE_DMA,
1247 },
1248 {
1249 .start = CH_UART1_RX,
1250 .end = CH_UART1_RX,
1251 .flags = IORESOURCE_DMA,
1252 },
1253};
1254
1255unsigned short bfin_uart1_peripherals[] = {
1256 P_UART1_TX, P_UART1_RX, 0
1394f032
BW		 1257};
1258
6bd1fbea 1259static struct platform_device bfin_uart1_device = {
1394f032
BW		 1260 .name = "bfin-uart",
1261 .id = 1,
6bd1fbea
SZ		 1262 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
1263 .resource = bfin_uart1_resources,
1264 .dev = {
1265 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
1266 },
1394f032
BW		 1267};
1268#endif
6bd1fbea 1269#endif
1394f032 1270
5be36d22 1271#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 1272#ifdef CONFIG_BFIN_SIR0
42bd8bcb 1273static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 1274 {
1275 .start = 0xFFC00400,
1276 .end = 0xFFC004FF,
1277 .flags = IORESOURCE_MEM,
1278 },
42bd8bcb
GY		 1279 {
1280 .start = IRQ_UART0_RX,
1281 .end = IRQ_UART0_RX+1,
1282 .flags = IORESOURCE_IRQ,
1283 },
1284 {
1285 .start = CH_UART0_RX,
1286 .end = CH_UART0_RX+1,
1287 .flags = IORESOURCE_DMA,
1288 },
1289};
1290
1291static struct platform_device bfin_sir0_device = {
1292 .name = "bfin_sir",
1293 .id = 0,
1294 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
1295 .resource = bfin_sir0_resources,
1296};
5be36d22
GY		 1297#endif
1298#ifdef CONFIG_BFIN_SIR1
42bd8bcb 1299static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 1300 {
1301 .start = 0xFFC02000,
1302 .end = 0xFFC020FF,
1303 .flags = IORESOURCE_MEM,
1304 },
42bd8bcb
GY		 1305 {
1306 .start = IRQ_UART1_RX,
1307 .end = IRQ_UART1_RX+1,
1308 .flags = IORESOURCE_IRQ,
1309 },
1310 {
1311 .start = CH_UART1_RX,
1312 .end = CH_UART1_RX+1,
1313 .flags = IORESOURCE_DMA,
1314 },
5be36d22
GY		 1315};
1316
42bd8bcb 1317static struct platform_device bfin_sir1_device = {
5be36d22 1318 .name = "bfin_sir",
42bd8bcb
GY		 1319 .id = 1,
1320 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
1321 .resource = bfin_sir1_resources,
5be36d22
GY		 1322};
1323#endif
42bd8bcb 1324#endif
5be36d22 1325
1394f032 1326#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
c6c4d7bb
BW		 1327static struct resource bfin_twi0_resource[] = {
1328 [0] = {
1329 .start = TWI0_REGBASE,
1330 .end = TWI0_REGBASE,
1331 .flags = IORESOURCE_MEM,
1332 },
1333 [1] = {
1334 .start = IRQ_TWI,
1335 .end = IRQ_TWI,
1336 .flags = IORESOURCE_IRQ,
1337 },
1338};
1339
1394f032
BW		 1340static struct platform_device i2c_bfin_twi_device = {
1341 .name = "i2c-bfin-twi",
1342 .id = 0,
c6c4d7bb
BW		 1343 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1344 .resource = bfin_twi0_resource,
1394f032
BW		 1345};
1346#endif
1347
51ed9ad7 1348#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
51ed9ad7
MH		 1349static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
1350 [0] = KEY_GRAVE,
1351 [1] = KEY_1,
1352 [2] = KEY_2,
1353 [3] = KEY_3,
1354 [4] = KEY_4,
1355 [5] = KEY_5,
1356 [6] = KEY_6,
1357 [7] = KEY_7,
1358 [8] = KEY_8,
1359 [9] = KEY_9,
1360 [10] = KEY_0,
1361 [11] = KEY_MINUS,
1362 [12] = KEY_EQUAL,
1363 [13] = KEY_BACKSLASH,
1364 [15] = KEY_KP0,
1365 [16] = KEY_Q,
1366 [17] = KEY_W,
1367 [18] = KEY_E,
1368 [19] = KEY_R,
1369 [20] = KEY_T,
1370 [21] = KEY_Y,
1371 [22] = KEY_U,
1372 [23] = KEY_I,
1373 [24] = KEY_O,
1374 [25] = KEY_P,
1375 [26] = KEY_LEFTBRACE,
1376 [27] = KEY_RIGHTBRACE,
1377 [29] = KEY_KP1,
1378 [30] = KEY_KP2,
1379 [31] = KEY_KP3,
1380 [32] = KEY_A,
1381 [33] = KEY_S,
1382 [34] = KEY_D,
1383 [35] = KEY_F,
1384 [36] = KEY_G,
1385 [37] = KEY_H,
1386 [38] = KEY_J,
1387 [39] = KEY_K,
1388 [40] = KEY_L,
1389 [41] = KEY_SEMICOLON,
1390 [42] = KEY_APOSTROPHE,
1391 [43] = KEY_BACKSLASH,
1392 [45] = KEY_KP4,
1393 [46] = KEY_KP5,
1394 [47] = KEY_KP6,
1395 [48] = KEY_102ND,
1396 [49] = KEY_Z,
1397 [50] = KEY_X,
1398 [51] = KEY_C,
1399 [52] = KEY_V,
1400 [53] = KEY_B,
1401 [54] = KEY_N,
1402 [55] = KEY_M,
1403 [56] = KEY_COMMA,
1404 [57] = KEY_DOT,
1405 [58] = KEY_SLASH,
1406 [60] = KEY_KPDOT,
1407 [61] = KEY_KP7,
1408 [62] = KEY_KP8,
1409 [63] = KEY_KP9,
1410 [64] = KEY_SPACE,
1411 [65] = KEY_BACKSPACE,
1412 [66] = KEY_TAB,
1413 [67] = KEY_KPENTER,
1414 [68] = KEY_ENTER,
1415 [69] = KEY_ESC,
1416 [70] = KEY_DELETE,
1417 [74] = KEY_KPMINUS,
1418 [76] = KEY_UP,
1419 [77] = KEY_DOWN,
1420 [78] = KEY_RIGHT,
1421 [79] = KEY_LEFT,
1422};
1423
1424static struct adp5588_kpad_platform_data adp5588_kpad_data = {
1425 .rows = 8,
1426 .cols = 10,
1427 .keymap = adp5588_keymap,
1428 .keymapsize = ARRAY_SIZE(adp5588_keymap),
1429 .repeat = 0,
1430};
1431#endif
1432
3ea57218
MH		 1433#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
1434#include <linux/mfd/adp5520.h>
1435
1436 /*
1437 * ADP5520/5501 Backlight Data
1438 */
1439
1d23dc89
MH		 1440static struct adp5520_backlight_platform_data adp5520_backlight_data = {
1441 .fade_in = ADP5520_FADE_T_1200ms,
1442 .fade_out = ADP5520_FADE_T_1200ms,
1443 .fade_led_law = ADP5520_BL_LAW_LINEAR,
1444 .en_ambl_sens = 1,
1445 .abml_filt = ADP5520_BL_AMBL_FILT_640ms,
1446 .l1_daylight_max = ADP5520_BL_CUR_mA(15),
1447 .l1_daylight_dim = ADP5520_BL_CUR_mA(0),
1448 .l2_office_max = ADP5520_BL_CUR_mA(7),
1449 .l2_office_dim = ADP5520_BL_CUR_mA(0),
1450 .l3_dark_max = ADP5520_BL_CUR_mA(3),
1451 .l3_dark_dim = ADP5520_BL_CUR_mA(0),
1452 .l2_trip = ADP5520_L2_COMP_CURR_uA(700),
1453 .l2_hyst = ADP5520_L2_COMP_CURR_uA(50),
1454 .l3_trip = ADP5520_L3_COMP_CURR_uA(80),
1455 .l3_hyst = ADP5520_L3_COMP_CURR_uA(20),
3ea57218
MH		 1456};
1457
1458 /*
1459 * ADP5520/5501 LEDs Data
1460 */
1461
3ea57218
MH		 1462static struct led_info adp5520_leds[] = {
1463 {
1464 .name = "adp5520-led1",
1465 .default_trigger = "none",
1d23dc89 1466 .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
3ea57218
MH		 1467 },
1468#ifdef ADP5520_EN_ALL_LEDS
1469 {
1470 .name = "adp5520-led2",
1471 .default_trigger = "none",
1472 .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1,
1473 },
1474 {
1475 .name = "adp5520-led3",
1476 .default_trigger = "none",
1477 .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2,
1478 },
1479#endif
1480};
1481
1d23dc89 1482static struct adp5520_leds_platform_data adp5520_leds_data = {
3ea57218
MH		 1483 .num_leds = ARRAY_SIZE(adp5520_leds),
1484 .leds = adp5520_leds,
1d23dc89
MH		 1485 .fade_in = ADP5520_FADE_T_600ms,
1486 .fade_out = ADP5520_FADE_T_600ms,
1487 .led_on_time = ADP5520_LED_ONT_600ms,
3ea57218
MH		 1488};
1489
1490 /*
1491 * ADP5520 GPIO Data
1492 */
1493
1d23dc89 1494static struct adp5520_gpio_platform_data adp5520_gpio_data = {
3ea57218 1495 .gpio_start = 50,
1d23dc89
MH		 1496 .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
1497 .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
3ea57218
MH		 1498};
1499
1500 /*
1501 * ADP5520 Keypad Data
1502 */
1503
3ea57218 1504static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
1d23dc89
MH		 1505 [ADP5520_KEY(0, 0)] = KEY_GRAVE,
1506 [ADP5520_KEY(0, 1)] = KEY_1,
1507 [ADP5520_KEY(0, 2)] = KEY_2,
1508 [ADP5520_KEY(0, 3)] = KEY_3,
1509 [ADP5520_KEY(1, 0)] = KEY_4,
1510 [ADP5520_KEY(1, 1)] = KEY_5,
1511 [ADP5520_KEY(1, 2)] = KEY_6,
1512 [ADP5520_KEY(1, 3)] = KEY_7,
1513 [ADP5520_KEY(2, 0)] = KEY_8,
1514 [ADP5520_KEY(2, 1)] = KEY_9,
1515 [ADP5520_KEY(2, 2)] = KEY_0,
1516 [ADP5520_KEY(2, 3)] = KEY_MINUS,
1517 [ADP5520_KEY(3, 0)] = KEY_EQUAL,
1518 [ADP5520_KEY(3, 1)] = KEY_BACKSLASH,
1519 [ADP5520_KEY(3, 2)] = KEY_BACKSPACE,
1520 [ADP5520_KEY(3, 3)] = KEY_ENTER,
1521};
1522
1523static struct adp5520_keys_platform_data adp5520_keys_data = {
1524 .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
1525 .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
3ea57218
MH		 1526 .keymap = adp5520_keymap,
1527 .keymapsize = ARRAY_SIZE(adp5520_keymap),
1528 .repeat = 0,
1529};
1530
1531 /*
1532 * ADP5520/5501 Multifuction Device Init Data
1533 */
1534
3ea57218 1535static struct adp5520_platform_data adp5520_pdev_data = {
1d23dc89
MH		 1536 .backlight = &adp5520_backlight_data,
1537 .leds = &adp5520_leds_data,
1538 .gpio = &adp5520_gpio_data,
1539 .keys = &adp5520_keys_data,
3ea57218
MH		 1540};
1541
1542#endif
1543
ba877d44 1544#if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE)
1d23dc89 1545static struct adp5588_gpio_platform_data adp5588_gpio_data = {
ba877d44
MH		 1546 .gpio_start = 50,
1547 .pullup_dis_mask = 0,
1548};
1549#endif
1550
78756c62
MH		 1551#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
1552#include <linux/i2c/adp8870.h>
1553static struct led_info adp8870_leds[] = {
1554 {
1555 .name = "adp8870-led7",
1556 .default_trigger = "none",
1557 .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
1558 },
1559};
1560
1561
1562static struct adp8870_backlight_platform_data adp8870_pdata = {
1563 .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
1564 ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */
1565 .pwm_assign = 0, /* 1 = Enables PWM mode */
1566
1567 .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */
1568 .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */
1569 .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
1570
1571 .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
1572 .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */
1573
1574 .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1575 .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1576 .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1577 .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1578 .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1579 .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1580 .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1581 .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1582 .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1583 .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1584
1585 .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
1586 .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
1587 .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
1588 .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
1589 .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
1590 .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
1591 .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
1592 .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
1593
1594 .leds = adp8870_leds,
1595 .num_leds = ARRAY_SIZE(adp8870_leds),
1596 .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
1597 .led_fade_in = ADP8870_FADE_T_600ms,
1598 .led_fade_out = ADP8870_FADE_T_600ms,
1599 .led_on_time = ADP8870_LED_ONT_200ms,
1600};
1601#endif
1602
81d9c7f2 1603static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
5b7c5775 1604#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
81d9c7f2 1605 {
427f277e 1606 I2C_BOARD_INFO("ad7142_captouch", 0x2C),
4c94c3e0 1607 .irq = IRQ_PG5,
5b7c5775 1608 .platform_data = (void *)&ad7142_i2c_platform_data,
81d9c7f2
BW		 1609 },
1610#endif
ebd58333 1611#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
81d9c7f2
BW		 1612 {
1613 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 1614 },
1615#endif
204844eb 1616#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
81d9c7f2
BW		 1617 {
1618 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
f5150155
MH		 1619 .irq = IRQ_PG6,
1620 },
1621#endif
1622#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
1623 {
1624 I2C_BOARD_INFO("ad7879", 0x2F),
1625 .irq = IRQ_PG5,
1626 .platform_data = (void *)&bfin_ad7879_ts_info,
81d9c7f2
BW		 1627 },
1628#endif
51ed9ad7
MH		 1629#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
1630 {
1631 I2C_BOARD_INFO("adp5588-keys", 0x34),
1632 .irq = IRQ_PG0,
1633 .platform_data = (void *)&adp5588_kpad_data,
1634 },
1635#endif
3ea57218
MH		 1636#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
1637 {
1638 I2C_BOARD_INFO("pmic-adp5520", 0x32),
4f84b6e0 1639 .irq = IRQ_PG0,
3ea57218
MH		 1640 .platform_data = (void *)&adp5520_pdev_data,
1641 },
1642#endif
ffc4d8bc
MH		 1643#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1644 {
1645 I2C_BOARD_INFO("adxl34x", 0x53),
1646 .irq = IRQ_PG3,
1647 .platform_data = (void *)&adxl34x_info,
1648 },
1649#endif
ba877d44
MH		 1650#if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE)
1651 {
1652 I2C_BOARD_INFO("adp5588-gpio", 0x34),
1653 .platform_data = (void *)&adp5588_gpio_data,
1654 },
1655#endif
50c4c086
MH		 1656#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
1657 {
1658 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
1659 },
1660#endif
ddcd7cb8
MH		 1661#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1662 {
1663 I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C),
1664 },
1665#endif
78756c62
MH		 1666#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
1667 {
1668 I2C_BOARD_INFO("adp8870", 0x2B),
1669 .platform_data = (void *)&adp8870_pdata,
1670 },
1671#endif
d53127ff
CC		 1672#if defined(CONFIG_SND_SOC_ADAU1371) || defined(CONFIG_SND_SOC_ADAU1371_MODULE)
1673 {
1674 I2C_BOARD_INFO("adau1371", 0x1A),
1675 },
1676#endif
04267638
CC		 1677#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
1678 {
1679 I2C_BOARD_INFO("adau1761", 0x38),
1680 },
1681#endif
1f13f2fd
MH		 1682#if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE)
1683 {
1684 I2C_BOARD_INFO("ad5258", 0x18),
1685 },
1686#endif
29bb3bc0
CC		 1687#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
1688 {
1689 I2C_BOARD_INFO("ssm2602", 0x1b),
1690 },
1691#endif
81d9c7f2 1692};
81d9c7f2 1693
1394f032 1694#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 1695#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1696static struct resource bfin_sport0_uart_resources[] = {
1697 {
1698 .start = SPORT0_TCR1,
1699 .end = SPORT0_MRCS3+4,
1700 .flags = IORESOURCE_MEM,
1701 },
1702 {
1703 .start = IRQ_SPORT0_RX,
1704 .end = IRQ_SPORT0_RX+1,
1705 .flags = IORESOURCE_IRQ,
1706 },
1707 {
1708 .start = IRQ_SPORT0_ERROR,
1709 .end = IRQ_SPORT0_ERROR,
1710 .flags = IORESOURCE_IRQ,
1711 },
1712};
1713
1714unsigned short bfin_sport0_peripherals[] = {
1715 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
1716 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
1717};
1718
1394f032
BW		 1719static struct platform_device bfin_sport0_uart_device = {
1720 .name = "bfin-sport-uart",
1721 .id = 0,
df5de261
SZ		 1722 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
1723 .resource = bfin_sport0_uart_resources,
1724 .dev = {
1725 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
1726 },
1727};
1728#endif
1729#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1730static struct resource bfin_sport1_uart_resources[] = {
1731 {
1732 .start = SPORT1_TCR1,
1733 .end = SPORT1_MRCS3+4,
1734 .flags = IORESOURCE_MEM,
1735 },
1736 {
1737 .start = IRQ_SPORT1_RX,
1738 .end = IRQ_SPORT1_RX+1,
1739 .flags = IORESOURCE_IRQ,
1740 },
1741 {
1742 .start = IRQ_SPORT1_ERROR,
1743 .end = IRQ_SPORT1_ERROR,
1744 .flags = IORESOURCE_IRQ,
1745 },
1746};
1747
1748unsigned short bfin_sport1_peripherals[] = {
1749 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
1750 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
1394f032
BW		 1751};
1752
1753static struct platform_device bfin_sport1_uart_device = {
1754 .name = "bfin-sport-uart",
1755 .id = 1,
df5de261
SZ		 1756 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
1757 .resource = bfin_sport1_uart_resources,
1758 .dev = {
1759 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
1760 },
1394f032
BW		 1761};
1762#endif
df5de261 1763#endif
1394f032 1764
c6c4d7bb 1765#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
2c8beb2c
MH		 1766#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
1767/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
c6c4d7bb 1768
2c8beb2c
MH		 1769#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE
1770#define PATA_INT IRQ_PF5
c6c4d7bb
BW		 1771static struct pata_platform_info bfin_pata_platform_data = {
1772 .ioport_shift = 1,
64e5c512 1773 .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
c6c4d7bb
BW		 1774};
1775
1776static struct resource bfin_pata_resources[] = {
1777 {
1778 .start = 0x20314020,
1779 .end = 0x2031403F,
1780 .flags = IORESOURCE_MEM,
1781 },
1782 {
1783 .start = 0x2031401C,
1784 .end = 0x2031401F,
1785 .flags = IORESOURCE_MEM,
1786 },
1787 {
1788 .start = PATA_INT,
1789 .end = PATA_INT,
1790 .flags = IORESOURCE_IRQ,
1791 },
1792};
2c8beb2c
MH		 1793#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE)
1794static struct pata_platform_info bfin_pata_platform_data = {
1795 .ioport_shift = 0,
1796};
648882d9
MH		 1797/* CompactFlash Storage Card Memory Mapped Adressing
1798 * /REG = A11 = 1
1799 */
2c8beb2c
MH		 1800static struct resource bfin_pata_resources[] = {
1801 {
648882d9
MH		 1802 .start = 0x20211800,
1803 .end = 0x20211807,
2c8beb2c
MH		 1804 .flags = IORESOURCE_MEM,
1805 },
1806 {
648882d9
MH		 1807 .start = 0x2021180E, /* Device Ctl */
1808 .end = 0x2021180E,
2c8beb2c
MH		 1809 .flags = IORESOURCE_MEM,
1810 },
1811};
1812#endif
c6c4d7bb
BW		 1813
1814static struct platform_device bfin_pata_device = {
1815 .name = "pata_platform",
1816 .id = -1,
1817 .num_resources = ARRAY_SIZE(bfin_pata_resources),
1818 .resource = bfin_pata_resources,
1819 .dev = {
1820 .platform_data = &bfin_pata_platform_data,
1821 }
1822};
1823#endif
1824
14b03204
MH		 1825static const unsigned int cclk_vlev_datasheet[] =
1826{
1827 VRPAIR(VLEV_085, 250000000),
1828 VRPAIR(VLEV_090, 376000000),
1829 VRPAIR(VLEV_095, 426000000),
1830 VRPAIR(VLEV_100, 426000000),
1831 VRPAIR(VLEV_105, 476000000),
1832 VRPAIR(VLEV_110, 476000000),
1833 VRPAIR(VLEV_115, 476000000),
1834 VRPAIR(VLEV_120, 500000000),
1835 VRPAIR(VLEV_125, 533000000),
1836 VRPAIR(VLEV_130, 600000000),
1837};
1838
1839static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1840 .tuple_tab = cclk_vlev_datasheet,
1841 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1842 .vr_settling_time = 25 /* us */,
1843};
1844
1845static struct platform_device bfin_dpmc = {
1846 .name = "bfin dpmc",
1847 .dev = {
1848 .platform_data = &bfin_dmpc_vreg_data,
1849 },
1850};
1851
8312440e
BS		 1852#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1853static struct platform_device bfin_tdm = {
1854 .name = "bfin-tdm",
1855 /* TODO: add platform data here */
1856};
1857#endif
1858
1394f032 1859static struct platform_device *stamp_devices[] __initdata = {
14b03204
MH		 1860
1861 &bfin_dpmc,
1862
1394f032
BW		 1863#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
1864 &bfin_pcmcia_cf_device,
1865#endif
1866
1867#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1868 &rtc_device,
1869#endif
1870
1871#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
1872 &sl811_hcd_device,
1873#endif
1874
1875#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
1876 &isp1362_hcd_device,
1877#endif
1878
3f375690
MH		 1879#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1880 &bfin_isp1760_device,
1881#endif
1882
1394f032
BW		 1883#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
1884 &smc91x_device,
1885#endif
1886
f40d24d9
AL		 1887#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
1888 &dm9000_device,
1889#endif
1890
706a01b1
BS		 1891#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1892 &bfin_can_device,
1893#endif
1894
1394f032 1895#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 1896 &bfin_mii_bus,
1394f032
BW		 1897 &bfin_mac_device,
1898#endif
1899
1900#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
1901 &net2272_bfin_device,
1902#endif
1903
1904#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb 1905 &bfin_spi0_device,
1394f032
BW		 1906#endif
1907
1e9aa955
CC		 1908#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
1909 &bfin_sport_spi0_device,
1910 &bfin_sport_spi1_device,
1911#endif
1912
1394f032
BW		 1913#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1914 &bfin_fb_device,
1915#endif
1916
2043f3f7
MH		 1917#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1918 &bfin_lq035q1_device,
1919#endif
1920
1394f032 1921#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 1922#ifdef CONFIG_SERIAL_BFIN_UART0
1923 &bfin_uart0_device,
1924#endif
1925#ifdef CONFIG_SERIAL_BFIN_UART1
1926 &bfin_uart1_device,
1927#endif
1394f032
BW		 1928#endif
1929
5be36d22 1930#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 1931#ifdef CONFIG_BFIN_SIR0
1932 &bfin_sir0_device,
1933#endif
1934#ifdef CONFIG_BFIN_SIR1
1935 &bfin_sir1_device,
1936#endif
5be36d22
GY		 1937#endif
1938
1394f032
BW		 1939#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1940 &i2c_bfin_twi_device,
1941#endif
1942
1943#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 1944#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1394f032 1945 &bfin_sport0_uart_device,
df5de261
SZ		 1946#endif
1947#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1394f032
BW		 1948 &bfin_sport1_uart_device,
1949#endif
df5de261 1950#endif
c6c4d7bb
BW		 1951
1952#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1953 &bfin_pata_device,
1954#endif
2463ef22
MH		 1955
1956#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1957 &bfin_device_gpiokeys,
1958#endif
cad2ab65 1959
fc68911e
MF		 1960#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
1961 &bfin_async_nand_device,
1962#endif
1963
793dc27b 1964#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1965 &stamp_flash_device,
793dc27b 1966#endif
8312440e
BS		 1967
1968#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1969 &bfin_tdm,
1970#endif
1394f032
BW		 1971};
1972
1973static int __init stamp_init(void)
1974{
b85d858b 1975 printk(KERN_INFO "%s(): registering device resources\n", __func__);
fc68911e 1976 bfin_plat_nand_init();
0531c467 1977 adf702x_mac_init();
1394f032 1978 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
df5de261
SZ		 1979 i2c_register_board_info(0, bfin_i2c_board_info,
1980 ARRAY_SIZE(bfin_i2c_board_info));
5bda2723 1981 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb 1982
1394f032
BW		 1983 return 0;
1984}
1985
1986arch_initcall(stamp_init);
c6c4d7bb 1987
c13ce9fd
SZ		 1988
1989static struct platform_device *stamp_early_devices[] __initdata = {
1990#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1991#ifdef CONFIG_SERIAL_BFIN_UART0
1992 &bfin_uart0_device,
1993#endif
1994#ifdef CONFIG_SERIAL_BFIN_UART1
1995 &bfin_uart1_device,
1996#endif
1997#endif
1998
1999#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
2000#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2001 &bfin_sport0_uart_device,
2002#endif
2003#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2004 &bfin_sport1_uart_device,
2005#endif
2006#endif
2007};
2008
2009void __init native_machine_early_platform_add_devices(void)
2010{
2011 printk(KERN_INFO "register early platform devices\n");
2012 early_platform_add_devices(stamp_early_devices,
2013 ARRAY_SIZE(stamp_early_devices));
2014}
2015
c6c4d7bb
BW		 2016void native_machine_restart(char *cmd)
2017{
2018 /* workaround reboot hang when booting from SPI */
2019 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 2020 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
c6c4d7bb 2021}
137b1529
MF		 2022
2023/*
2024 * Currently the MAC address is saved in Flash by U-Boot
2025 */
2026#define FLASH_MAC 0x203f0000
9862cc52 2027void bfin_get_ether_addr(char *addr)
137b1529
MF		 2028{
2029 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
2030 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
2031}
9862cc52 2032EXPORT_SYMBOL(bfin_get_ether_addr);
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