[net-next-2.6.git] / arch / blackfin / mach-bf533 / include / mach / mem_map.h

/*
 * File:         include/asm-blackfin/mach-bf533/mem_map.h
 * Based on:
 * Author:
 *
 * Created:
 * Description:
 *
 * Rev:
 *
 * Modified:
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; see the file COPYING.
 * If not, write to the Free Software Foundation,
 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

#ifndef _MEM_MAP_533_H_
#define _MEM_MAP_533_H_

#define COREMMR_BASE           0xFFE00000	 /* Core MMRs */
#define SYSMMR_BASE            0xFFC00000	 /* System MMRs */

/* Async Memory Banks */
#define ASYNC_BANK3_BASE	0x20300000	 /* Async Bank 3 */
#define ASYNC_BANK3_SIZE	0x00100000	/* 1M */
#define ASYNC_BANK2_BASE	0x20200000	 /* Async Bank 2 */
#define ASYNC_BANK2_SIZE	0x00100000	/* 1M */
#define ASYNC_BANK1_BASE	0x20100000	 /* Async Bank 1 */
#define ASYNC_BANK1_SIZE	0x00100000	/* 1M */
#define ASYNC_BANK0_BASE	0x20000000	 /* Async Bank 0 */
#define ASYNC_BANK0_SIZE	0x00100000	/* 1M */

/* Boot ROM Memory */

#define BOOT_ROM_START		0xEF000000
#define BOOT_ROM_LENGTH		0x400

/* Level 1 Memory */

#ifdef CONFIG_BFIN_ICACHE
#define BFIN_ICACHESIZE	(16*1024)
#else
#define BFIN_ICACHESIZE	(0*1024)
#endif

/* Memory Map for ADSP-BF533 processors */

#ifdef CONFIG_BF533
#define L1_CODE_START       0xFFA00000
#define L1_DATA_A_START     0xFF800000
#define L1_DATA_B_START     0xFF900000

#ifdef CONFIG_BFIN_ICACHE
#define L1_CODE_LENGTH      (0x14000 - 0x4000)
#else
#define L1_CODE_LENGTH      0x14000
#endif

#ifdef CONFIG_BFIN_DCACHE

#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH      0x8000
#define BFIN_DCACHESIZE	(16*1024)
#define BFIN_DSUPBANKS	1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
#define BFIN_DCACHESIZE	(32*1024)
#define BFIN_DSUPBANKS	2
#endif

#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      0x8000
#define L1_DATA_B_LENGTH      0x8000
#define BFIN_DCACHESIZE	(0*1024)
#define BFIN_DSUPBANKS	0
#endif /*CONFIG_BFIN_DCACHE*/
#endif

/* Memory Map for ADSP-BF532 processors */

#ifdef CONFIG_BF532
#define L1_CODE_START       0xFFA08000
#define L1_DATA_A_START     0xFF804000
#define L1_DATA_B_START     0xFF904000

#ifdef CONFIG_BFIN_ICACHE
#define L1_CODE_LENGTH      (0xC000 - 0x4000)
#else
#define L1_CODE_LENGTH      0xC000
#endif

#ifdef CONFIG_BFIN_DCACHE

#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
#define L1_DATA_B_LENGTH      0x4000
#define BFIN_DCACHESIZE	(16*1024)
#define BFIN_DSUPBANKS	1

#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
#define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
#define BFIN_DCACHESIZE	(32*1024)
#define BFIN_DSUPBANKS	2
#endif

#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      0x4000
#define L1_DATA_B_LENGTH      0x4000
#define BFIN_DCACHESIZE	(0*1024)
#define BFIN_DSUPBANKS	0
#endif /*CONFIG_BFIN_DCACHE*/
#endif

/* Memory Map for ADSP-BF531 processors */

#ifdef CONFIG_BF531
#define L1_CODE_START       0xFFA08000
#define L1_DATA_A_START     0xFF804000
#define L1_DATA_B_START     0xFF904000
#define L1_CODE_LENGTH      0x4000
#define L1_DATA_B_LENGTH      0x0000


#ifdef CONFIG_BFIN_DCACHE
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB  | PORT_PREF0)
#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
#define BFIN_DCACHESIZE	(16*1024)
#define BFIN_DSUPBANKS	1
#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB  | PORT_PREF0)
#define L1_DATA_A_LENGTH      0x4000
#define BFIN_DCACHESIZE	(0*1024)
#define BFIN_DSUPBANKS	0
#endif

#endif

/* Level 2 Memory - none */

#define L2_START	0
#define L2_LENGTH	0

/* Scratch Pad Memory */

#define L1_SCRATCH_START	0xFFB00000
#define L1_SCRATCH_LENGTH	0x1000

#define get_l1_scratch_start_cpu(cpu)		L1_SCRATCH_START
#define get_l1_code_start_cpu(cpu)		L1_CODE_START
#define get_l1_data_a_start_cpu(cpu)		L1_DATA_A_START
#define get_l1_data_b_start_cpu(cpu)		L1_DATA_B_START
#define get_l1_scratch_start()			L1_SCRATCH_START
#define get_l1_code_start()			L1_CODE_START
#define get_l1_data_a_start()			L1_DATA_A_START
#define get_l1_data_b_start()			L1_DATA_B_START

#define GET_PDA_SAFE(preg)		\
	preg.l = _cpu_pda;		\
	preg.h = _cpu_pda;

#define GET_PDA(preg, dreg)	GET_PDA_SAFE(preg)

#endif				/* _MEM_MAP_533_H_ */
Commit	Line	Data
1394f032 BW	1	/*
	2	* File: include/asm-blackfin/mach-bf533/mem_map.h
	3	* Based on:
	4	* Author:
	5	*
	6	* Created:
	7	* Description:
	8	*
	9	* Rev:
	10	*
	11	* Modified:
	12	*
	13	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License as published by
	17	* the Free Software Foundation; either version 2, or (at your option)
	18	* any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; see the file COPYING.
	27	* If not, write to the Free Software Foundation,
	28	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	29	*/
	30
	31	#ifndef _MEM_MAP_533_H_
	32	#define _MEM_MAP_533_H_
	33
	34	#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
	35	#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
	36
	37	/* Async Memory Banks */
	38	#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
	39	#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
	40	#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
	41	#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
	42	#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
	43	#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
	44	#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
	45	#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
	46
	47	/* Boot ROM Memory */
	48
	49	#define BOOT_ROM_START 0xEF000000
c3a9f435	50	#define BOOT_ROM_LENGTH 0x400
1394f032 BW	51
	52	/* Level 1 Memory */
	53
3bebca2d RG	54	#ifdef CONFIG_BFIN_ICACHE
3bebca2d RG	55	#define BFIN_ICACHESIZE (16*1024)
1394f032	56	#else
3bebca2d	57	#define BFIN_ICACHESIZE (0*1024)
1394f032 BW	58	#endif
	59
	60	/* Memory Map for ADSP-BF533 processors */
	61
	62	#ifdef CONFIG_BF533
	63	#define L1_CODE_START 0xFFA00000
	64	#define L1_DATA_A_START 0xFF800000
	65	#define L1_DATA_B_START 0xFF900000
	66
3bebca2d	67	#ifdef CONFIG_BFIN_ICACHE
1394f032 BW	68	#define L1_CODE_LENGTH (0x14000 - 0x4000)
	69	#else
	70	#define L1_CODE_LENGTH 0x14000
	71	#endif
	72
3bebca2d	73	#ifdef CONFIG_BFIN_DCACHE
1394f032	74
3bebca2d	75	#ifdef CONFIG_BFIN_DCACHE_BANKA
1394f032 BW	76	#define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0)
	77	#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
	78	#define L1_DATA_B_LENGTH 0x8000
3bebca2d RG	79	#define BFIN_DCACHESIZE (16*1024)
3bebca2d RG	80	#define BFIN_DSUPBANKS 1
1394f032 BW	81	#else
	82	#define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0)
	83	#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
	84	#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
3bebca2d RG	85	#define BFIN_DCACHESIZE (32*1024)
3bebca2d RG	86	#define BFIN_DSUPBANKS 2
1394f032 BW	87	#endif
	88
	89	#else
	90	#define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)
	91	#define L1_DATA_A_LENGTH 0x8000
	92	#define L1_DATA_B_LENGTH 0x8000
3bebca2d RG	93	#define BFIN_DCACHESIZE (0*1024)
	94	#define BFIN_DSUPBANKS 0
	95	#endif /CONFIG_BFIN_DCACHE/
1394f032 BW	96	#endif
	97
	98	/* Memory Map for ADSP-BF532 processors */
	99
	100	#ifdef CONFIG_BF532
	101	#define L1_CODE_START 0xFFA08000
	102	#define L1_DATA_A_START 0xFF804000
	103	#define L1_DATA_B_START 0xFF904000
	104
3bebca2d	105	#ifdef CONFIG_BFIN_ICACHE
1394f032 BW	106	#define L1_CODE_LENGTH (0xC000 - 0x4000)
	107	#else
	108	#define L1_CODE_LENGTH 0xC000
	109	#endif
	110
3bebca2d	111	#ifdef CONFIG_BFIN_DCACHE
1394f032	112
3bebca2d	113	#ifdef CONFIG_BFIN_DCACHE_BANKA
1394f032 BW	114	#define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0)
	115	#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
	116	#define L1_DATA_B_LENGTH 0x4000
3bebca2d RG	117	#define BFIN_DCACHESIZE (16*1024)
3bebca2d RG	118	#define BFIN_DSUPBANKS 1
1394f032 BW	119
	120	#else
	121	#define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0)
	122	#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
	123	#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
3bebca2d RG	124	#define BFIN_DCACHESIZE (32*1024)
3bebca2d RG	125	#define BFIN_DSUPBANKS 2
1394f032 BW	126	#endif
	127
	128	#else
	129	#define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)
	130	#define L1_DATA_A_LENGTH 0x4000
	131	#define L1_DATA_B_LENGTH 0x4000
3bebca2d RG	132	#define BFIN_DCACHESIZE (0*1024)
	133	#define BFIN_DSUPBANKS 0
	134	#endif /CONFIG_BFIN_DCACHE/
1394f032 BW	135	#endif
	136
	137	/* Memory Map for ADSP-BF531 processors */
	138
	139	#ifdef CONFIG_BF531
	140	#define L1_CODE_START 0xFFA08000
	141	#define L1_DATA_A_START 0xFF804000
	142	#define L1_DATA_B_START 0xFF904000
	143	#define L1_CODE_LENGTH 0x4000
	144	#define L1_DATA_B_LENGTH 0x0000
	145
	146
3bebca2d	147	#ifdef CONFIG_BFIN_DCACHE
1394f032 BW	148	#define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0)
1394f032 BW	149	#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
3bebca2d RG	150	#define BFIN_DCACHESIZE (16*1024)
3bebca2d RG	151	#define BFIN_DSUPBANKS 1
1394f032 BW	152	#else
	153	#define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)
	154	#define L1_DATA_A_LENGTH 0x4000
3bebca2d RG	155	#define BFIN_DCACHESIZE (0*1024)
3bebca2d RG	156	#define BFIN_DSUPBANKS 0
1394f032 BW	157	#endif
	158
	159	#endif
	160
07aa7be5 MF	161	/* Level 2 Memory - none */
	162
	163	#define L2_START 0
	164	#define L2_LENGTH 0
	165
1394f032 BW	166	/* Scratch Pad Memory */
1394f032 BW	167
1394f032 BW	168	#define L1_SCRATCH_START 0xFFB00000
1394f032 BW	169	#define L1_SCRATCH_LENGTH 0x1000
1394f032	170
46fa5eec GY	171	#define get_l1_scratch_start_cpu(cpu) L1_SCRATCH_START
	172	#define get_l1_code_start_cpu(cpu) L1_CODE_START
	173	#define get_l1_data_a_start_cpu(cpu) L1_DATA_A_START
	174	#define get_l1_data_b_start_cpu(cpu) L1_DATA_B_START
	175	#define get_l1_scratch_start() L1_SCRATCH_START
	176	#define get_l1_code_start() L1_CODE_START
	177	#define get_l1_data_a_start() L1_DATA_A_START
	178	#define get_l1_data_b_start() L1_DATA_B_START
	179
	180	#define GET_PDA_SAFE(preg) \
	181	preg.l = _cpu_pda; \
	182	preg.h = _cpu_pda;
	183
	184	#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
	185
1394f032	186	#endif /* _MEM_MAP_533_H_ */