git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 1394f032 | 1 | /* |
| 96f1050d | 2 | * System & MMR bit and Address definitions for ADSP-BF532 |
| 1394f032 | 3 | * |
| 96f1050d | 4 | * Copyright 2005-2008 Analog Devices Inc. |
| 1394f032 | 5 | * |
| 96f1050d | 6 | * Licensed under the ADI BSD license or the GPL-2 (or later) |
| 1394f032 | 7 | */ |
| 1394f032 BW |
8 | |
| 9 | #ifndef _DEF_BF532_H | |
| 10 | #define _DEF_BF532_H | |
| 19381f02 | 11 | |
| 1394f032 | 12 | /* include all Core registers and bit definitions */ |
| 639f6571 | 13 | #include <asm/def_LPBlackfin.h> |
| 1394f032 BW |
14 | |
| 15 | /*********************************************************************************** */ | |
| 16 | /* System MMR Register Map */ | |
| 17 | /*********************************************************************************** */ | |
| 18 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | |
| 19 | ||
| 20 | #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ | |
| 21 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ | |
| 22 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ | |
| 23 | #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ | |
| 24 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ | |
| 25 | #define CHIPID 0xFFC00014 /* Chip ID Register */ | |
| 1394f032 BW |
26 | |
| 27 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | |
| 19381f02 BW |
28 | #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ |
| 29 | #define SYSCR 0xFFC00104 /* System Configuration registe */ | |
| 1394f032 BW |
30 | #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ |
| 31 | #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ | |
| 32 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ | |
| 33 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ | |
| 34 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ | |
| 35 | #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ | |
| 36 | #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ | |
| 37 | ||
| 38 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | |
| 39 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ | |
| 40 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ | |
| 41 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ | |
| 42 | ||
| 43 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | |
| 44 | #define RTC_STAT 0xFFC00300 /* RTC Status Register */ | |
| 45 | #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ | |
| 46 | #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ | |
| 47 | #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ | |
| 48 | #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ | |
| 49 | #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ | |
| 50 | #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ | |
| 51 | ||
| 52 | /* UART Controller (0xFFC00400 - 0xFFC004FF) */ | |
| 6ed83942 GY |
53 | |
| 54 | /* | |
| 55 | * Because include/linux/serial_reg.h have defined UART_*, | |
| 56 | * So we define blackfin uart regs to BFIN_UART_*. | |
| 57 | */ | |
| 58 | #define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ | |
| 59 | #define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ | |
| 60 | #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | |
| 61 | #define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ | |
| 62 | #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | |
| 63 | #define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ | |
| 64 | #define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ | |
| 65 | #define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ | |
| 66 | #define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ | |
| 1394f032 | 67 | #if 0 |
| 6ed83942 | 68 | #define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ |
| 1394f032 | 69 | #endif |
| 6ed83942 GY |
70 | #define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ |
| 71 | #define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ | |
| 1394f032 BW |
72 | |
| 73 | /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ | |
| 1d487f46 | 74 | #define SPI0_REGBASE 0xFFC00500 |
| 1394f032 BW |
75 | #define SPI_CTL 0xFFC00500 /* SPI Control Register */ |
| 76 | #define SPI_FLG 0xFFC00504 /* SPI Flag register */ | |
| 77 | #define SPI_STAT 0xFFC00508 /* SPI Status register */ | |
| 78 | #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ | |
| 79 | #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ | |
| 80 | #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ | |
| 81 | #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ | |
| 82 | ||
| 83 | /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ | |
| 84 | ||
| 85 | #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ | |
| 86 | #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ | |
| 87 | #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ | |
| 88 | #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ | |
| 89 | ||
| 90 | #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ | |
| 91 | #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ | |
| 92 | #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ | |
| 93 | #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ | |
| 94 | ||
| 95 | #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ | |
| 96 | #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ | |
| 97 | #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ | |
| 98 | #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ | |
| 99 | ||
| 100 | #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ | |
| 101 | #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ | |
| 102 | #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ | |
| 103 | ||
| 104 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ | |
| 105 | ||
| 106 | #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ | |
| 107 | #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ | |
| 108 | #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ | |
| 109 | #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ | |
| 110 | #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ | |
| 111 | #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ | |
| 112 | #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ | |
| 113 | #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ | |
| 114 | #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ | |
| 115 | #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ | |
| 116 | #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ | |
| 117 | #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ | |
| 118 | #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ | |
| 119 | #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ | |
| 120 | #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ | |
| 121 | #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ | |
| 122 | #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ | |
| 123 | ||
| 124 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | |
| 125 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | |
| 126 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | |
| 127 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | |
| 128 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | |
| 129 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | |
| 130 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | |
| 131 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | |
| 132 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | |
| 133 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | |
| 134 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | |
| 135 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | |
| 136 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | |
| 137 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | |
| 138 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | |
| 139 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | |
| 140 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | |
| 141 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | |
| 142 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | |
| 143 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | |
| 144 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | |
| 145 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | |
| 146 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | |
| 147 | ||
| 148 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | |
| 149 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | |
| 150 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | |
| 151 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | |
| 152 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | |
| 153 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | |
| 154 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | |
| 155 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | |
| 156 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | |
| 157 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | |
| 158 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | |
| 159 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | |
| 160 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | |
| 161 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | |
| 162 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | |
| 163 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | |
| 164 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | |
| 165 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | |
| 166 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | |
| 167 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | |
| 168 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | |
| 169 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | |
| 170 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | |
| 171 | ||
| 172 | /* Asynchronous Memory Controller - External Bus Interface Unit */ | |
| 173 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | |
| 174 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | |
| 175 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | |
| 176 | ||
| 177 | /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | |
| 178 | ||
| 179 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | |
| 180 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | |
| 181 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | |
| 182 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | |
| 183 | ||
| 184 | /* DMA Traffic controls */ | |
| 1394f032 BW |
185 | #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ |
| 186 | #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | |
| 187 | ||
| 19381f02 BW |
188 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ |
| 189 | #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ | |
| 190 | #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | |
| 191 | ||
| 1394f032 BW |
192 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ |
| 193 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ | |
| 194 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | |
| 195 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ | |
| 196 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ | |
| 197 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ | |
| 198 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ | |
| 199 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ | |
| 200 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ | |
| 201 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ | |
| 202 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ | |
| 203 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ | |
| 204 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ | |
| 205 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ | |
| 206 | ||
| 207 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ | |
| 208 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ | |
| 209 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ | |
| 210 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ | |
| 211 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ | |
| 212 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ | |
| 213 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ | |
| 214 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ | |
| 215 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ | |
| 216 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ | |
| 217 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ | |
| 218 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ | |
| 219 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ | |
| 220 | ||
| 221 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ | |
| 222 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ | |
| 223 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ | |
| 224 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ | |
| 225 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ | |
| 226 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ | |
| 227 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ | |
| 228 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ | |
| 229 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ | |
| 230 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ | |
| 231 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ | |
| 232 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ | |
| 233 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ | |
| 234 | ||
| 235 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ | |
| 236 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ | |
| 237 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ | |
| 238 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ | |
| 239 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ | |
| 240 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ | |
| 241 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ | |
| 242 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ | |
| 243 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ | |
| 244 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ | |
| 245 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ | |
| 246 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ | |
| 247 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ | |
| 248 | ||
| 249 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ | |
| 250 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ | |
| 251 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ | |
| 252 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ | |
| 253 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ | |
| 254 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ | |
| 255 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ | |
| 256 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ | |
| 257 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ | |
| 258 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ | |
| 259 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ | |
| 260 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ | |
| 261 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ | |
| 262 | ||
| 263 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ | |
| 264 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ | |
| 265 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ | |
| 266 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ | |
| 267 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ | |
| 268 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ | |
| 269 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ | |
| 270 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ | |
| 271 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ | |
| 272 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ | |
| 273 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ | |
| 274 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ | |
| 275 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ | |
| 276 | ||
| 277 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ | |
| 278 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ | |
| 279 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ | |
| 280 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ | |
| 281 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ | |
| 282 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ | |
| 283 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ | |
| 284 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ | |
| 285 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ | |
| 286 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ | |
| 287 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ | |
| 288 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ | |
| 289 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ | |
| 290 | ||
| 291 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ | |
| 292 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ | |
| 293 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ | |
| 294 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ | |
| 295 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ | |
| 296 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ | |
| 297 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ | |
| 298 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ | |
| 299 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ | |
| 300 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ | |
| 301 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ | |
| 302 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ | |
| 303 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ | |
| 304 | ||
| 305 | #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ | |
| 306 | #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ | |
| 307 | #define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ | |
| 308 | #define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ | |
| 309 | #define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ | |
| 310 | #define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ | |
| 311 | #define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ | |
| 312 | #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ | |
| 313 | #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ | |
| 314 | #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ | |
| 315 | #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ | |
| 316 | #define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ | |
| 317 | #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ | |
| 318 | ||
| 319 | #define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ | |
| 320 | #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ | |
| 321 | #define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ | |
| 322 | #define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ | |
| 323 | #define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ | |
| 324 | #define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ | |
| 325 | #define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ | |
| 326 | #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ | |
| 327 | #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ | |
| 328 | #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ | |
| 329 | #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ | |
| 330 | #define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ | |
| 331 | #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ | |
| 332 | ||
| 333 | #define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ | |
| 334 | #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ | |
| 335 | #define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ | |
| 336 | #define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ | |
| 337 | #define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ | |
| 338 | #define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ | |
| 339 | #define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ | |
| 340 | #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ | |
| 341 | #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ | |
| 342 | #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ | |
| 343 | #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ | |
| 344 | #define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ | |
| 345 | #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ | |
| 346 | ||
| 347 | #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ | |
| 348 | #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ | |
| 349 | #define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ | |
| 350 | #define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ | |
| 351 | #define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ | |
| 352 | #define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ | |
| 353 | #define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ | |
| 354 | #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ | |
| 355 | #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ | |
| 356 | #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ | |
| 357 | #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ | |
| 358 | #define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ | |
| 359 | #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ | |
| 360 | ||
| 361 | /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ | |
| 362 | ||
| 363 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ | |
| 364 | #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ | |
| 365 | #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ | |
| 366 | #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ | |
| 367 | #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ | |
| 368 | ||
| 369 | /*********************************************************************************** */ | |
| 370 | /* System MMR Register Bits */ | |
| 371 | /******************************************************************************* */ | |
| 372 | ||
| 1394f032 BW |
373 | /* CHIPID Masks */ |
| 374 | #define CHIPID_VERSION 0xF0000000 | |
| 375 | #define CHIPID_FAMILY 0x0FFFF000 | |
| 376 | #define CHIPID_MANUFACTURE 0x00000FFE | |
| 377 | ||
| 378 | /* SWRST Mask */ | |
| 19381f02 BW |
379 | #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ |
| 380 | #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ | |
| 381 | #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ | |
| 382 | #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ | |
| 383 | #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ | |
| 384 | ||
| 385 | /* SYSCR Masks */ | |
| 386 | #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ | |
| 387 | #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ | |
| 1394f032 BW |
388 | |
| 389 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ | |
| 390 | ||
| 391 | /* SIC_IAR0 Masks */ | |
| 392 | ||
| 393 | #define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ | |
| 394 | #define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ | |
| 395 | #define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ | |
| 396 | #define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ | |
| 397 | #define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ | |
| 398 | #define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ | |
| 399 | #define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ | |
| 400 | #define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ | |
| 401 | ||
| 402 | /* SIC_IAR1 Masks */ | |
| 403 | ||
| 404 | #define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ | |
| 405 | #define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ | |
| 406 | #define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ | |
| 407 | #define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ | |
| 408 | #define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ | |
| 409 | #define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ | |
| 410 | #define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ | |
| 411 | #define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ | |
| 412 | ||
| 413 | /* SIC_IAR2 Masks */ | |
| 414 | #define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ | |
| 415 | #define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ | |
| 416 | #define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ | |
| 417 | #define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ | |
| 418 | #define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ | |
| 419 | #define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ | |
| 420 | #define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ | |
| 421 | #define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ | |
| 422 | ||
| 423 | /* SIC_IMASK Masks */ | |
| 424 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | |
| 425 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | |
| 426 | #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ | |
| 427 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ | |
| 428 | ||
| 429 | /* SIC_IWR Masks */ | |
| 430 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | |
| 431 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | |
| 432 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ | |
| 433 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ | |
| 434 | ||
| 1394f032 BW |
435 | /* ***************************** UART CONTROLLER MASKS ********************** */ |
| 436 | ||
| 437 | /* UART_LCR Register */ | |
| 438 | ||
| 439 | #define DLAB 0x80 | |
| 440 | #define SB 0x40 | |
| 441 | #define STP 0x20 | |
| 442 | #define EPS 0x10 | |
| 443 | #define PEN 0x08 | |
| 444 | #define STB 0x04 | |
| 445 | #define WLS(x) ((x-5) & 0x03) | |
| 446 | ||
| 447 | #define DLAB_P 0x07 | |
| 448 | #define SB_P 0x06 | |
| 449 | #define STP_P 0x05 | |
| 450 | #define EPS_P 0x04 | |
| 451 | #define PEN_P 0x03 | |
| 452 | #define STB_P 0x02 | |
| 453 | #define WLS_P1 0x01 | |
| 454 | #define WLS_P0 0x00 | |
| 455 | ||
| 456 | /* UART_MCR Register */ | |
| 457 | #define LOOP_ENA 0x10 | |
| 458 | #define LOOP_ENA_P 0x04 | |
| 459 | ||
| 460 | /* UART_LSR Register */ | |
| 461 | #define TEMT 0x40 | |
| 462 | #define THRE 0x20 | |
| 463 | #define BI 0x10 | |
| 464 | #define FE 0x08 | |
| 465 | #define PE 0x04 | |
| 466 | #define OE 0x02 | |
| 467 | #define DR 0x01 | |
| 468 | ||
| 469 | #define TEMP_P 0x06 | |
| 470 | #define THRE_P 0x05 | |
| 471 | #define BI_P 0x04 | |
| 472 | #define FE_P 0x03 | |
| 473 | #define PE_P 0x02 | |
| 474 | #define OE_P 0x01 | |
| 475 | #define DR_P 0x00 | |
| 476 | ||
| 477 | /* UART_IER Register */ | |
| 478 | #define ELSI 0x04 | |
| 479 | #define ETBEI 0x02 | |
| 480 | #define ERBFI 0x01 | |
| 481 | ||
| 482 | #define ELSI_P 0x02 | |
| 483 | #define ETBEI_P 0x01 | |
| 484 | #define ERBFI_P 0x00 | |
| 485 | ||
| 486 | /* UART_IIR Register */ | |
| 487 | #define STATUS(x) ((x << 1) & 0x06) | |
| 488 | #define NINT 0x01 | |
| 489 | #define STATUS_P1 0x02 | |
| 490 | #define STATUS_P0 0x01 | |
| 491 | #define NINT_P 0x00 | |
| 492 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | |
| 493 | #define IIR_RX_READY 0x04 /* Receive data ready */ | |
| 494 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | |
| 495 | #define IIR_STATUS 0x06 | |
| 496 | ||
| 497 | /* UART_GCTL Register */ | |
| 498 | #define FFE 0x20 | |
| 499 | #define FPE 0x10 | |
| 500 | #define RPOLC 0x08 | |
| 501 | #define TPOLC 0x04 | |
| 502 | #define IREN 0x02 | |
| 503 | #define UCEN 0x01 | |
| 504 | ||
| 505 | #define FFE_P 0x05 | |
| 506 | #define FPE_P 0x04 | |
| 507 | #define RPOLC_P 0x03 | |
| 508 | #define TPOLC_P 0x02 | |
| 509 | #define IREN_P 0x01 | |
| 510 | #define UCEN_P 0x00 | |
| 511 | ||
| 1394f032 BW |
512 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ |
| 513 | ||
| 514 | /* PPI_CONTROL Masks */ | |
| 515 | #define PORT_EN 0x00000001 /* PPI Port Enable */ | |
| 516 | #define PORT_DIR 0x00000002 /* PPI Port Direction */ | |
| 517 | #define XFR_TYPE 0x0000000C /* PPI Transfer Type */ | |
| 518 | #define PORT_CFG 0x00000030 /* PPI Port Configuration */ | |
| 519 | #define FLD_SEL 0x00000040 /* PPI Active Field Select */ | |
| 520 | #define PACK_EN 0x00000080 /* PPI Packing Mode */ | |
| 521 | #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ | |
| 522 | #define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ | |
| 523 | #define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ | |
| 524 | #define DLENGTH 0x00003800 /* PPI Data Length */ | |
| 525 | #define DLEN_8 0x0000 /* Data Length = 8 Bits */ | |
| 526 | #define DLEN_10 0x0800 /* Data Length = 10 Bits */ | |
| 527 | #define DLEN_11 0x1000 /* Data Length = 11 Bits */ | |
| 528 | #define DLEN_12 0x1800 /* Data Length = 12 Bits */ | |
| 529 | #define DLEN_13 0x2000 /* Data Length = 13 Bits */ | |
| 530 | #define DLEN_14 0x2800 /* Data Length = 14 Bits */ | |
| 531 | #define DLEN_15 0x3000 /* Data Length = 15 Bits */ | |
| 532 | #define DLEN_16 0x3800 /* Data Length = 16 Bits */ | |
| 533 | #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ | |
| 534 | #define POL 0x0000C000 /* PPI Signal Polarities */ | |
| 19381f02 BW |
535 | #define POLC 0x4000 /* PPI Clock Polarity */ |
| 536 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ | |
| 1394f032 BW |
537 | |
| 538 | /* PPI_STATUS Masks */ | |
| 539 | #define FLD 0x00000400 /* Field Indicator */ | |
| 540 | #define FT_ERR 0x00000800 /* Frame Track Error */ | |
| 541 | #define OVR 0x00001000 /* FIFO Overflow Error */ | |
| 542 | #define UNDR 0x00002000 /* FIFO Underrun Error */ | |
| 543 | #define ERR_DET 0x00004000 /* Error Detected Indicator */ | |
| 544 | #define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ | |
| 545 | ||
| 546 | /* ********** DMA CONTROLLER MASKS *********************8 */ | |
| 547 | ||
| 00d24604 | 548 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ |
| 1394f032 BW |
549 | |
| 550 | #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ | |
| 551 | #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ | |
| 552 | #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ | |
| 553 | #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ | |
| 554 | #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ | |
| 555 | #define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ | |
| 556 | #define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ | |
| 557 | #define PMAP 0x00007000 /* DMA Peripheral Map Field */ | |
| 558 | ||
| 19381f02 BW |
559 | #define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ |
| 560 | #define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ | |
| 561 | #define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ | |
| 562 | #define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ | |
| 563 | #define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ | |
| 564 | #define PMAP_SPI 0x5000 /* PMAP SPI DMA */ | |
| 565 | #define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */ | |
| 566 | #define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */ | |
| 567 | ||
| 1394f032 BW |
568 | /* ************* GENERAL PURPOSE TIMER MASKS ******************** */ |
| 569 | ||
| 570 | /* PWM Timer bit definitions */ | |
| 571 | ||
| 572 | /* TIMER_ENABLE Register */ | |
| 573 | #define TIMEN0 0x0001 | |
| 574 | #define TIMEN1 0x0002 | |
| 575 | #define TIMEN2 0x0004 | |
| 576 | ||
| 577 | #define TIMEN0_P 0x00 | |
| 578 | #define TIMEN1_P 0x01 | |
| 579 | #define TIMEN2_P 0x02 | |
| 580 | ||
| 581 | /* TIMER_DISABLE Register */ | |
| 582 | #define TIMDIS0 0x0001 | |
| 583 | #define TIMDIS1 0x0002 | |
| 584 | #define TIMDIS2 0x0004 | |
| 585 | ||
| 586 | #define TIMDIS0_P 0x00 | |
| 587 | #define TIMDIS1_P 0x01 | |
| 588 | #define TIMDIS2_P 0x02 | |
| 589 | ||
| 590 | /* TIMER_STATUS Register */ | |
| 591 | #define TIMIL0 0x0001 | |
| 592 | #define TIMIL1 0x0002 | |
| 593 | #define TIMIL2 0x0004 | |
| 19381f02 BW |
594 | #define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ |
| 595 | #define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ | |
| 596 | #define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ | |
| 1394f032 BW |
597 | #define TRUN0 0x1000 |
| 598 | #define TRUN1 0x2000 | |
| 599 | #define TRUN2 0x4000 | |
| 600 | ||
| 601 | #define TIMIL0_P 0x00 | |
| 602 | #define TIMIL1_P 0x01 | |
| 603 | #define TIMIL2_P 0x02 | |
| 19381f02 BW |
604 | #define TOVF_ERR0_P 0x04 |
| 605 | #define TOVF_ERR1_P 0x05 | |
| 606 | #define TOVF_ERR2_P 0x06 | |
| 1394f032 BW |
607 | #define TRUN0_P 0x0C |
| 608 | #define TRUN1_P 0x0D | |
| 609 | #define TRUN2_P 0x0E | |
| 610 | ||
| 19381f02 BW |
611 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ |
| 612 | #define TOVL_ERR0 TOVF_ERR0 | |
| 613 | #define TOVL_ERR1 TOVF_ERR1 | |
| 614 | #define TOVL_ERR2 TOVF_ERR2 | |
| 615 | #define TOVL_ERR0_P TOVF_ERR0_P | |
| 616 | #define TOVL_ERR1_P TOVF_ERR1_P | |
| 617 | #define TOVL_ERR2_P TOVF_ERR2_P | |
| 618 | ||
| 1394f032 BW |
619 | /* TIMERx_CONFIG Registers */ |
| 620 | #define PWM_OUT 0x0001 | |
| 621 | #define WDTH_CAP 0x0002 | |
| 622 | #define EXT_CLK 0x0003 | |
| 623 | #define PULSE_HI 0x0004 | |
| 624 | #define PERIOD_CNT 0x0008 | |
| 625 | #define IRQ_ENA 0x0010 | |
| 626 | #define TIN_SEL 0x0020 | |
| 627 | #define OUT_DIS 0x0040 | |
| 628 | #define CLK_SEL 0x0080 | |
| 629 | #define TOGGLE_HI 0x0100 | |
| 630 | #define EMU_RUN 0x0200 | |
| 631 | #define ERR_TYP(x) ((x & 0x03) << 14) | |
| 632 | ||
| 633 | #define TMODE_P0 0x00 | |
| 634 | #define TMODE_P1 0x01 | |
| 635 | #define PULSE_HI_P 0x02 | |
| 636 | #define PERIOD_CNT_P 0x03 | |
| 637 | #define IRQ_ENA_P 0x04 | |
| 638 | #define TIN_SEL_P 0x05 | |
| 639 | #define OUT_DIS_P 0x06 | |
| 640 | #define CLK_SEL_P 0x07 | |
| 641 | #define TOGGLE_HI_P 0x08 | |
| 642 | #define EMU_RUN_P 0x09 | |
| 643 | #define ERR_TYP_P0 0x0E | |
| 644 | #define ERR_TYP_P1 0x0F | |
| 645 | ||
| 646 | /*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ | |
| 647 | ||
| 648 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ | |
| 649 | #define PF0 0x0001 | |
| 650 | #define PF1 0x0002 | |
| 651 | #define PF2 0x0004 | |
| 652 | #define PF3 0x0008 | |
| 653 | #define PF4 0x0010 | |
| 654 | #define PF5 0x0020 | |
| 655 | #define PF6 0x0040 | |
| 656 | #define PF7 0x0080 | |
| 657 | #define PF8 0x0100 | |
| 658 | #define PF9 0x0200 | |
| 659 | #define PF10 0x0400 | |
| 660 | #define PF11 0x0800 | |
| 661 | #define PF12 0x1000 | |
| 662 | #define PF13 0x2000 | |
| 663 | #define PF14 0x4000 | |
| 664 | #define PF15 0x8000 | |
| 665 | ||
| 666 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ | |
| 667 | #define PF0_P 0 | |
| 668 | #define PF1_P 1 | |
| 669 | #define PF2_P 2 | |
| 670 | #define PF3_P 3 | |
| 671 | #define PF4_P 4 | |
| 672 | #define PF5_P 5 | |
| 673 | #define PF6_P 6 | |
| 674 | #define PF7_P 7 | |
| 675 | #define PF8_P 8 | |
| 676 | #define PF9_P 9 | |
| 677 | #define PF10_P 10 | |
| 678 | #define PF11_P 11 | |
| 679 | #define PF12_P 12 | |
| 680 | #define PF13_P 13 | |
| 681 | #define PF14_P 14 | |
| 682 | #define PF15_P 15 | |
| 683 | ||
| 684 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ | |
| 685 | ||
| 686 | /* SPI_CTL Masks */ | |
| 687 | #define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ | |
| 19381f02 BW |
688 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ |
| 689 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ | |
| 690 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ | |
| 691 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ | |
| 1394f032 BW |
692 | #define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ |
| 693 | #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ | |
| 694 | #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ | |
| 695 | #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ | |
| dbcc78be | 696 | #define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ |
| 1394f032 BW |
697 | #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ |
| 698 | #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ | |
| 699 | #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ | |
| 700 | #define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ | |
| 701 | #define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ | |
| 702 | #define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ | |
| 703 | ||
| 704 | /* SPI_FLG Masks */ | |
| 705 | #define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
| 706 | #define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
| 707 | #define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
| 708 | #define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
| 709 | #define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
| 710 | #define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
| 711 | #define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
| 712 | #define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
| 713 | #define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
| 714 | #define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
| 715 | #define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
| 716 | #define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
| 717 | #define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
| 718 | #define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
| 719 | ||
| 720 | /* SPI_FLG Bit Positions */ | |
| 721 | #define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
| 722 | #define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
| 723 | #define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
| 724 | #define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
| 725 | #define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
| 726 | #define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
| 727 | #define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
| 728 | #define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
| 729 | #define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
| 730 | #define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
| 731 | #define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
| 732 | #define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
| 733 | #define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
| 734 | #define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
| 735 | ||
| 736 | /* SPI_STAT Masks */ | |
| 737 | #define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ | |
| 738 | #define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ | |
| 739 | #define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ | |
| 740 | #define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ | |
| 741 | #define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ | |
| 742 | #define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ | |
| 743 | #define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ | |
| 744 | ||
| 19381f02 BW |
745 | /* SPIx_FLG Masks */ |
| 746 | #define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */ | |
| 747 | #define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */ | |
| 748 | #define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */ | |
| 749 | #define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */ | |
| 750 | #define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */ | |
| 751 | #define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */ | |
| 752 | #define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */ | |
| 753 | ||
| 1394f032 BW |
754 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ |
| 755 | ||
| 756 | /* AMGCTL Masks */ | |
| 757 | #define AMCKEN 0x00000001 /* Enable CLKOUT */ | |
| 19381f02 | 758 | #define AMBEN_NONE 0x00000000 /* All Banks Disabled */ |
| 1394f032 BW |
759 | #define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ |
| 760 | #define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ | |
| 761 | #define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ | |
| 762 | #define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ | |
| 763 | ||
| 764 | /* AMGCTL Bit Positions */ | |
| 765 | #define AMCKEN_P 0x00000000 /* Enable CLKOUT */ | |
| 766 | #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ | |
| 767 | #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ | |
| 768 | #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ | |
| 769 | ||
| 770 | /* AMBCTL0 Masks */ | |
| 771 | #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ | |
| 772 | #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ | |
| 773 | #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ | |
| 774 | #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ | |
| 775 | #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ | |
| 776 | #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ | |
| 777 | #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ | |
| 778 | #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ | |
| 779 | #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ | |
| 780 | #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ | |
| 781 | #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ | |
| 782 | #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ | |
| 783 | #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ | |
| 784 | #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ | |
| 785 | #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ | |
| 786 | #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ | |
| 787 | #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ | |
| 788 | #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ | |
| 789 | #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ | |
| 790 | #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ | |
| 791 | #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ | |
| 792 | #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ | |
| 793 | #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ | |
| 794 | #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ | |
| 795 | #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ | |
| 796 | #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ | |
| 797 | #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ | |
| 798 | #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ | |
| 799 | #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ | |
| 800 | #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ | |
| 801 | #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ | |
| 802 | #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ | |
| 803 | #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ | |
| 804 | #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ | |
| 805 | #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ | |
| 806 | #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ | |
| 807 | #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ | |
| 808 | #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ | |
| 809 | #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ | |
| 810 | #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ | |
| 811 | #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ | |
| 812 | #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ | |
| 813 | #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ | |
| 814 | #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ | |
| 815 | #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ | |
| 816 | #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ | |
| 817 | #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ | |
| 818 | #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ | |
| 819 | #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ | |
| 820 | #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ | |
| 821 | #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | |
| 822 | #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | |
| 823 | #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | |
| 824 | #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | |
| 825 | #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | |
| 826 | #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | |
| 827 | #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | |
| 828 | #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | |
| 829 | #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ | |
| 830 | #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ | |
| 831 | #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ | |
| 832 | #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ | |
| 833 | #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ | |
| 834 | #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ | |
| 835 | #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ | |
| 836 | #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ | |
| 837 | #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ | |
| 838 | #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ | |
| 839 | #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ | |
| 840 | #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ | |
| 841 | #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ | |
| 842 | #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ | |
| 843 | #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ | |
| 844 | #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ | |
| 845 | #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ | |
| 846 | #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ | |
| 847 | #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ | |
| 848 | #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ | |
| 849 | #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ | |
| 850 | #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ | |
| 851 | #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ | |
| 852 | #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ | |
| 853 | #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ | |
| 854 | #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ | |
| 855 | #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ | |
| 856 | #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ | |
| 857 | #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ | |
| 858 | #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ | |
| 859 | ||
| 860 | /* AMBCTL1 Masks */ | |
| 861 | #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ | |
| 862 | #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ | |
| 863 | #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ | |
| 864 | #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ | |
| 865 | #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ | |
| 866 | #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ | |
| 867 | #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | |
| 868 | #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | |
| 869 | #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | |
| 870 | #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | |
| 871 | #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | |
| 872 | #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | |
| 873 | #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | |
| 874 | #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | |
| 875 | #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ | |
| 876 | #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ | |
| 877 | #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ | |
| 878 | #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ | |
| 879 | #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ | |
| 880 | #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ | |
| 881 | #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ | |
| 882 | #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ | |
| 883 | #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ | |
| 884 | #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ | |
| 885 | #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ | |
| 886 | #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ | |
| 887 | #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ | |
| 888 | #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ | |
| 889 | #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ | |
| 890 | #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ | |
| 891 | #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ | |
| 892 | #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ | |
| 893 | #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ | |
| 894 | #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ | |
| 895 | #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ | |
| 896 | #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ | |
| 897 | #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ | |
| 898 | #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ | |
| 899 | #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ | |
| 900 | #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ | |
| 901 | #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ | |
| 902 | #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ | |
| 903 | #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ | |
| 904 | #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ | |
| 905 | #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ | |
| 906 | #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ | |
| 907 | #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ | |
| 908 | #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ | |
| 909 | #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ | |
| 910 | #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ | |
| 911 | #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | |
| 912 | #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | |
| 913 | #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | |
| 914 | #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | |
| 915 | #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | |
| 916 | #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | |
| 917 | #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | |
| 918 | #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | |
| 919 | #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ | |
| 920 | #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ | |
| 921 | #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ | |
| 922 | #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ | |
| 923 | #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ | |
| 924 | #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ | |
| 925 | #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ | |
| 926 | #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ | |
| 927 | #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ | |
| 928 | #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ | |
| 929 | #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ | |
| 930 | #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ | |
| 931 | #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ | |
| 932 | #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ | |
| 933 | #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ | |
| 934 | #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ | |
| 935 | #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ | |
| 936 | #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ | |
| 937 | #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ | |
| 938 | #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ | |
| 939 | #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ | |
| 940 | #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ | |
| 941 | #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ | |
| 942 | #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ | |
| 943 | #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ | |
| 944 | #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ | |
| 945 | #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ | |
| 946 | #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ | |
| 947 | #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ | |
| 948 | #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ | |
| 949 | ||
| 950 | /* ********************** SDRAM CONTROLLER MASKS *************************** */ | |
| 951 | ||
| 952 | /* SDGCTL Masks */ | |
| 953 | #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ | |
| 954 | #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ | |
| 955 | #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ | |
| 956 | #define PFE 0x00000010 /* Enable SDRAM prefetch */ | |
| 957 | #define PFP 0x00000020 /* Prefetch has priority over AMC requests */ | |
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958 | #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ |
| 959 | #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ | |
| 960 | #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ | |
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961 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ |
| 962 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | |
| 963 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | |
| 964 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | |
| 965 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | |
| 966 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | |
| 967 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | |
| 968 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | |
| 969 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | |
| 970 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | |
| 971 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | |
| 972 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | |
| 973 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | |
| 974 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | |
| 975 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | |
| 976 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | |
| 977 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | |
| 978 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | |
| 979 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | |
| 980 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | |
| 981 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | |
| 982 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | |
| 983 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | |
| 984 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | |
| 985 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | |
| 986 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | |
| 987 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | |
| 988 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | |
| 989 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | |
| 990 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | |
| 991 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | |
| 992 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | |
| 993 | #define PUPSD 0x00200000 /*Power-up start delay */ | |
| 994 | #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ | |
| 995 | #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ | |
| 996 | #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ | |
| 997 | #define EBUFE 0x02000000 /* Enable external buffering timing */ | |
| 998 | #define FBBRW 0x04000000 /* Fast back-to-back read write enable */ | |
| 999 | #define EMREN 0x10000000 /* Extended mode register enable */ | |
| 1000 | #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ | |
| 1001 | #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ | |
| 1002 | ||
| 1003 | /* EBIU_SDBCTL Masks */ | |
| 1004 | #define EBE 0x00000001 /* Enable SDRAM external bank */ | |
| 1005 | #define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | |
| 1006 | #define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ | |
| 1007 | #define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ | |
| 1008 | #define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ | |
| 1009 | #define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | |
| 1010 | #define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ | |
| 1011 | #define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ | |
| 1012 | #define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ | |
| 1013 | ||
| 1014 | /* EBIU_SDSTAT Masks */ | |
| 1015 | #define SDCI 0x00000001 /* SDRAM controller is idle */ | |
| 1016 | #define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ | |
| 1017 | #define SDPUA 0x00000004 /* SDRAM power up active */ | |
| 1018 | #define SDRS 0x00000008 /* SDRAM is in reset state */ | |
| 1019 | #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ | |
| 1020 | #define BGSTAT 0x00000020 /* Bus granted */ | |
| 1021 | ||
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1022 | |
| 1023 | #endif /* _DEF_BF532_H */ |