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Blackfin: bf537-stamp: add example AD2S120x resources
[net-next-2.6.git] / arch / blackfin / mach-bf527 / boards / cm_bf527.c
CommitLineData
9db144fe 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
9db144fe 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
9db144fe
MH		 8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/etherdevice.h>
9db144fe
MH		 18#include <linux/i2c.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
9db144fe 21#include <linux/usb/musb.h>
9db144fe
MH		 22#include <asm/dma.h>
23#include <asm/bfin5xx_spi.h>
24#include <asm/reboot.h>
25#include <asm/nand.h>
26#include <asm/portmux.h>
27#include <asm/dpmc.h>
28#include <linux/spi/ad7877.h>
29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
33const char bfin_board_name[] = "Bluetechnix CM-BF527";
34
35/*
36 * Driver needs to know address, irq and flag pin.
37 */
38
9db144fe 39#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 40#include <linux/usb/isp1760.h>
41static struct resource bfin_isp1760_resources[] = {
9db144fe 42 [0] = {
3f375690
MH		 43 .start = 0x203C0000,
44 .end = 0x203C0000 + 0x000fffff,
9db144fe
MH		 45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
3f375690
MH		 48 .start = IRQ_PF7,
49 .end = IRQ_PF7,
9db144fe
MH		 50 .flags = IORESOURCE_IRQ,
51 },
52};
53
3f375690
MH		 54static struct isp1760_platform_data isp1760_priv = {
55 .is_isp1761 = 0,
3f375690
MH		 56 .bus_width_16 = 1,
57 .port1_otg = 0,
58 .analog_oc = 0,
59 .dack_polarity_high = 0,
60 .dreq_polarity_high = 0,
9db144fe
MH		 61};
62
3f375690 63static struct platform_device bfin_isp1760_device = {
c6feb768 64 .name = "isp1760",
3f375690
MH		 65 .id = 0,
66 .dev = {
67 .platform_data = &isp1760_priv,
68 },
69 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
70 .resource = bfin_isp1760_resources,
9db144fe 71};
9db144fe
MH		 72#endif
73
74#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
75static struct resource musb_resources[] = {
76 [0] = {
77 .start = 0xffc03800,
78 .end = 0xffc03cff,
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = { /* general IRQ */
82 .start = IRQ_USB_INT0,
83 .end = IRQ_USB_INT0,
84 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
85 },
86 [2] = { /* DMA IRQ */
87 .start = IRQ_USB_DMA,
88 .end = IRQ_USB_DMA,
89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
90 },
91};
92
50041acb
BW		 93static struct musb_hdrc_config musb_config = {
94 .multipoint = 0,
95 .dyn_fifo = 0,
96 .soft_con = 1,
97 .dma = 1,
fea05dac
BW		 98 .num_eps = 8,
99 .dma_channels = 8,
50041acb
BW		 100 .gpio_vrsel = GPIO_PF11,
101};
102
9db144fe
MH		 103static struct musb_hdrc_platform_data musb_plat = {
104#if defined(CONFIG_USB_MUSB_OTG)
105 .mode = MUSB_OTG,
106#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
107 .mode = MUSB_HOST,
108#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
109 .mode = MUSB_PERIPHERAL,
110#endif
50041acb 111 .config = &musb_config,
9db144fe
MH		 112};
113
114static u64 musb_dmamask = ~(u32)0;
115
116static struct platform_device musb_device = {
117 .name = "musb_hdrc",
118 .id = 0,
119 .dev = {
120 .dma_mask = &musb_dmamask,
121 .coherent_dma_mask = 0xffffffff,
122 .platform_data = &musb_plat,
123 },
124 .num_resources = ARRAY_SIZE(musb_resources),
125 .resource = musb_resources,
126};
127#endif
128
9db144fe
MH		 129#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
130static struct mtd_partition partition_info[] = {
131 {
aa582977 132 .name = "linux kernel(nand)",
9db144fe 133 .offset = 0,
f4585a08 134 .size = 4 * 1024 * 1024,
9db144fe
MH		 135 },
136 {
aa582977 137 .name = "file system(nand)",
9db144fe
MH		 138 .offset = MTDPART_OFS_APPEND,
139 .size = MTDPART_SIZ_FULL,
140 },
141};
142
143static struct bf5xx_nand_platform bf5xx_nand_platform = {
144 .page_size = NFC_PG_SIZE_256,
145 .data_width = NFC_NWIDTH_8,
146 .partitions = partition_info,
147 .nr_partitions = ARRAY_SIZE(partition_info),
148 .rd_dly = 3,
149 .wr_dly = 3,
150};
151
152static struct resource bf5xx_nand_resources[] = {
153 {
154 .start = NFC_CTL,
155 .end = NFC_DATA_RD + 2,
156 .flags = IORESOURCE_MEM,
157 },
158 {
159 .start = CH_NFC,
160 .end = CH_NFC,
161 .flags = IORESOURCE_IRQ,
162 },
163};
164
165static struct platform_device bf5xx_nand_device = {
166 .name = "bf5xx-nand",
167 .id = 0,
168 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
169 .resource = bf5xx_nand_resources,
170 .dev = {
171 .platform_data = &bf5xx_nand_platform,
172 },
173};
174#endif
175
176#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
177static struct resource bfin_pcmcia_cf_resources[] = {
178 {
179 .start = 0x20310000, /* IO PORT */
180 .end = 0x20312000,
181 .flags = IORESOURCE_MEM,
182 }, {
183 .start = 0x20311000, /* Attribute Memory */
184 .end = 0x20311FFF,
185 .flags = IORESOURCE_MEM,
186 }, {
187 .start = IRQ_PF4,
188 .end = IRQ_PF4,
189 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
190 }, {
191 .start = 6, /* Card Detect PF6 */
192 .end = 6,
193 .flags = IORESOURCE_IRQ,
194 },
195};
196
197static struct platform_device bfin_pcmcia_cf_device = {
198 .name = "bfin_cf_pcmcia",
199 .id = -1,
200 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
201 .resource = bfin_pcmcia_cf_resources,
202};
203#endif
204
205#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
206static struct platform_device rtc_device = {
207 .name = "rtc-bfin",
208 .id = -1,
209};
210#endif
211
212#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 213#include <linux/smc91x.h>
214
215static struct smc91x_platdata smc91x_info = {
216 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
217 .leda = RPC_LED_100_10,
218 .ledb = RPC_LED_TX_RX,
219};
220
9db144fe
MH		 221static struct resource smc91x_resources[] = {
222 {
223 .name = "smc91x-regs",
224 .start = 0x20300300,
225 .end = 0x20300300 + 16,
226 .flags = IORESOURCE_MEM,
227 }, {
228
229 .start = IRQ_PF7,
230 .end = IRQ_PF7,
231 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
232 },
233};
234static struct platform_device smc91x_device = {
235 .name = "smc91x",
236 .id = 0,
237 .num_resources = ARRAY_SIZE(smc91x_resources),
238 .resource = smc91x_resources,
61f09b5a
MH		 239 .dev = {
240 .platform_data = &smc91x_info,
241 },
9db144fe
MH		 242};
243#endif
244
245#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
246static struct resource dm9000_resources[] = {
247 [0] = {
248 .start = 0x203FB800,
b3dec4a4 249 .end = 0x203FB800 + 1,
9db144fe
MH		 250 .flags = IORESOURCE_MEM,
251 },
252 [1] = {
b3dec4a4
BS		 253 .start = 0x203FB804,
254 .end = 0x203FB804 + 1,
255 .flags = IORESOURCE_MEM,
256 },
257 [2] = {
9db144fe
MH		 258 .start = IRQ_PF9,
259 .end = IRQ_PF9,
260 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
261 },
262};
263
264static struct platform_device dm9000_device = {
265 .name = "dm9000",
266 .id = -1,
267 .num_resources = ARRAY_SIZE(dm9000_resources),
268 .resource = dm9000_resources,
269};
270#endif
271
9db144fe 272#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 273static struct platform_device bfin_mii_bus = {
274 .name = "bfin_mii_bus",
275};
276
9db144fe
MH		 277static struct platform_device bfin_mac_device = {
278 .name = "bfin_mac",
65319628 279 .dev.platform_data = &bfin_mii_bus,
9db144fe
MH		 280};
281#endif
282
283#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
284static struct resource net2272_bfin_resources[] = {
285 {
286 .start = 0x20300000,
287 .end = 0x20300000 + 0x100,
288 .flags = IORESOURCE_MEM,
289 }, {
290 .start = IRQ_PF7,
291 .end = IRQ_PF7,
292 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
293 },
294};
295
296static struct platform_device net2272_bfin_device = {
297 .name = "net2272",
298 .id = -1,
299 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
300 .resource = net2272_bfin_resources,
301};
302#endif
303
304#if defined(CONFIG_MTD_M25P80) \
305 || defined(CONFIG_MTD_M25P80_MODULE)
306static struct mtd_partition bfin_spi_flash_partitions[] = {
307 {
aa582977 308 .name = "bootloader(spi)",
9db144fe
MH		 309 .size = 0x00040000,
310 .offset = 0,
311 .mask_flags = MTD_CAP_ROM
312 }, {
aa582977 313 .name = "linux kernel(spi)",
9db144fe
MH		 314 .size = MTDPART_SIZ_FULL,
315 .offset = MTDPART_OFS_APPEND,
316 }
317};
318
319static struct flash_platform_data bfin_spi_flash_data = {
320 .name = "m25p80",
321 .parts = bfin_spi_flash_partitions,
322 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
323 .type = "m25p16",
324};
325
326/* SPI flash chip (m25p64) */
327static struct bfin5xx_spi_chip spi_flash_chip_info = {
328 .enable_dma = 0, /* use dma transfer with this chip*/
329 .bits_per_word = 8,
330};
331#endif
332
a261eec0
MF		 333#if defined(CONFIG_BFIN_SPI_ADC) \
334 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
9db144fe
MH		 335/* SPI ADC chip */
336static struct bfin5xx_spi_chip spi_adc_chip_info = {
337 .enable_dma = 1, /* use dma transfer with this chip*/
338 .bits_per_word = 16,
339};
340#endif
341
342#if defined(CONFIG_SND_BLACKFIN_AD1836) \
343 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
344static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
345 .enable_dma = 0,
346 .bits_per_word = 16,
347};
348#endif
349
f3f704d3
MH		 350#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
351static struct bfin5xx_spi_chip mmc_spi_chip_info = {
352 .enable_dma = 0,
9db144fe
MH		 353 .bits_per_word = 8,
354};
355#endif
356
9db144fe
MH		 357#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
358static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
359 .enable_dma = 0,
360 .bits_per_word = 16,
361};
362
363static const struct ad7877_platform_data bfin_ad7877_ts_info = {
364 .model = 7877,
365 .vref_delay_usecs = 50, /* internal, no capacitor */
366 .x_plate_ohms = 419,
367 .y_plate_ohms = 486,
368 .pressure_max = 1000,
369 .pressure_min = 0,
370 .stopacq_polarity = 1,
371 .first_conversion_delay = 3,
372 .acquisition_time = 1,
373 .averaging = 1,
374 .pen_down_acc_interval = 1,
375};
376#endif
377
378#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
379 && defined(CONFIG_SND_SOC_WM8731_SPI)
380static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
381 .enable_dma = 0,
382 .bits_per_word = 16,
383};
384#endif
385
386#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
387static struct bfin5xx_spi_chip spidev_chip_info = {
388 .enable_dma = 0,
389 .bits_per_word = 8,
390};
391#endif
392
393static struct spi_board_info bfin_spi_board_info[] __initdata = {
394#if defined(CONFIG_MTD_M25P80) \
395 || defined(CONFIG_MTD_M25P80_MODULE)
396 {
397 /* the modalias must be the same as spi device driver name */
398 .modalias = "m25p80", /* Name of spi_driver for this device */
399 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
400 .bus_num = 0, /* Framework bus number */
401 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
402 .platform_data = &bfin_spi_flash_data,
403 .controller_data = &spi_flash_chip_info,
404 .mode = SPI_MODE_3,
405 },
406#endif
407
a261eec0
MF		 408#if defined(CONFIG_BFIN_SPI_ADC) \
409 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
9db144fe
MH		 410 {
411 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
412 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
413 .bus_num = 0, /* Framework bus number */
414 .chip_select = 1, /* Framework chip select. */
415 .platform_data = NULL, /* No spi_driver specific config */
416 .controller_data = &spi_adc_chip_info,
417 },
418#endif
419
420#if defined(CONFIG_SND_BLACKFIN_AD1836) \
421 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
422 {
dac98174 423 .modalias = "ad1836",
9db144fe
MH		 424 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
425 .bus_num = 0,
426 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
427 .controller_data = &ad1836_spi_chip_info,
428 },
429#endif
f3f704d3 430#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
9db144fe 431 {
f3f704d3
MH		 432 .modalias = "mmc_spi",
433 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
9db144fe 434 .bus_num = 0,
f3f704d3
MH		 435 .chip_select = 5,
436 .controller_data = &mmc_spi_chip_info,
9db144fe
MH		 437 .mode = SPI_MODE_3,
438 },
439#endif
9db144fe
MH		 440#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
441 {
442 .modalias = "ad7877",
443 .platform_data = &bfin_ad7877_ts_info,
444 .irq = IRQ_PF8,
445 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
446 .bus_num = 0,
447 .chip_select = 2,
448 .controller_data = &spi_ad7877_chip_info,
449 },
450#endif
451#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
452 && defined(CONFIG_SND_SOC_WM8731_SPI)
453 {
454 .modalias = "wm8731",
455 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
456 .bus_num = 0,
457 .chip_select = 5,
458 .controller_data = &spi_wm8731_chip_info,
459 .mode = SPI_MODE_0,
460 },
461#endif
462#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
463 {
464 .modalias = "spidev",
465 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
466 .bus_num = 0,
467 .chip_select = 1,
468 .controller_data = &spidev_chip_info,
469 },
470#endif
471};
472
473#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
474/* SPI controller data */
475static struct bfin5xx_spi_master bfin_spi0_info = {
476 .num_chipselect = 8,
477 .enable_dma = 1, /* master has the ability to do dma transfer */
478 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
479};
480
481/* SPI (0) */
482static struct resource bfin_spi0_resource[] = {
483 [0] = {
484 .start = SPI0_REGBASE,
485 .end = SPI0_REGBASE + 0xFF,
486 .flags = IORESOURCE_MEM,
487 },
488 [1] = {
489 .start = CH_SPI,
490 .end = CH_SPI,
53122693
YL		 491 .flags = IORESOURCE_DMA,
492 },
493 [2] = {
494 .start = IRQ_SPI,
495 .end = IRQ_SPI,
9db144fe
MH		 496 .flags = IORESOURCE_IRQ,
497 },
498};
499
500static struct platform_device bfin_spi0_device = {
501 .name = "bfin-spi",
502 .id = 0, /* Bus number */
503 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
504 .resource = bfin_spi0_resource,
505 .dev = {
506 .platform_data = &bfin_spi0_info, /* Passed to driver */
507 },
508};
509#endif /* spi master and devices */
510
9c21453e
HK		 511#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
512static struct mtd_partition cm_partitions[] = {
513 {
514 .name = "bootloader(nor)",
515 .size = 0x40000,
516 .offset = 0,
517 }, {
518 .name = "linux kernel(nor)",
519 .size = 0x100000,
520 .offset = MTDPART_OFS_APPEND,
521 }, {
522 .name = "file system(nor)",
523 .size = MTDPART_SIZ_FULL,
524 .offset = MTDPART_OFS_APPEND,
525 }
526};
527
528static struct physmap_flash_data cm_flash_data = {
529 .width = 2,
530 .parts = cm_partitions,
531 .nr_parts = ARRAY_SIZE(cm_partitions),
532};
533
534static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 };
535
536static struct resource cm_flash_resource[] = {
537 {
538 .name = "cfi_probe",
539 .start = 0x20000000,
540 .end = 0x201fffff,
541 .flags = IORESOURCE_MEM,
542 }, {
543 .start = (unsigned long)cm_flash_gpios,
544 .end = ARRAY_SIZE(cm_flash_gpios),
545 .flags = IORESOURCE_IRQ,
546 }
547};
548
549static struct platform_device cm_flash_device = {
550 .name = "gpio-addr-flash",
551 .id = 0,
552 .dev = {
553 .platform_data = &cm_flash_data,
554 },
555 .num_resources = ARRAY_SIZE(cm_flash_resource),
556 .resource = cm_flash_resource,
557};
558#endif
559
9db144fe 560#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
9db144fe 561#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 562static struct resource bfin_uart0_resources[] = {
9db144fe 563 {
6bd1fbea
SZ		 564 .start = UART0_THR,
565 .end = UART0_GCTL+2,
9db144fe
MH		 566 .flags = IORESOURCE_MEM,
567 },
6bd1fbea
SZ		 568 {
569 .start = IRQ_UART0_RX,
570 .end = IRQ_UART0_RX+1,
571 .flags = IORESOURCE_IRQ,
572 },
573 {
574 .start = IRQ_UART0_ERROR,
575 .end = IRQ_UART0_ERROR,
576 .flags = IORESOURCE_IRQ,
577 },
578 {
579 .start = CH_UART0_TX,
580 .end = CH_UART0_TX,
581 .flags = IORESOURCE_DMA,
582 },
583 {
584 .start = CH_UART0_RX,
585 .end = CH_UART0_RX,
586 .flags = IORESOURCE_DMA,
587 },
588};
589
590unsigned short bfin_uart0_peripherals[] = {
591 P_UART0_TX, P_UART0_RX, 0
592};
593
594static struct platform_device bfin_uart0_device = {
595 .name = "bfin-uart",
596 .id = 0,
597 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
598 .resource = bfin_uart0_resources,
599 .dev = {
600 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
601 },
602};
9db144fe
MH		 603#endif
604#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 605static struct resource bfin_uart1_resources[] = {
9db144fe 606 {
6bd1fbea
SZ		 607 .start = UART1_THR,
608 .end = UART1_GCTL+2,
9db144fe
MH		 609 .flags = IORESOURCE_MEM,
610 },
6bd1fbea
SZ		 611 {
612 .start = IRQ_UART1_RX,
613 .end = IRQ_UART1_RX+1,
614 .flags = IORESOURCE_IRQ,
615 },
616 {
617 .start = IRQ_UART1_ERROR,
618 .end = IRQ_UART1_ERROR,
619 .flags = IORESOURCE_IRQ,
620 },
621 {
622 .start = CH_UART1_TX,
623 .end = CH_UART1_TX,
624 .flags = IORESOURCE_DMA,
625 },
626 {
627 .start = CH_UART1_RX,
628 .end = CH_UART1_RX,
629 .flags = IORESOURCE_DMA,
630 },
631#ifdef CONFIG_BFIN_UART1_CTSRTS
632 { /* CTS pin */
633 .start = GPIO_PF9,
634 .end = GPIO_PF9,
635 .flags = IORESOURCE_IO,
636 },
637 { /* RTS pin */
638 .start = GPIO_PF10,
639 .end = GPIO_PF10,
640 .flags = IORESOURCE_IO,
641 },
9db144fe
MH		 642#endif
643};
644
6bd1fbea
SZ		 645unsigned short bfin_uart1_peripherals[] = {
646 P_UART1_TX, P_UART1_RX, 0
647};
648
649static struct platform_device bfin_uart1_device = {
9db144fe
MH		 650 .name = "bfin-uart",
651 .id = 1,
6bd1fbea
SZ		 652 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
653 .resource = bfin_uart1_resources,
654 .dev = {
655 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
656 },
9db144fe
MH		 657};
658#endif
6bd1fbea 659#endif
9db144fe
MH		 660
661#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
9db144fe 662#ifdef CONFIG_BFIN_SIR0
42bd8bcb 663static struct resource bfin_sir0_resources[] = {
9db144fe
MH		 664 {
665 .start = 0xFFC00400,
666 .end = 0xFFC004FF,
667 .flags = IORESOURCE_MEM,
668 },
42bd8bcb
GY		 669 {
670 .start = IRQ_UART0_RX,
671 .end = IRQ_UART0_RX+1,
672 .flags = IORESOURCE_IRQ,
673 },
674 {
675 .start = CH_UART0_RX,
676 .end = CH_UART0_RX+1,
677 .flags = IORESOURCE_DMA,
678 },
679};
680
681static struct platform_device bfin_sir0_device = {
682 .name = "bfin_sir",
683 .id = 0,
684 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
685 .resource = bfin_sir0_resources,
686};
9db144fe
MH		 687#endif
688#ifdef CONFIG_BFIN_SIR1
42bd8bcb 689static struct resource bfin_sir1_resources[] = {
9db144fe
MH		 690 {
691 .start = 0xFFC02000,
692 .end = 0xFFC020FF,
693 .flags = IORESOURCE_MEM,
694 },
42bd8bcb
GY		 695 {
696 .start = IRQ_UART1_RX,
697 .end = IRQ_UART1_RX+1,
698 .flags = IORESOURCE_IRQ,
699 },
700 {
701 .start = CH_UART1_RX,
702 .end = CH_UART1_RX+1,
703 .flags = IORESOURCE_DMA,
704 },
9db144fe
MH		 705};
706
42bd8bcb 707static struct platform_device bfin_sir1_device = {
9db144fe 708 .name = "bfin_sir",
42bd8bcb
GY		 709 .id = 1,
710 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
711 .resource = bfin_sir1_resources,
9db144fe
MH		 712};
713#endif
42bd8bcb 714#endif
9db144fe
MH		 715
716#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
717static struct resource bfin_twi0_resource[] = {
718 [0] = {
719 .start = TWI0_REGBASE,
720 .end = TWI0_REGBASE,
721 .flags = IORESOURCE_MEM,
722 },
723 [1] = {
724 .start = IRQ_TWI,
725 .end = IRQ_TWI,
726 .flags = IORESOURCE_IRQ,
727 },
728};
729
730static struct platform_device i2c_bfin_twi_device = {
731 .name = "i2c-bfin-twi",
732 .id = 0,
733 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
734 .resource = bfin_twi0_resource,
735};
736#endif
737
9db144fe 738static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
ebd58333 739#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
9db144fe
MH		 740 {
741 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
9db144fe
MH		 742 },
743#endif
204844eb 744#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
9db144fe
MH		 745 {
746 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
9db144fe
MH		 747 .irq = IRQ_PF8,
748 },
749#endif
50c4c086
MH		 750#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
751 {
752 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
753 },
754#endif
9db144fe 755};
9db144fe
MH		 756
757#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 758#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
759static struct resource bfin_sport0_uart_resources[] = {
760 {
761 .start = SPORT0_TCR1,
762 .end = SPORT0_MRCS3+4,
763 .flags = IORESOURCE_MEM,
764 },
765 {
766 .start = IRQ_SPORT0_RX,
767 .end = IRQ_SPORT0_RX+1,
768 .flags = IORESOURCE_IRQ,
769 },
770 {
771 .start = IRQ_SPORT0_ERROR,
772 .end = IRQ_SPORT0_ERROR,
773 .flags = IORESOURCE_IRQ,
774 },
775};
776
777unsigned short bfin_sport0_peripherals[] = {
778 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
779 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
780};
781
9db144fe
MH		 782static struct platform_device bfin_sport0_uart_device = {
783 .name = "bfin-sport-uart",
784 .id = 0,
df5de261
SZ		 785 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
786 .resource = bfin_sport0_uart_resources,
787 .dev = {
788 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
789 },
790};
791#endif
792#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
793static struct resource bfin_sport1_uart_resources[] = {
794 {
795 .start = SPORT1_TCR1,
796 .end = SPORT1_MRCS3+4,
797 .flags = IORESOURCE_MEM,
798 },
799 {
800 .start = IRQ_SPORT1_RX,
801 .end = IRQ_SPORT1_RX+1,
802 .flags = IORESOURCE_IRQ,
803 },
804 {
805 .start = IRQ_SPORT1_ERROR,
806 .end = IRQ_SPORT1_ERROR,
807 .flags = IORESOURCE_IRQ,
808 },
809};
810
811unsigned short bfin_sport1_peripherals[] = {
812 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
813 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
9db144fe
MH		 814};
815
816static struct platform_device bfin_sport1_uart_device = {
817 .name = "bfin-sport-uart",
818 .id = 1,
df5de261
SZ		 819 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
820 .resource = bfin_sport1_uart_resources,
821 .dev = {
822 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
823 },
9db144fe
MH		 824};
825#endif
df5de261 826#endif
9db144fe 827
9db144fe
MH		 828#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
829#include <linux/input.h>
830#include <linux/gpio_keys.h>
831
832static struct gpio_keys_button bfin_gpio_keys_table[] = {
833 {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"},
834};
835
836static struct gpio_keys_platform_data bfin_gpio_keys_data = {
837 .buttons = bfin_gpio_keys_table,
838 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
839};
840
841static struct platform_device bfin_device_gpiokeys = {
842 .name = "gpio-keys",
843 .dev = {
844 .platform_data = &bfin_gpio_keys_data,
845 },
846};
847#endif
848
9db144fe
MH		 849static const unsigned int cclk_vlev_datasheet[] =
850{
851 VRPAIR(VLEV_100, 400000000),
852 VRPAIR(VLEV_105, 426000000),
853 VRPAIR(VLEV_110, 500000000),
854 VRPAIR(VLEV_115, 533000000),
855 VRPAIR(VLEV_120, 600000000),
856};
857
858static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
859 .tuple_tab = cclk_vlev_datasheet,
860 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
861 .vr_settling_time = 25 /* us */,
862};
863
864static struct platform_device bfin_dpmc = {
865 .name = "bfin dpmc",
866 .dev = {
867 .platform_data = &bfin_dmpc_vreg_data,
868 },
869};
870
9c21453e 871static struct platform_device *cmbf527_devices[] __initdata = {
9db144fe
MH		 872
873 &bfin_dpmc,
874
875#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
876 &bf5xx_nand_device,
877#endif
878
879#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
880 &bfin_pcmcia_cf_device,
881#endif
882
883#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
884 &rtc_device,
885#endif
886
3f375690
MH		 887#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
888 &bfin_isp1760_device,
889#endif
890
9db144fe
MH		 891#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
892 &musb_device,
893#endif
894
895#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
896 &smc91x_device,
897#endif
898
899#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
900 &dm9000_device,
901#endif
902
903#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 904 &bfin_mii_bus,
9db144fe
MH		 905 &bfin_mac_device,
906#endif
907
908#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
909 &net2272_bfin_device,
910#endif
911
912#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
913 &bfin_spi0_device,
914#endif
915
9db144fe 916#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 917#ifdef CONFIG_SERIAL_BFIN_UART0
918 &bfin_uart0_device,
919#endif
920#ifdef CONFIG_SERIAL_BFIN_UART1
921 &bfin_uart1_device,
922#endif
9db144fe
MH		 923#endif
924
925#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 926#ifdef CONFIG_BFIN_SIR0
927 &bfin_sir0_device,
928#endif
929#ifdef CONFIG_BFIN_SIR1
930 &bfin_sir1_device,
931#endif
9db144fe
MH		 932#endif
933
934#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
935 &i2c_bfin_twi_device,
936#endif
937
938#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 939#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
9db144fe 940 &bfin_sport0_uart_device,
df5de261
SZ		 941#endif
942#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
9db144fe
MH		 943 &bfin_sport1_uart_device,
944#endif
df5de261 945#endif
9db144fe 946
9db144fe
MH		 947#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
948 &bfin_device_gpiokeys,
949#endif
950
9c21453e
HK		 951#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
952 &cm_flash_device,
9db144fe 953#endif
9db144fe
MH		 954};
955
7f6678c5 956static int __init cm_init(void)
9db144fe
MH		 957{
958 printk(KERN_INFO "%s(): registering device resources\n", __func__);
9db144fe
MH		 959 i2c_register_board_info(0, bfin_i2c_board_info,
960 ARRAY_SIZE(bfin_i2c_board_info));
9c21453e 961 platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices));
9db144fe 962 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
9db144fe
MH		 963 return 0;
964}
965
7f6678c5 966arch_initcall(cm_init);
9db144fe 967
c13ce9fd
SZ		 968static struct platform_device *cmbf527_early_devices[] __initdata = {
969#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
970#ifdef CONFIG_SERIAL_BFIN_UART0
971 &bfin_uart0_device,
972#endif
973#ifdef CONFIG_SERIAL_BFIN_UART1
974 &bfin_uart1_device,
975#endif
976#endif
977
978#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
979#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
980 &bfin_sport0_uart_device,
981#endif
982#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
983 &bfin_sport1_uart_device,
984#endif
985#endif
986};
987
988void __init native_machine_early_platform_add_devices(void)
989{
990 printk(KERN_INFO "register early platform devices\n");
991 early_platform_add_devices(cmbf527_early_devices,
992 ARRAY_SIZE(cmbf527_early_devices));
993}
994
9db144fe
MH		 995void native_machine_restart(char *cmd)
996{
997 /* workaround reboot hang when booting from SPI */
998 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 999 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
9db144fe
MH		 1000}
1001
1002void bfin_get_ether_addr(char *addr)
1003{
1004 random_ether_addr(addr);
1005 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
1006}
1007EXPORT_SYMBOL(bfin_get_ether_addr);
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