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Blackfin: add UART/SPORT early platform resources
[net-next-2.6.git] / arch / blackfin / mach-bf527 / boards / cm_bf527.c
CommitLineData
9db144fe 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
9db144fe 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
9db144fe
MH		 8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/etherdevice.h>
9db144fe
MH		 18#include <linux/i2c.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/usb/sl811.h>
9db144fe 22#include <linux/usb/musb.h>
9db144fe
MH		 23#include <asm/dma.h>
24#include <asm/bfin5xx_spi.h>
25#include <asm/reboot.h>
26#include <asm/nand.h>
27#include <asm/portmux.h>
28#include <asm/dpmc.h>
29#include <linux/spi/ad7877.h>
30
31/*
32 * Name the Board for the /proc/cpuinfo
33 */
34const char bfin_board_name[] = "Bluetechnix CM-BF527";
35
36/*
37 * Driver needs to know address, irq and flag pin.
38 */
39
9db144fe 40#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 41#include <linux/usb/isp1760.h>
42static struct resource bfin_isp1760_resources[] = {
9db144fe 43 [0] = {
3f375690
MH		 44 .start = 0x203C0000,
45 .end = 0x203C0000 + 0x000fffff,
9db144fe
MH		 46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
3f375690
MH		 49 .start = IRQ_PF7,
50 .end = IRQ_PF7,
9db144fe
MH		 51 .flags = IORESOURCE_IRQ,
52 },
53};
54
3f375690
MH		 55static struct isp1760_platform_data isp1760_priv = {
56 .is_isp1761 = 0,
3f375690
MH		 57 .bus_width_16 = 1,
58 .port1_otg = 0,
59 .analog_oc = 0,
60 .dack_polarity_high = 0,
61 .dreq_polarity_high = 0,
9db144fe
MH		 62};
63
3f375690 64static struct platform_device bfin_isp1760_device = {
c6feb768 65 .name = "isp1760",
3f375690
MH		 66 .id = 0,
67 .dev = {
68 .platform_data = &isp1760_priv,
69 },
70 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
71 .resource = bfin_isp1760_resources,
9db144fe 72};
9db144fe
MH		 73#endif
74
75#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
76static struct resource musb_resources[] = {
77 [0] = {
78 .start = 0xffc03800,
79 .end = 0xffc03cff,
80 .flags = IORESOURCE_MEM,
81 },
82 [1] = { /* general IRQ */
83 .start = IRQ_USB_INT0,
84 .end = IRQ_USB_INT0,
85 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
86 },
87 [2] = { /* DMA IRQ */
88 .start = IRQ_USB_DMA,
89 .end = IRQ_USB_DMA,
90 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
91 },
92};
93
50041acb
BW		 94static struct musb_hdrc_config musb_config = {
95 .multipoint = 0,
96 .dyn_fifo = 0,
97 .soft_con = 1,
98 .dma = 1,
fea05dac
BW		 99 .num_eps = 8,
100 .dma_channels = 8,
50041acb
BW		 101 .gpio_vrsel = GPIO_PF11,
102};
103
9db144fe
MH		 104static struct musb_hdrc_platform_data musb_plat = {
105#if defined(CONFIG_USB_MUSB_OTG)
106 .mode = MUSB_OTG,
107#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
108 .mode = MUSB_HOST,
109#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
110 .mode = MUSB_PERIPHERAL,
111#endif
50041acb 112 .config = &musb_config,
9db144fe
MH		 113};
114
115static u64 musb_dmamask = ~(u32)0;
116
117static struct platform_device musb_device = {
118 .name = "musb_hdrc",
119 .id = 0,
120 .dev = {
121 .dma_mask = &musb_dmamask,
122 .coherent_dma_mask = 0xffffffff,
123 .platform_data = &musb_plat,
124 },
125 .num_resources = ARRAY_SIZE(musb_resources),
126 .resource = musb_resources,
127};
128#endif
129
9db144fe
MH		 130#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
131static struct mtd_partition partition_info[] = {
132 {
aa582977 133 .name = "linux kernel(nand)",
9db144fe 134 .offset = 0,
f4585a08 135 .size = 4 * 1024 * 1024,
9db144fe
MH		 136 },
137 {
aa582977 138 .name = "file system(nand)",
9db144fe
MH		 139 .offset = MTDPART_OFS_APPEND,
140 .size = MTDPART_SIZ_FULL,
141 },
142};
143
144static struct bf5xx_nand_platform bf5xx_nand_platform = {
145 .page_size = NFC_PG_SIZE_256,
146 .data_width = NFC_NWIDTH_8,
147 .partitions = partition_info,
148 .nr_partitions = ARRAY_SIZE(partition_info),
149 .rd_dly = 3,
150 .wr_dly = 3,
151};
152
153static struct resource bf5xx_nand_resources[] = {
154 {
155 .start = NFC_CTL,
156 .end = NFC_DATA_RD + 2,
157 .flags = IORESOURCE_MEM,
158 },
159 {
160 .start = CH_NFC,
161 .end = CH_NFC,
162 .flags = IORESOURCE_IRQ,
163 },
164};
165
166static struct platform_device bf5xx_nand_device = {
167 .name = "bf5xx-nand",
168 .id = 0,
169 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
170 .resource = bf5xx_nand_resources,
171 .dev = {
172 .platform_data = &bf5xx_nand_platform,
173 },
174};
175#endif
176
177#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
178static struct resource bfin_pcmcia_cf_resources[] = {
179 {
180 .start = 0x20310000, /* IO PORT */
181 .end = 0x20312000,
182 .flags = IORESOURCE_MEM,
183 }, {
184 .start = 0x20311000, /* Attribute Memory */
185 .end = 0x20311FFF,
186 .flags = IORESOURCE_MEM,
187 }, {
188 .start = IRQ_PF4,
189 .end = IRQ_PF4,
190 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
191 }, {
192 .start = 6, /* Card Detect PF6 */
193 .end = 6,
194 .flags = IORESOURCE_IRQ,
195 },
196};
197
198static struct platform_device bfin_pcmcia_cf_device = {
199 .name = "bfin_cf_pcmcia",
200 .id = -1,
201 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
202 .resource = bfin_pcmcia_cf_resources,
203};
204#endif
205
206#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
207static struct platform_device rtc_device = {
208 .name = "rtc-bfin",
209 .id = -1,
210};
211#endif
212
213#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 214#include <linux/smc91x.h>
215
216static struct smc91x_platdata smc91x_info = {
217 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
218 .leda = RPC_LED_100_10,
219 .ledb = RPC_LED_TX_RX,
220};
221
9db144fe
MH		 222static struct resource smc91x_resources[] = {
223 {
224 .name = "smc91x-regs",
225 .start = 0x20300300,
226 .end = 0x20300300 + 16,
227 .flags = IORESOURCE_MEM,
228 }, {
229
230 .start = IRQ_PF7,
231 .end = IRQ_PF7,
232 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
233 },
234};
235static struct platform_device smc91x_device = {
236 .name = "smc91x",
237 .id = 0,
238 .num_resources = ARRAY_SIZE(smc91x_resources),
239 .resource = smc91x_resources,
61f09b5a
MH		 240 .dev = {
241 .platform_data = &smc91x_info,
242 },
9db144fe
MH		 243};
244#endif
245
246#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
247static struct resource dm9000_resources[] = {
248 [0] = {
249 .start = 0x203FB800,
b3dec4a4 250 .end = 0x203FB800 + 1,
9db144fe
MH		 251 .flags = IORESOURCE_MEM,
252 },
253 [1] = {
b3dec4a4
BS		 254 .start = 0x203FB804,
255 .end = 0x203FB804 + 1,
256 .flags = IORESOURCE_MEM,
257 },
258 [2] = {
9db144fe
MH		 259 .start = IRQ_PF9,
260 .end = IRQ_PF9,
261 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
262 },
263};
264
265static struct platform_device dm9000_device = {
266 .name = "dm9000",
267 .id = -1,
268 .num_resources = ARRAY_SIZE(dm9000_resources),
269 .resource = dm9000_resources,
270};
271#endif
272
273#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
274static struct resource sl811_hcd_resources[] = {
275 {
276 .start = 0x20340000,
277 .end = 0x20340000,
278 .flags = IORESOURCE_MEM,
279 }, {
280 .start = 0x20340004,
281 .end = 0x20340004,
282 .flags = IORESOURCE_MEM,
283 }, {
284 .start = CONFIG_USB_SL811_BFIN_IRQ,
285 .end = CONFIG_USB_SL811_BFIN_IRQ,
286 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
287 },
288};
289
290#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
291void sl811_port_power(struct device *dev, int is_on)
292{
293 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
294 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
295}
296#endif
297
298static struct sl811_platform_data sl811_priv = {
299 .potpg = 10,
300 .power = 250, /* == 500mA */
301#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
302 .port_power = &sl811_port_power,
303#endif
304};
305
306static struct platform_device sl811_hcd_device = {
307 .name = "sl811-hcd",
308 .id = 0,
309 .dev = {
310 .platform_data = &sl811_priv,
311 },
312 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
313 .resource = sl811_hcd_resources,
314};
315#endif
316
9db144fe 317#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 318static struct platform_device bfin_mii_bus = {
319 .name = "bfin_mii_bus",
320};
321
9db144fe
MH		 322static struct platform_device bfin_mac_device = {
323 .name = "bfin_mac",
65319628 324 .dev.platform_data = &bfin_mii_bus,
9db144fe
MH		 325};
326#endif
327
328#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
329static struct resource net2272_bfin_resources[] = {
330 {
331 .start = 0x20300000,
332 .end = 0x20300000 + 0x100,
333 .flags = IORESOURCE_MEM,
334 }, {
335 .start = IRQ_PF7,
336 .end = IRQ_PF7,
337 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
338 },
339};
340
341static struct platform_device net2272_bfin_device = {
342 .name = "net2272",
343 .id = -1,
344 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
345 .resource = net2272_bfin_resources,
346};
347#endif
348
349#if defined(CONFIG_MTD_M25P80) \
350 || defined(CONFIG_MTD_M25P80_MODULE)
351static struct mtd_partition bfin_spi_flash_partitions[] = {
352 {
aa582977 353 .name = "bootloader(spi)",
9db144fe
MH		 354 .size = 0x00040000,
355 .offset = 0,
356 .mask_flags = MTD_CAP_ROM
357 }, {
aa582977 358 .name = "linux kernel(spi)",
9db144fe
MH		 359 .size = MTDPART_SIZ_FULL,
360 .offset = MTDPART_OFS_APPEND,
361 }
362};
363
364static struct flash_platform_data bfin_spi_flash_data = {
365 .name = "m25p80",
366 .parts = bfin_spi_flash_partitions,
367 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
368 .type = "m25p16",
369};
370
371/* SPI flash chip (m25p64) */
372static struct bfin5xx_spi_chip spi_flash_chip_info = {
373 .enable_dma = 0, /* use dma transfer with this chip*/
374 .bits_per_word = 8,
375};
376#endif
377
a261eec0
MF		 378#if defined(CONFIG_BFIN_SPI_ADC) \
379 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
9db144fe
MH		 380/* SPI ADC chip */
381static struct bfin5xx_spi_chip spi_adc_chip_info = {
382 .enable_dma = 1, /* use dma transfer with this chip*/
383 .bits_per_word = 16,
384};
385#endif
386
387#if defined(CONFIG_SND_BLACKFIN_AD1836) \
388 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
389static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
390 .enable_dma = 0,
391 .bits_per_word = 16,
392};
393#endif
394
f3f704d3
MH		 395#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
396static struct bfin5xx_spi_chip mmc_spi_chip_info = {
397 .enable_dma = 0,
9db144fe
MH		 398 .bits_per_word = 8,
399};
400#endif
401
9db144fe
MH		 402#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
403static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
404 .enable_dma = 0,
405 .bits_per_word = 16,
406};
407
408static const struct ad7877_platform_data bfin_ad7877_ts_info = {
409 .model = 7877,
410 .vref_delay_usecs = 50, /* internal, no capacitor */
411 .x_plate_ohms = 419,
412 .y_plate_ohms = 486,
413 .pressure_max = 1000,
414 .pressure_min = 0,
415 .stopacq_polarity = 1,
416 .first_conversion_delay = 3,
417 .acquisition_time = 1,
418 .averaging = 1,
419 .pen_down_acc_interval = 1,
420};
421#endif
422
423#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
424 && defined(CONFIG_SND_SOC_WM8731_SPI)
425static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
426 .enable_dma = 0,
427 .bits_per_word = 16,
428};
429#endif
430
431#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
432static struct bfin5xx_spi_chip spidev_chip_info = {
433 .enable_dma = 0,
434 .bits_per_word = 8,
435};
436#endif
437
438static struct spi_board_info bfin_spi_board_info[] __initdata = {
439#if defined(CONFIG_MTD_M25P80) \
440 || defined(CONFIG_MTD_M25P80_MODULE)
441 {
442 /* the modalias must be the same as spi device driver name */
443 .modalias = "m25p80", /* Name of spi_driver for this device */
444 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
445 .bus_num = 0, /* Framework bus number */
446 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
447 .platform_data = &bfin_spi_flash_data,
448 .controller_data = &spi_flash_chip_info,
449 .mode = SPI_MODE_3,
450 },
451#endif
452
a261eec0
MF		 453#if defined(CONFIG_BFIN_SPI_ADC) \
454 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
9db144fe
MH		 455 {
456 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
457 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
458 .bus_num = 0, /* Framework bus number */
459 .chip_select = 1, /* Framework chip select. */
460 .platform_data = NULL, /* No spi_driver specific config */
461 .controller_data = &spi_adc_chip_info,
462 },
463#endif
464
465#if defined(CONFIG_SND_BLACKFIN_AD1836) \
466 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
467 {
dac98174 468 .modalias = "ad1836",
9db144fe
MH		 469 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
470 .bus_num = 0,
471 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
472 .controller_data = &ad1836_spi_chip_info,
473 },
474#endif
f3f704d3 475#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
9db144fe 476 {
f3f704d3
MH		 477 .modalias = "mmc_spi",
478 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
9db144fe 479 .bus_num = 0,
f3f704d3
MH		 480 .chip_select = 5,
481 .controller_data = &mmc_spi_chip_info,
9db144fe
MH		 482 .mode = SPI_MODE_3,
483 },
484#endif
9db144fe
MH		 485#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
486 {
487 .modalias = "ad7877",
488 .platform_data = &bfin_ad7877_ts_info,
489 .irq = IRQ_PF8,
490 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
491 .bus_num = 0,
492 .chip_select = 2,
493 .controller_data = &spi_ad7877_chip_info,
494 },
495#endif
496#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
497 && defined(CONFIG_SND_SOC_WM8731_SPI)
498 {
499 .modalias = "wm8731",
500 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
501 .bus_num = 0,
502 .chip_select = 5,
503 .controller_data = &spi_wm8731_chip_info,
504 .mode = SPI_MODE_0,
505 },
506#endif
507#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
508 {
509 .modalias = "spidev",
510 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
511 .bus_num = 0,
512 .chip_select = 1,
513 .controller_data = &spidev_chip_info,
514 },
515#endif
516};
517
518#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
519/* SPI controller data */
520static struct bfin5xx_spi_master bfin_spi0_info = {
521 .num_chipselect = 8,
522 .enable_dma = 1, /* master has the ability to do dma transfer */
523 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
524};
525
526/* SPI (0) */
527static struct resource bfin_spi0_resource[] = {
528 [0] = {
529 .start = SPI0_REGBASE,
530 .end = SPI0_REGBASE + 0xFF,
531 .flags = IORESOURCE_MEM,
532 },
533 [1] = {
534 .start = CH_SPI,
535 .end = CH_SPI,
53122693
YL		 536 .flags = IORESOURCE_DMA,
537 },
538 [2] = {
539 .start = IRQ_SPI,
540 .end = IRQ_SPI,
9db144fe
MH		 541 .flags = IORESOURCE_IRQ,
542 },
543};
544
545static struct platform_device bfin_spi0_device = {
546 .name = "bfin-spi",
547 .id = 0, /* Bus number */
548 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
549 .resource = bfin_spi0_resource,
550 .dev = {
551 .platform_data = &bfin_spi0_info, /* Passed to driver */
552 },
553};
554#endif /* spi master and devices */
555
9c21453e
HK		 556#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
557static struct mtd_partition cm_partitions[] = {
558 {
559 .name = "bootloader(nor)",
560 .size = 0x40000,
561 .offset = 0,
562 }, {
563 .name = "linux kernel(nor)",
564 .size = 0x100000,
565 .offset = MTDPART_OFS_APPEND,
566 }, {
567 .name = "file system(nor)",
568 .size = MTDPART_SIZ_FULL,
569 .offset = MTDPART_OFS_APPEND,
570 }
571};
572
573static struct physmap_flash_data cm_flash_data = {
574 .width = 2,
575 .parts = cm_partitions,
576 .nr_parts = ARRAY_SIZE(cm_partitions),
577};
578
579static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 };
580
581static struct resource cm_flash_resource[] = {
582 {
583 .name = "cfi_probe",
584 .start = 0x20000000,
585 .end = 0x201fffff,
586 .flags = IORESOURCE_MEM,
587 }, {
588 .start = (unsigned long)cm_flash_gpios,
589 .end = ARRAY_SIZE(cm_flash_gpios),
590 .flags = IORESOURCE_IRQ,
591 }
592};
593
594static struct platform_device cm_flash_device = {
595 .name = "gpio-addr-flash",
596 .id = 0,
597 .dev = {
598 .platform_data = &cm_flash_data,
599 },
600 .num_resources = ARRAY_SIZE(cm_flash_resource),
601 .resource = cm_flash_resource,
602};
603#endif
604
9db144fe 605#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
9db144fe 606#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 607static struct resource bfin_uart0_resources[] = {
9db144fe 608 {
6bd1fbea
SZ		 609 .start = UART0_THR,
610 .end = UART0_GCTL+2,
9db144fe
MH		 611 .flags = IORESOURCE_MEM,
612 },
6bd1fbea
SZ		 613 {
614 .start = IRQ_UART0_RX,
615 .end = IRQ_UART0_RX+1,
616 .flags = IORESOURCE_IRQ,
617 },
618 {
619 .start = IRQ_UART0_ERROR,
620 .end = IRQ_UART0_ERROR,
621 .flags = IORESOURCE_IRQ,
622 },
623 {
624 .start = CH_UART0_TX,
625 .end = CH_UART0_TX,
626 .flags = IORESOURCE_DMA,
627 },
628 {
629 .start = CH_UART0_RX,
630 .end = CH_UART0_RX,
631 .flags = IORESOURCE_DMA,
632 },
633};
634
635unsigned short bfin_uart0_peripherals[] = {
636 P_UART0_TX, P_UART0_RX, 0
637};
638
639static struct platform_device bfin_uart0_device = {
640 .name = "bfin-uart",
641 .id = 0,
642 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
643 .resource = bfin_uart0_resources,
644 .dev = {
645 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
646 },
647};
9db144fe
MH		 648#endif
649#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 650static struct resource bfin_uart1_resources[] = {
9db144fe 651 {
6bd1fbea
SZ		 652 .start = UART1_THR,
653 .end = UART1_GCTL+2,
9db144fe
MH		 654 .flags = IORESOURCE_MEM,
655 },
6bd1fbea
SZ		 656 {
657 .start = IRQ_UART1_RX,
658 .end = IRQ_UART1_RX+1,
659 .flags = IORESOURCE_IRQ,
660 },
661 {
662 .start = IRQ_UART1_ERROR,
663 .end = IRQ_UART1_ERROR,
664 .flags = IORESOURCE_IRQ,
665 },
666 {
667 .start = CH_UART1_TX,
668 .end = CH_UART1_TX,
669 .flags = IORESOURCE_DMA,
670 },
671 {
672 .start = CH_UART1_RX,
673 .end = CH_UART1_RX,
674 .flags = IORESOURCE_DMA,
675 },
676#ifdef CONFIG_BFIN_UART1_CTSRTS
677 { /* CTS pin */
678 .start = GPIO_PF9,
679 .end = GPIO_PF9,
680 .flags = IORESOURCE_IO,
681 },
682 { /* RTS pin */
683 .start = GPIO_PF10,
684 .end = GPIO_PF10,
685 .flags = IORESOURCE_IO,
686 },
9db144fe
MH		 687#endif
688};
689
6bd1fbea
SZ		 690unsigned short bfin_uart1_peripherals[] = {
691 P_UART1_TX, P_UART1_RX, 0
692};
693
694static struct platform_device bfin_uart1_device = {
9db144fe
MH		 695 .name = "bfin-uart",
696 .id = 1,
6bd1fbea
SZ		 697 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
698 .resource = bfin_uart1_resources,
699 .dev = {
700 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
701 },
9db144fe
MH		 702};
703#endif
6bd1fbea 704#endif
9db144fe
MH		 705
706#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
9db144fe 707#ifdef CONFIG_BFIN_SIR0
42bd8bcb 708static struct resource bfin_sir0_resources[] = {
9db144fe
MH		 709 {
710 .start = 0xFFC00400,
711 .end = 0xFFC004FF,
712 .flags = IORESOURCE_MEM,
713 },
42bd8bcb
GY		 714 {
715 .start = IRQ_UART0_RX,
716 .end = IRQ_UART0_RX+1,
717 .flags = IORESOURCE_IRQ,
718 },
719 {
720 .start = CH_UART0_RX,
721 .end = CH_UART0_RX+1,
722 .flags = IORESOURCE_DMA,
723 },
724};
725
726static struct platform_device bfin_sir0_device = {
727 .name = "bfin_sir",
728 .id = 0,
729 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
730 .resource = bfin_sir0_resources,
731};
9db144fe
MH		 732#endif
733#ifdef CONFIG_BFIN_SIR1
42bd8bcb 734static struct resource bfin_sir1_resources[] = {
9db144fe
MH		 735 {
736 .start = 0xFFC02000,
737 .end = 0xFFC020FF,
738 .flags = IORESOURCE_MEM,
739 },
42bd8bcb
GY		 740 {
741 .start = IRQ_UART1_RX,
742 .end = IRQ_UART1_RX+1,
743 .flags = IORESOURCE_IRQ,
744 },
745 {
746 .start = CH_UART1_RX,
747 .end = CH_UART1_RX+1,
748 .flags = IORESOURCE_DMA,
749 },
9db144fe
MH		 750};
751
42bd8bcb 752static struct platform_device bfin_sir1_device = {
9db144fe 753 .name = "bfin_sir",
42bd8bcb
GY		 754 .id = 1,
755 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
756 .resource = bfin_sir1_resources,
9db144fe
MH		 757};
758#endif
42bd8bcb 759#endif
9db144fe
MH		 760
761#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
762static struct resource bfin_twi0_resource[] = {
763 [0] = {
764 .start = TWI0_REGBASE,
765 .end = TWI0_REGBASE,
766 .flags = IORESOURCE_MEM,
767 },
768 [1] = {
769 .start = IRQ_TWI,
770 .end = IRQ_TWI,
771 .flags = IORESOURCE_IRQ,
772 },
773};
774
775static struct platform_device i2c_bfin_twi_device = {
776 .name = "i2c-bfin-twi",
777 .id = 0,
778 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
779 .resource = bfin_twi0_resource,
780};
781#endif
782
9db144fe 783static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
ebd58333 784#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
9db144fe
MH		 785 {
786 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
9db144fe
MH		 787 },
788#endif
204844eb 789#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
9db144fe
MH		 790 {
791 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
9db144fe
MH		 792 .irq = IRQ_PF8,
793 },
794#endif
50c4c086
MH		 795#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
796 {
797 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
798 },
799#endif
9db144fe 800};
9db144fe
MH		 801
802#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 803#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
804static struct resource bfin_sport0_uart_resources[] = {
805 {
806 .start = SPORT0_TCR1,
807 .end = SPORT0_MRCS3+4,
808 .flags = IORESOURCE_MEM,
809 },
810 {
811 .start = IRQ_SPORT0_RX,
812 .end = IRQ_SPORT0_RX+1,
813 .flags = IORESOURCE_IRQ,
814 },
815 {
816 .start = IRQ_SPORT0_ERROR,
817 .end = IRQ_SPORT0_ERROR,
818 .flags = IORESOURCE_IRQ,
819 },
820};
821
822unsigned short bfin_sport0_peripherals[] = {
823 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
824 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
825};
826
9db144fe
MH		 827static struct platform_device bfin_sport0_uart_device = {
828 .name = "bfin-sport-uart",
829 .id = 0,
df5de261
SZ		 830 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
831 .resource = bfin_sport0_uart_resources,
832 .dev = {
833 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
834 },
835};
836#endif
837#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
838static struct resource bfin_sport1_uart_resources[] = {
839 {
840 .start = SPORT1_TCR1,
841 .end = SPORT1_MRCS3+4,
842 .flags = IORESOURCE_MEM,
843 },
844 {
845 .start = IRQ_SPORT1_RX,
846 .end = IRQ_SPORT1_RX+1,
847 .flags = IORESOURCE_IRQ,
848 },
849 {
850 .start = IRQ_SPORT1_ERROR,
851 .end = IRQ_SPORT1_ERROR,
852 .flags = IORESOURCE_IRQ,
853 },
854};
855
856unsigned short bfin_sport1_peripherals[] = {
857 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
858 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
9db144fe
MH		 859};
860
861static struct platform_device bfin_sport1_uart_device = {
862 .name = "bfin-sport-uart",
863 .id = 1,
df5de261
SZ		 864 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
865 .resource = bfin_sport1_uart_resources,
866 .dev = {
867 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
868 },
9db144fe
MH		 869};
870#endif
df5de261 871#endif
9db144fe 872
9db144fe
MH		 873#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
874#include <linux/input.h>
875#include <linux/gpio_keys.h>
876
877static struct gpio_keys_button bfin_gpio_keys_table[] = {
878 {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"},
879};
880
881static struct gpio_keys_platform_data bfin_gpio_keys_data = {
882 .buttons = bfin_gpio_keys_table,
883 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
884};
885
886static struct platform_device bfin_device_gpiokeys = {
887 .name = "gpio-keys",
888 .dev = {
889 .platform_data = &bfin_gpio_keys_data,
890 },
891};
892#endif
893
9db144fe
MH		 894static const unsigned int cclk_vlev_datasheet[] =
895{
896 VRPAIR(VLEV_100, 400000000),
897 VRPAIR(VLEV_105, 426000000),
898 VRPAIR(VLEV_110, 500000000),
899 VRPAIR(VLEV_115, 533000000),
900 VRPAIR(VLEV_120, 600000000),
901};
902
903static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
904 .tuple_tab = cclk_vlev_datasheet,
905 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
906 .vr_settling_time = 25 /* us */,
907};
908
909static struct platform_device bfin_dpmc = {
910 .name = "bfin dpmc",
911 .dev = {
912 .platform_data = &bfin_dmpc_vreg_data,
913 },
914};
915
9c21453e 916static struct platform_device *cmbf527_devices[] __initdata = {
9db144fe
MH		 917
918 &bfin_dpmc,
919
920#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
921 &bf5xx_nand_device,
922#endif
923
924#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
925 &bfin_pcmcia_cf_device,
926#endif
927
928#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
929 &rtc_device,
930#endif
931
932#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
933 &sl811_hcd_device,
934#endif
935
3f375690
MH		 936#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
937 &bfin_isp1760_device,
938#endif
939
9db144fe
MH		 940#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
941 &musb_device,
942#endif
943
944#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
945 &smc91x_device,
946#endif
947
948#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
949 &dm9000_device,
950#endif
951
952#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 953 &bfin_mii_bus,
9db144fe
MH		 954 &bfin_mac_device,
955#endif
956
957#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
958 &net2272_bfin_device,
959#endif
960
961#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
962 &bfin_spi0_device,
963#endif
964
9db144fe 965#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 966#ifdef CONFIG_SERIAL_BFIN_UART0
967 &bfin_uart0_device,
968#endif
969#ifdef CONFIG_SERIAL_BFIN_UART1
970 &bfin_uart1_device,
971#endif
9db144fe
MH		 972#endif
973
974#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 975#ifdef CONFIG_BFIN_SIR0
976 &bfin_sir0_device,
977#endif
978#ifdef CONFIG_BFIN_SIR1
979 &bfin_sir1_device,
980#endif
9db144fe
MH		 981#endif
982
983#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
984 &i2c_bfin_twi_device,
985#endif
986
987#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 988#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
9db144fe 989 &bfin_sport0_uart_device,
df5de261
SZ		 990#endif
991#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
9db144fe
MH		 992 &bfin_sport1_uart_device,
993#endif
df5de261 994#endif
9db144fe 995
9db144fe
MH		 996#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
997 &bfin_device_gpiokeys,
998#endif
999
9c21453e
HK		 1000#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
1001 &cm_flash_device,
9db144fe 1002#endif
9db144fe
MH		 1003};
1004
7f6678c5 1005static int __init cm_init(void)
9db144fe
MH		 1006{
1007 printk(KERN_INFO "%s(): registering device resources\n", __func__);
9db144fe
MH		 1008 i2c_register_board_info(0, bfin_i2c_board_info,
1009 ARRAY_SIZE(bfin_i2c_board_info));
9c21453e 1010 platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices));
9db144fe 1011 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
9db144fe
MH		 1012 return 0;
1013}
1014
7f6678c5 1015arch_initcall(cm_init);
9db144fe 1016
c13ce9fd
SZ		 1017static struct platform_device *cmbf527_early_devices[] __initdata = {
1018#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1019#ifdef CONFIG_SERIAL_BFIN_UART0
1020 &bfin_uart0_device,
1021#endif
1022#ifdef CONFIG_SERIAL_BFIN_UART1
1023 &bfin_uart1_device,
1024#endif
1025#endif
1026
1027#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1028#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1029 &bfin_sport0_uart_device,
1030#endif
1031#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1032 &bfin_sport1_uart_device,
1033#endif
1034#endif
1035};
1036
1037void __init native_machine_early_platform_add_devices(void)
1038{
1039 printk(KERN_INFO "register early platform devices\n");
1040 early_platform_add_devices(cmbf527_early_devices,
1041 ARRAY_SIZE(cmbf527_early_devices));
1042}
1043
9db144fe
MH		 1044void native_machine_restart(char *cmd)
1045{
1046 /* workaround reboot hang when booting from SPI */
1047 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 1048 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
9db144fe
MH		 1049}
1050
1051void bfin_get_ether_addr(char *addr)
1052{
1053 random_ether_addr(addr);
1054 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
1055}
1056EXPORT_SYMBOL(bfin_get_ether_addr);
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