[net-next-2.6.git] / arch / blackfin / mach-bf518 / include / mach / portmux.h

#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_

#define MAX_RESOURCES 	MAX_BLACKFIN_GPIOS

/* EMAC MII/RMII Port Mux */
#define P_MII0_ETxD2	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
#define P_MII0_ERxD2	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
#define P_MII0_ETxD3	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
#define P_MII0_ERxD3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
#define P_MII0_ERxCLK	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
#define P_MII0_ERxDV	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
#define P_MII0_COL	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))

#define P_MII0_MDC	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
#define P_MII0_MDIO	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))

#define P_MII0 {\
	P_MII0_ETxD0, \
	P_MII0_ETxD1, \
	P_MII0_ETxD2, \
	P_MII0_ETxD3, \
	P_MII0_ETxEN, \
	P_MII0_TxCLK, \
	P_MII0_PHYINT, \
	P_MII0_COL, \
	P_MII0_ERxD0, \
	P_MII0_ERxD1, \
	P_MII0_ERxD2, \
	P_MII0_ERxD3, \
	P_MII0_ERxDV, \
	P_MII0_ERxCLK, \
	P_MII0_ERxER, \
	P_MII0_CRS, \
	P_MII0_MDC, \
	P_MII0_MDIO, 0}

#define P_RMII0 {\
	P_MII0_ETxD0, \
	P_MII0_ETxD1, \
	P_MII0_ETxEN, \
	P_MII0_ERxD0, \
	P_MII0_ERxD1, \
	P_MII0_ERxER, \
	P_MII0_TxCLK, \
	P_MII0_PHYINT, \
	P_MII0_CRS, \
	P_MII0_MDC, \
	P_MII0_MDIO, 0}

/* PPI Port Mux */
#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))

#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))

/* SPI Port Mux */
#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))

#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))

#define P_SPI1_SS	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))

#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
#define P_SPI1_SSEL4	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
#define P_SPI1_SSEL5	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))

/* SPORT Port Mux */
#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))

#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))

/* UART Port Mux */
#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))

#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))

/* Timer */
#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))

/* DMA */
#define P_DMAR1		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
#define P_DMAR0		(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))

/* TWI */
#define P_TWI0_SCL	(P_DONTCARE)
#define P_TWI0_SDA	(P_DONTCARE)

/* PWM */
#define P_PWM0_AH		(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
#define P_PWM0_AL		(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
#define P_PWM0_BH		(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
#define P_PWM0_BL		(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
#define P_PWM0_CH		(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
#define P_PWM0_CL		(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
#define P_PWM0_SYNC		(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))

#define P_PWM1_AH		(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
#define P_PWM1_AL		(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
#define P_PWM1_BH		(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
#define P_PWM1_BL		(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
#define P_PWM1_CH		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
#define P_PWM1_CL		(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
#define P_PWM1_SYNC		(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))

#define P_PWM_TRIPB		(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))

/* RSI */
#define P_RSI_DATA0		(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
#define P_RSI_DATA1		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
#define P_RSI_DATA2		(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
#define P_RSI_DATA3		(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
#define P_RSI_DATA4		(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
#define P_RSI_DATA5		(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
#define P_RSI_DATA6		(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
#define P_RSI_DATA7		(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
#define P_RSI_CMD		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
#define P_RSI_CLK		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))

/* PTP */
#define P_PTP_PPS		(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
#define P_PTP_CLKOUT		(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))

#define P_HWAIT		(P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1))

#endif				/* _MACH_PORTMUX_H_ */
Commit	Line	Data
2f6f4bcd BW	1	#ifndef _MACH_PORTMUX_H_
	2	#define _MACH_PORTMUX_H_
	3
	4	#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
	5
	6	/* EMAC MII/RMII Port Mux */
	7	#define P_MII0_ETxD2 (P_DEFINED \| P_IDENT(GPIO_PF0) \| P_FUNCT(0))
	8	#define P_MII0_ERxD2 (P_DEFINED \| P_IDENT(GPIO_PF1) \| P_FUNCT(0))
	9	#define P_MII0_ETxD3 (P_DEFINED \| P_IDENT(GPIO_PF2) \| P_FUNCT(0))
	10	#define P_MII0_ERxD3 (P_DEFINED \| P_IDENT(GPIO_PF3) \| P_FUNCT(0))
	11	#define P_MII0_ERxCLK (P_DEFINED \| P_IDENT(GPIO_PF4) \| P_FUNCT(0))
	12	#define P_MII0_ERxDV (P_DEFINED \| P_IDENT(GPIO_PF5) \| P_FUNCT(0))
	13	#define P_MII0_COL (P_DEFINED \| P_IDENT(GPIO_PF6) \| P_FUNCT(0))
	14
	15	#define P_MII0_MDC (P_DEFINED \| P_IDENT(GPIO_PF8) \| P_FUNCT(0))
	16	#define P_MII0_MDIO (P_DEFINED \| P_IDENT(GPIO_PF9) \| P_FUNCT(0))
	17	#define P_MII0_ETxD0 (P_DEFINED \| P_IDENT(GPIO_PF10) \| P_FUNCT(0))
	18	#define P_MII0_ERxD0 (P_DEFINED \| P_IDENT(GPIO_PF11) \| P_FUNCT(0))
	19	#define P_MII0_ETxD1 (P_DEFINED \| P_IDENT(GPIO_PF12) \| P_FUNCT(0))
	20	#define P_MII0_ERxD1 (P_DEFINED \| P_IDENT(GPIO_PF13) \| P_FUNCT(0))
39ca4453	21	#define P_MII0_ETxEN (P_DEFINED \| P_IDENT(GPIO_PF14) \| P_FUNCT(0))
2f6f4bcd BW	22	#define P_MII0_PHYINT (P_DEFINED \| P_IDENT(GPIO_PF15) \| P_FUNCT(0))
	23	#define P_MII0_CRS (P_DEFINED \| P_IDENT(GPIO_PG0) \| P_FUNCT(0))
	24	#define P_MII0_ERxER (P_DEFINED \| P_IDENT(GPIO_PG1) \| P_FUNCT(0))
39ca4453	25	#define P_MII0_TxCLK (P_DEFINED \| P_IDENT(GPIO_PG2) \| P_FUNCT(0))
2f6f4bcd	26
39ca4453	27	#define P_MII0 {\
2f6f4bcd BW	28	P_MII0_ETxD0, \
	29	P_MII0_ETxD1, \
	30	P_MII0_ETxD2, \
	31	P_MII0_ETxD3, \
	32	P_MII0_ETxEN, \
	33	P_MII0_TxCLK, \
	34	P_MII0_PHYINT, \
	35	P_MII0_COL, \
	36	P_MII0_ERxD0, \
	37	P_MII0_ERxD1, \
	38	P_MII0_ERxD2, \
	39	P_MII0_ERxD3, \
	40	P_MII0_ERxDV, \
	41	P_MII0_ERxCLK, \
	42	P_MII0_ERxER, \
	43	P_MII0_CRS, \
	44	P_MII0_MDC, \
	45	P_MII0_MDIO, 0}
	46
39ca4453	47	#define P_RMII0 {\
2f6f4bcd BW	48	P_MII0_ETxD0, \
	49	P_MII0_ETxD1, \
	50	P_MII0_ETxEN, \
	51	P_MII0_ERxD0, \
	52	P_MII0_ERxD1, \
	53	P_MII0_ERxER, \
	54	P_MII0_TxCLK, \
	55	P_MII0_PHYINT, \
	56	P_MII0_CRS, \
	57	P_MII0_MDC, \
	58	P_MII0_MDIO, 0}
	59
	60	/* PPI Port Mux */
	61	#define P_PPI0_D0 (P_DEFINED \| P_IDENT(GPIO_PF0) \| P_FUNCT(1))
	62	#define P_PPI0_D1 (P_DEFINED \| P_IDENT(GPIO_PF1) \| P_FUNCT(1))
	63	#define P_PPI0_D2 (P_DEFINED \| P_IDENT(GPIO_PF2) \| P_FUNCT(1))
	64	#define P_PPI0_D3 (P_DEFINED \| P_IDENT(GPIO_PF3) \| P_FUNCT(1))
	65	#define P_PPI0_D4 (P_DEFINED \| P_IDENT(GPIO_PF4) \| P_FUNCT(1))
	66	#define P_PPI0_D5 (P_DEFINED \| P_IDENT(GPIO_PF5) \| P_FUNCT(1))
	67	#define P_PPI0_D6 (P_DEFINED \| P_IDENT(GPIO_PF6) \| P_FUNCT(1))
	68	#define P_PPI0_D7 (P_DEFINED \| P_IDENT(GPIO_PF7) \| P_FUNCT(1))
	69	#define P_PPI0_D8 (P_DEFINED \| P_IDENT(GPIO_PF8) \| P_FUNCT(1))
	70	#define P_PPI0_D9 (P_DEFINED \| P_IDENT(GPIO_PF9) \| P_FUNCT(1))
	71	#define P_PPI0_D10 (P_DEFINED \| P_IDENT(GPIO_PF10) \| P_FUNCT(1))
	72	#define P_PPI0_D11 (P_DEFINED \| P_IDENT(GPIO_PF11) \| P_FUNCT(1))
	73	#define P_PPI0_D12 (P_DEFINED \| P_IDENT(GPIO_PF12) \| P_FUNCT(1))
	74	#define P_PPI0_D13 (P_DEFINED \| P_IDENT(GPIO_PF13) \| P_FUNCT(1))
	75	#define P_PPI0_D14 (P_DEFINED \| P_IDENT(GPIO_PF14) \| P_FUNCT(1))
	76	#define P_PPI0_D15 (P_DEFINED \| P_IDENT(GPIO_PF15) \| P_FUNCT(1))
	77
	78	#define P_PPI0_CLK (P_DEFINED \| P_IDENT(GPIO_PG12) \| P_FUNCT(1))
	79	#define P_PPI0_FS1 (P_DEFINED \| P_IDENT(GPIO_PG13) \| P_FUNCT(1))
	80	#define P_PPI0_FS2 (P_DEFINED \| P_IDENT(GPIO_PG14) \| P_FUNCT(1))
	81	#define P_PPI0_FS3 (P_DEFINED \| P_IDENT(GPIO_PG15) \| P_FUNCT(1))
	82
	83	/* SPI Port Mux */
	84	#define P_SPI0_SS (P_DEFINED \| P_IDENT(GPIO_PG11) \| P_FUNCT(0))
	85	#define P_SPI0_SCK (P_DEFINED \| P_IDENT(GPIO_PG12) \| P_FUNCT(0))
	86	#define P_SPI0_MISO (P_DEFINED \| P_IDENT(GPIO_PG13) \| P_FUNCT(0))
	87	#define P_SPI0_MOSI (P_DEFINED \| P_IDENT(GPIO_PG14) \| P_FUNCT(0))
	88
	89	#define P_SPI0_SSEL1 (P_DEFINED \| P_IDENT(GPIO_PF7) \| P_FUNCT(0))
	90	#define P_SPI0_SSEL2 (P_DEFINED \| P_IDENT(GPIO_PG15) \| P_FUNCT(0))
	91	#define P_SPI0_SSEL3 (P_DEFINED \| P_IDENT(GPIO_PH4) \| P_FUNCT(2))
	92	#define P_SPI0_SSEL4 (P_DEFINED \| P_IDENT(GPIO_PG10) \| P_FUNCT(2))
	93	#define P_SPI0_SSEL5 (P_DEFINED \| P_IDENT(GPIO_PG3) \| P_FUNCT(2))
	94
	95	#define P_SPI1_SS (P_DEFINED \| P_IDENT(GPIO_PH0) \| P_FUNCT(1))
	96	#define P_SPI1_SCK (P_DEFINED \| P_IDENT(GPIO_PH1) \| P_FUNCT(1))
	97	#define P_SPI1_MISO (P_DEFINED \| P_IDENT(GPIO_PH2) \| P_FUNCT(1))
	98	#define P_SPI1_MOSI (P_DEFINED \| P_IDENT(GPIO_PH3) \| P_FUNCT(1))
	99
	100	#define P_SPI1_SSEL1 (P_DEFINED \| P_IDENT(GPIO_PH6) \| P_FUNCT(2))
	101	#define P_SPI1_SSEL2 (P_DEFINED \| P_IDENT(GPIO_PF0) \| P_FUNCT(2))
	102	#define P_SPI1_SSEL3 (P_DEFINED \| P_IDENT(GPIO_PG0) \| P_FUNCT(2))
	103	#define P_SPI1_SSEL4 (P_DEFINED \| P_IDENT(GPIO_PF8) \| P_FUNCT(2))
	104	#define P_SPI1_SSEL5 (P_DEFINED \| P_IDENT(GPIO_PG11) \| P_FUNCT(2))
	105
	106	/* SPORT Port Mux */
	107	#define P_SPORT0_DRPRI (P_DEFINED \| P_IDENT(GPIO_PG3) \| P_FUNCT(0))
	108	#define P_SPORT0_RSCLK (P_DEFINED \| P_IDENT(GPIO_PG4) \| P_FUNCT(0))
	109	#define P_SPORT0_RFS (P_DEFINED \| P_IDENT(GPIO_PG5) \| P_FUNCT(0))
	110	#define P_SPORT0_TFS (P_DEFINED \| P_IDENT(GPIO_PG6) \| P_FUNCT(0))
	111	#define P_SPORT0_DTPRI (P_DEFINED \| P_IDENT(GPIO_PG7) \| P_FUNCT(0))
112	#define P_SPORT0_TSCLK (P_DEFINED \| P_IDENT(GPIO_PG8) \| P_FUNCT(0))
113	#define P_SPORT0_DTSEC (P_DEFINED \| P_IDENT(GPIO_PG9) \| P_FUNCT(0))
114	#define P_SPORT0_DRSEC (P_DEFINED \| P_IDENT(GPIO_PG10) \| P_FUNCT(0))
115
116	#define P_SPORT1_DRPRI (P_DEFINED \| P_IDENT(GPIO_PH0) \| P_FUNCT(0))
117	#define P_SPORT1_RFS (P_DEFINED \| P_IDENT(GPIO_PH1) \| P_FUNCT(0))
118	#define P_SPORT1_RSCLK (P_DEFINED \| P_IDENT(GPIO_PH2) \| P_FUNCT(0))
119	#define P_SPORT1_DTPRI (P_DEFINED \| P_IDENT(GPIO_PH3) \| P_FUNCT(0))
120	#define P_SPORT1_TFS (P_DEFINED \| P_IDENT(GPIO_PH4) \| P_FUNCT(0))
121	#define P_SPORT1_TSCLK (P_DEFINED \| P_IDENT(GPIO_PH5) \| P_FUNCT(0))
122	#define P_SPORT1_DTSEC (P_DEFINED \| P_IDENT(GPIO_PH6) \| P_FUNCT(0))
123	#define P_SPORT1_DRSEC (P_DEFINED \| P_IDENT(GPIO_PH7) \| P_FUNCT(0))
124
125	/* UART Port Mux */
126	#define P_UART0_TX (P_DEFINED \| P_IDENT(GPIO_PG9) \| P_FUNCT(1))
127	#define P_UART0_RX (P_DEFINED \| P_IDENT(GPIO_PG10) \| P_FUNCT(1))
128
129	#define P_UART1_TX (P_DEFINED \| P_IDENT(GPIO_PH6) \| P_FUNCT(1))
130	#define P_UART1_RX (P_DEFINED \| P_IDENT(GPIO_PH7) \| P_FUNCT(1))
131
132	/* Timer */
133	#define P_TMRCLK (P_DEFINED \| P_IDENT(GPIO_PG5) \| P_FUNCT(2))
134	#define P_TMR0 (P_DEFINED \| P_IDENT(GPIO_PG6) \| P_FUNCT(2))
135	#define P_TMR1 (P_DEFINED \| P_IDENT(GPIO_PG7) \| P_FUNCT(2))
136	#define P_TMR2 (P_DEFINED \| P_IDENT(GPIO_PF9) \| P_FUNCT(2))
137	#define P_TMR3 (P_DEFINED \| P_IDENT(GPIO_PF10) \| P_FUNCT(2))
138	#define P_TMR4 (P_DEFINED \| P_IDENT(GPIO_PG9) \| P_FUNCT(2))
139	#define P_TMR5 (P_DEFINED \| P_IDENT(GPIO_PG4) \| P_FUNCT(2))
140	#define P_TMR6 (P_DEFINED \| P_IDENT(GPIO_PG8) \| P_FUNCT(2))
141	#define P_TMR7 (P_DEFINED \| P_IDENT(GPIO_PH7) \| P_FUNCT(2))
142
143	/* DMA */
144	#define P_DMAR1 (P_DEFINED \| P_IDENT(GPIO_PG1) \| P_FUNCT(1))
145	#define P_DMAR0 (P_DEFINED \| P_IDENT(GPIO_PG2) \| P_FUNCT(1))
146
147	/* TWI */
148	#define P_TWI0_SCL (P_DONTCARE)
149	#define P_TWI0_SDA (P_DONTCARE)
150
151	/* PWM */
152	#define P_PWM0_AH (P_DEFINED \| P_IDENT(GPIO_PF1) \| P_FUNCT(2))
153	#define P_PWM0_AL (P_DEFINED \| P_IDENT(GPIO_PF2) \| P_FUNCT(2))
154	#define P_PWM0_BH (P_DEFINED \| P_IDENT(GPIO_PF3) \| P_FUNCT(2))
155	#define P_PWM0_BL (P_DEFINED \| P_IDENT(GPIO_PF4) \| P_FUNCT(2))
156	#define P_PWM0_CH (P_DEFINED \| P_IDENT(GPIO_PF5) \| P_FUNCT(2))
157	#define P_PWM0_CL (P_DEFINED \| P_IDENT(GPIO_PF6) \| P_FUNCT(2))
158	#define P_PWM0_SYNC (P_DEFINED \| P_IDENT(GPIO_PF7) \| P_FUNCT(2))
159
160	#define P_PWM1_AH (P_DEFINED \| P_IDENT(GPIO_PF11) \| P_FUNCT(2))
161	#define P_PWM1_AL (P_DEFINED \| P_IDENT(GPIO_PF12) \| P_FUNCT(2))
162	#define P_PWM1_BH (P_DEFINED \| P_IDENT(GPIO_PF13) \| P_FUNCT(2))
163	#define P_PWM1_BL (P_DEFINED \| P_IDENT(GPIO_PF14) \| P_FUNCT(2))
164	#define P_PWM1_CH (P_DEFINED \| P_IDENT(GPIO_PG1) \| P_FUNCT(2))
165	#define P_PWM1_CL (P_DEFINED \| P_IDENT(GPIO_PG2) \| P_FUNCT(2))
166	#define P_PWM1_SYNC (P_DEFINED \| P_IDENT(GPIO_PF15) \| P_FUNCT(2))
167
168	#define P_PWM_TRIPB (P_DEFINED \| P_IDENT(GPIO_PG14) \| P_FUNCT(2))
169
170	/* RSI */
171	#define P_RSI_DATA0 (P_DEFINED \| P_IDENT(GPIO_PG3) \| P_FUNCT(1))
172	#define P_RSI_DATA1 (P_DEFINED \| P_IDENT(GPIO_PG4) \| P_FUNCT(1))
173	#define P_RSI_DATA2 (P_DEFINED \| P_IDENT(GPIO_PG5) \| P_FUNCT(1))
174	#define P_RSI_DATA3 (P_DEFINED \| P_IDENT(GPIO_PG6) \| P_FUNCT(1))
175	#define P_RSI_DATA4 (P_DEFINED \| P_IDENT(GPIO_PH0) \| P_FUNCT(2))
176	#define P_RSI_DATA5 (P_DEFINED \| P_IDENT(GPIO_PH1) \| P_FUNCT(2))
177	#define P_RSI_DATA6 (P_DEFINED \| P_IDENT(GPIO_PH2) \| P_FUNCT(2))
178	#define P_RSI_DATA7 (P_DEFINED \| P_IDENT(GPIO_PH3) \| P_FUNCT(2))
179	#define P_RSI_CMD (P_DEFINED \| P_IDENT(GPIO_PG7) \| P_FUNCT(1))
180	#define P_RSI_CLK (P_DEFINED \| P_IDENT(GPIO_PG8) \| P_FUNCT(1))
181
182	/* PTP */
183	#define P_PTP_PPS (P_DEFINED \| P_IDENT(GPIO_PG12) \| P_FUNCT(2))
184	#define P_PTP_CLKOUT (P_DEFINED \| P_IDENT(GPIO_PG13) \| P_FUNCT(2))
185
186	#define P_HWAIT (P_DEFINED \| P_IDENT(GPIO_PG000000000) \| P_FUNCT(1))
187
188	#endif /* _MACH_PORTMUX_H_ */