]>
Commit | Line | Data |
---|---|---|
2f6f4bcd BW |
1 | /* |
2 | * File: include/asm-blackfin/mach-bf518/anomaly.h | |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
4 | * | |
c18e99cf | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
2f6f4bcd BW |
6 | * Licensed under the GPL-2 or later. |
7 | */ | |
8 | ||
a413647b | 9 | /* This file should be up to date with: |
a200ad22 | 10 | * - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List |
2f6f4bcd BW |
11 | */ |
12 | ||
a413647b MF |
13 | /* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ |
14 | #if __SILICON_REVISION__ < 0 | |
15 | # error will not work on BF518 silicon version | |
16 | #endif | |
17 | ||
2f6f4bcd BW |
18 | #ifndef _MACH_ANOMALY_H_ |
19 | #define _MACH_ANOMALY_H_ | |
20 | ||
a200ad22 | 21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
2f6f4bcd BW |
22 | #define ANOMALY_05000074 (1) |
23 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
24 | #define ANOMALY_05000122 (1) | |
25 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
26 | #define ANOMALY_05000245 (1) | |
c18e99cf MF |
27 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ |
28 | #define ANOMALY_05000254 (1) | |
2f6f4bcd BW |
29 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
30 | #define ANOMALY_05000265 (1) | |
31 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | |
32 | #define ANOMALY_05000310 (1) | |
33 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | |
34 | #define ANOMALY_05000366 (1) | |
35 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ | |
36 | #define ANOMALY_05000405 (1) | |
37 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ | |
38 | #define ANOMALY_05000408 (1) | |
39 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | |
40 | #define ANOMALY_05000416 (1) | |
41 | /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ | |
42 | #define ANOMALY_05000421 (1) | |
43 | /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ | |
44 | #define ANOMALY_05000422 (1) | |
45 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | |
46 | #define ANOMALY_05000426 (1) | |
47 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | |
a200ad22 | 48 | #define ANOMALY_05000430 (__SILICON_REVISION__ < 1) |
2f6f4bcd BW |
49 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ |
50 | #define ANOMALY_05000431 (1) | |
51 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ | |
a200ad22 | 52 | #define ANOMALY_05000435 (__SILICON_REVISION__ < 1) |
2f6f4bcd | 53 | /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ |
a200ad22 | 54 | #define ANOMALY_05000438 (__SILICON_REVISION__ < 1) |
a413647b | 55 | /* Preboot Cannot be Used to Alter the PLL_DIV Register */ |
a200ad22 | 56 | #define ANOMALY_05000439 (__SILICON_REVISION__ < 1) |
2f6f4bcd | 57 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ |
a200ad22 | 58 | #define ANOMALY_05000440 (__SILICON_REVISION__ < 1) |
2f6f4bcd BW |
59 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
60 | #define ANOMALY_05000443 (1) | |
61 | /* Incorrect L1 Instruction Bank B Memory Map Location */ | |
a200ad22 | 62 | #define ANOMALY_05000444 (__SILICON_REVISION__ < 1) |
c18e99cf | 63 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ |
a200ad22 | 64 | #define ANOMALY_05000452 (__SILICON_REVISION__ < 1) |
c18e99cf | 65 | /* PWM_TRIPB Signal Not Available on PG10 */ |
a200ad22 | 66 | #define ANOMALY_05000453 (__SILICON_REVISION__ < 1) |
c18e99cf | 67 | /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ |
a200ad22 MF |
68 | #define ANOMALY_05000455 (__SILICON_REVISION__ < 1) |
69 | /* False Hardware Error when RETI Points to Invalid Memory */ | |
a413647b | 70 | #define ANOMALY_05000461 (1) |
a200ad22 MF |
71 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ |
72 | #define ANOMALY_05000462 (1) | |
2f6f4bcd BW |
73 | |
74 | /* Anomalies that don't exist on this proc */ | |
a413647b MF |
75 | #define ANOMALY_05000099 (0) |
76 | #define ANOMALY_05000119 (0) | |
77 | #define ANOMALY_05000120 (0) | |
2f6f4bcd | 78 | #define ANOMALY_05000125 (0) |
a413647b | 79 | #define ANOMALY_05000149 (0) |
2f6f4bcd | 80 | #define ANOMALY_05000158 (0) |
a413647b MF |
81 | #define ANOMALY_05000171 (0) |
82 | #define ANOMALY_05000179 (0) | |
a200ad22 | 83 | #define ANOMALY_05000182 (0) |
2f6f4bcd | 84 | #define ANOMALY_05000183 (0) |
976119bc | 85 | #define ANOMALY_05000189 (0) |
2f6f4bcd | 86 | #define ANOMALY_05000198 (0) |
a200ad22 | 87 | #define ANOMALY_05000202 (0) |
a413647b MF |
88 | #define ANOMALY_05000215 (0) |
89 | #define ANOMALY_05000220 (0) | |
90 | #define ANOMALY_05000227 (0) | |
2f6f4bcd | 91 | #define ANOMALY_05000230 (0) |
a413647b MF |
92 | #define ANOMALY_05000231 (0) |
93 | #define ANOMALY_05000233 (0) | |
a200ad22 | 94 | #define ANOMALY_05000234 (0) |
a413647b | 95 | #define ANOMALY_05000242 (0) |
2f6f4bcd | 96 | #define ANOMALY_05000244 (0) |
a413647b MF |
97 | #define ANOMALY_05000248 (0) |
98 | #define ANOMALY_05000250 (0) | |
a200ad22 | 99 | #define ANOMALY_05000257 (0) |
2f6f4bcd BW |
100 | #define ANOMALY_05000261 (0) |
101 | #define ANOMALY_05000263 (0) | |
102 | #define ANOMALY_05000266 (0) | |
103 | #define ANOMALY_05000273 (0) | |
a413647b | 104 | #define ANOMALY_05000274 (0) |
ee554be9 | 105 | #define ANOMALY_05000278 (0) |
a200ad22 MF |
106 | #define ANOMALY_05000281 (0) |
107 | #define ANOMALY_05000283 (0) | |
2f6f4bcd | 108 | #define ANOMALY_05000285 (0) |
a413647b MF |
109 | #define ANOMALY_05000287 (0) |
110 | #define ANOMALY_05000301 (0) | |
c18e99cf | 111 | #define ANOMALY_05000305 (0) |
2f6f4bcd BW |
112 | #define ANOMALY_05000307 (0) |
113 | #define ANOMALY_05000311 (0) | |
114 | #define ANOMALY_05000312 (0) | |
a200ad22 | 115 | #define ANOMALY_05000315 (0) |
2f6f4bcd BW |
116 | #define ANOMALY_05000323 (0) |
117 | #define ANOMALY_05000353 (0) | |
a200ad22 | 118 | #define ANOMALY_05000357 (0) |
a413647b | 119 | #define ANOMALY_05000362 (1) |
2f6f4bcd | 120 | #define ANOMALY_05000363 (0) |
976119bc | 121 | #define ANOMALY_05000364 (0) |
a200ad22 | 122 | #define ANOMALY_05000371 (0) |
ee554be9 | 123 | #define ANOMALY_05000380 (0) |
2f6f4bcd | 124 | #define ANOMALY_05000386 (0) |
a413647b MF |
125 | #define ANOMALY_05000389 (0) |
126 | #define ANOMALY_05000400 (0) | |
6651ece9 MF |
127 | #define ANOMALY_05000412 (0) |
128 | #define ANOMALY_05000432 (0) | |
7dbc3f6e MF |
129 | #define ANOMALY_05000447 (0) |
130 | #define ANOMALY_05000448 (0) | |
a413647b MF |
131 | #define ANOMALY_05000456 (0) |
132 | #define ANOMALY_05000450 (0) | |
a200ad22 MF |
133 | #define ANOMALY_05000465 (0) |
134 | #define ANOMALY_05000467 (0) | |
2f6f4bcd BW |
135 | |
136 | #endif |