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Commit | Line | Data |
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1394f032 | 1 | /* |
550d5538 | 2 | * arch/blackfin/kernel/setup.c |
1394f032 | 3 | * |
550d5538 | 4 | * Copyright 2004-2006 Analog Devices Inc. |
1394f032 | 5 | * |
550d5538 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
1394f032 | 7 | * |
550d5538 | 8 | * Licensed under the GPL-2 or later. |
1394f032 BW |
9 | */ |
10 | ||
11 | #include <linux/delay.h> | |
12 | #include <linux/console.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/seq_file.h> | |
15 | #include <linux/cpu.h> | |
259fea42 | 16 | #include <linux/mm.h> |
1394f032 | 17 | #include <linux/module.h> |
1394f032 | 18 | #include <linux/tty.h> |
856783b3 | 19 | #include <linux/pfn.h> |
1394f032 BW |
20 | |
21 | #include <linux/ext2_fs.h> | |
22 | #include <linux/cramfs_fs.h> | |
23 | #include <linux/romfs_fs.h> | |
24 | ||
3bebca2d | 25 | #include <asm/cplb.h> |
1394f032 BW |
26 | #include <asm/cacheflush.h> |
27 | #include <asm/blackfin.h> | |
28 | #include <asm/cplbinit.h> | |
1754a5d9 | 29 | #include <asm/div64.h> |
8f65873e | 30 | #include <asm/cpu.h> |
7adfb58f | 31 | #include <asm/fixed_code.h> |
ce3afa1c | 32 | #include <asm/early_printk.h> |
1394f032 | 33 | |
a9c59c27 | 34 | u16 _bfin_swrst; |
d45118b1 | 35 | EXPORT_SYMBOL(_bfin_swrst); |
a9c59c27 | 36 | |
1394f032 | 37 | unsigned long memory_start, memory_end, physical_mem_end; |
3132b586 | 38 | unsigned long _rambase, _ramstart, _ramend; |
1394f032 BW |
39 | unsigned long reserved_mem_dcache_on; |
40 | unsigned long reserved_mem_icache_on; | |
41 | EXPORT_SYMBOL(memory_start); | |
42 | EXPORT_SYMBOL(memory_end); | |
43 | EXPORT_SYMBOL(physical_mem_end); | |
44 | EXPORT_SYMBOL(_ramend); | |
58c35bd3 | 45 | EXPORT_SYMBOL(reserved_mem_dcache_on); |
1394f032 BW |
46 | |
47 | #ifdef CONFIG_MTD_UCLINUX | |
48 | unsigned long memory_mtd_end, memory_mtd_start, mtd_size; | |
49 | unsigned long _ebss; | |
50 | EXPORT_SYMBOL(memory_mtd_end); | |
51 | EXPORT_SYMBOL(memory_mtd_start); | |
52 | EXPORT_SYMBOL(mtd_size); | |
53 | #endif | |
54 | ||
5e10b4a6 | 55 | char __initdata command_line[COMMAND_LINE_SIZE]; |
0c7a6b21 RG |
56 | void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat, |
57 | *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr; | |
1394f032 | 58 | |
856783b3 YL |
59 | /* boot memmap, for parsing "memmap=" */ |
60 | #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */ | |
61 | #define BFIN_MEMMAP_RAM 1 | |
62 | #define BFIN_MEMMAP_RESERVED 2 | |
af4c7d4b | 63 | static struct bfin_memmap { |
856783b3 YL |
64 | int nr_map; |
65 | struct bfin_memmap_entry { | |
66 | unsigned long long addr; /* start of memory segment */ | |
67 | unsigned long long size; | |
68 | unsigned long type; | |
69 | } map[BFIN_MEMMAP_MAX]; | |
70 | } bfin_memmap __initdata; | |
71 | ||
72 | /* for memmap sanitization */ | |
73 | struct change_member { | |
74 | struct bfin_memmap_entry *pentry; /* pointer to original entry */ | |
75 | unsigned long long addr; /* address for this change point */ | |
76 | }; | |
77 | static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata; | |
78 | static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata; | |
79 | static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata; | |
80 | static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; | |
81 | ||
8f65873e GY |
82 | DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data); |
83 | ||
7f1e2f98 MF |
84 | static int early_init_clkin_hz(char *buf); |
85 | ||
3bebca2d | 86 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) |
8f65873e GY |
87 | void __init generate_cplb_tables(void) |
88 | { | |
89 | unsigned int cpu; | |
90 | ||
dbdf20db | 91 | generate_cplb_tables_all(); |
8f65873e GY |
92 | /* Generate per-CPU I&D CPLB tables */ |
93 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) | |
94 | generate_cplb_tables_cpu(cpu); | |
95 | } | |
1394f032 BW |
96 | #endif |
97 | ||
8f65873e GY |
98 | void __cpuinit bfin_setup_caches(unsigned int cpu) |
99 | { | |
3bebca2d | 100 | #ifdef CONFIG_BFIN_ICACHE |
8f65873e | 101 | bfin_icache_init(icplb_tbl[cpu]); |
1394f032 BW |
102 | #endif |
103 | ||
3bebca2d | 104 | #ifdef CONFIG_BFIN_DCACHE |
8f65873e | 105 | bfin_dcache_init(dcplb_tbl[cpu]); |
8f65873e GY |
106 | #endif |
107 | ||
108 | /* | |
109 | * In cache coherence emulation mode, we need to have the | |
110 | * D-cache enabled before running any atomic operation which | |
111 | * might invove cache invalidation (i.e. spinlock, rwlock). | |
112 | * So printk's are deferred until then. | |
113 | */ | |
114 | #ifdef CONFIG_BFIN_ICACHE | |
115 | printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); | |
116 | #endif | |
117 | #ifdef CONFIG_BFIN_DCACHE | |
118 | printk(KERN_INFO "Data Cache Enabled for CPU%u" | |
3bebca2d | 119 | # if defined CONFIG_BFIN_WB |
1394f032 | 120 | " (write-back)" |
3bebca2d | 121 | # elif defined CONFIG_BFIN_WT |
1394f032 BW |
122 | " (write-through)" |
123 | # endif | |
8f65873e | 124 | "\n", cpu); |
1394f032 BW |
125 | #endif |
126 | } | |
127 | ||
8f65873e GY |
128 | void __cpuinit bfin_setup_cpudata(unsigned int cpu) |
129 | { | |
130 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); | |
131 | ||
132 | cpudata->idle = current; | |
133 | cpudata->loops_per_jiffy = loops_per_jiffy; | |
8f65873e GY |
134 | cpudata->imemctl = bfin_read_IMEM_CONTROL(); |
135 | cpudata->dmemctl = bfin_read_DMEM_CONTROL(); | |
136 | } | |
137 | ||
138 | void __init bfin_cache_init(void) | |
139 | { | |
140 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) | |
141 | generate_cplb_tables(); | |
142 | #endif | |
143 | bfin_setup_caches(0); | |
144 | } | |
145 | ||
5b04f271 | 146 | void __init bfin_relocate_l1_mem(void) |
1394f032 BW |
147 | { |
148 | unsigned long l1_code_length; | |
149 | unsigned long l1_data_a_length; | |
150 | unsigned long l1_data_b_length; | |
262c3825 | 151 | unsigned long l2_length; |
1394f032 | 152 | |
fecbd736 RG |
153 | /* |
154 | * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S | |
155 | * we know that everything about l1 text/data is nice and aligned, | |
156 | * so copy by 4 byte chunks, and don't worry about overlapping | |
157 | * src/dest. | |
158 | * | |
159 | * We can't use the dma_memcpy functions, since they can call | |
160 | * scheduler functions which might be in L1 :( and core writes | |
161 | * into L1 instruction cause bad access errors, so we are stuck, | |
162 | * we are required to use DMA, but can't use the common dma | |
163 | * functions. We can't use memcpy either - since that might be | |
164 | * going to be in the relocated L1 | |
165 | */ | |
166 | ||
dd3dd384 MF |
167 | blackfin_dma_early_init(); |
168 | ||
fecbd736 | 169 | /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ |
1394f032 | 170 | l1_code_length = _etext_l1 - _stext_l1; |
fecbd736 RG |
171 | if (l1_code_length) |
172 | early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length); | |
1394f032 | 173 | |
fecbd736 | 174 | /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */ |
3b1f26a5 | 175 | l1_data_a_length = _sbss_l1 - _sdata_l1; |
fecbd736 RG |
176 | if (l1_data_a_length) |
177 | early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); | |
1394f032 | 178 | |
fecbd736 | 179 | /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */ |
3b1f26a5 | 180 | l1_data_b_length = _sbss_b_l1 - _sdata_b_l1; |
fecbd736 RG |
181 | if (l1_data_b_length) |
182 | early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + | |
1394f032 | 183 | l1_data_a_length, l1_data_b_length); |
262c3825 | 184 | |
fecbd736 RG |
185 | early_dma_memcpy_done(); |
186 | ||
187 | /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */ | |
07aa7be5 | 188 | if (L2_LENGTH != 0) { |
3b1f26a5 | 189 | l2_length = _sbss_l2 - _stext_l2; |
fecbd736 RG |
190 | if (l2_length) |
191 | memcpy(_stext_l2, _l2_lma_start, l2_length); | |
07aa7be5 | 192 | } |
1394f032 BW |
193 | } |
194 | ||
856783b3 YL |
195 | /* add_memory_region to memmap */ |
196 | static void __init add_memory_region(unsigned long long start, | |
197 | unsigned long long size, int type) | |
198 | { | |
199 | int i; | |
200 | ||
201 | i = bfin_memmap.nr_map; | |
202 | ||
203 | if (i == BFIN_MEMMAP_MAX) { | |
204 | printk(KERN_ERR "Ooops! Too many entries in the memory map!\n"); | |
205 | return; | |
206 | } | |
207 | ||
208 | bfin_memmap.map[i].addr = start; | |
209 | bfin_memmap.map[i].size = size; | |
210 | bfin_memmap.map[i].type = type; | |
211 | bfin_memmap.nr_map++; | |
212 | } | |
213 | ||
214 | /* | |
215 | * Sanitize the boot memmap, removing overlaps. | |
216 | */ | |
217 | static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) | |
218 | { | |
219 | struct change_member *change_tmp; | |
220 | unsigned long current_type, last_type; | |
221 | unsigned long long last_addr; | |
222 | int chgidx, still_changing; | |
223 | int overlap_entries; | |
224 | int new_entry; | |
225 | int old_nr, new_nr, chg_nr; | |
226 | int i; | |
227 | ||
228 | /* | |
229 | Visually we're performing the following (1,2,3,4 = memory types) | |
230 | ||
231 | Sample memory map (w/overlaps): | |
232 | ____22__________________ | |
233 | ______________________4_ | |
234 | ____1111________________ | |
235 | _44_____________________ | |
236 | 11111111________________ | |
237 | ____________________33__ | |
238 | ___________44___________ | |
239 | __________33333_________ | |
240 | ______________22________ | |
241 | ___________________2222_ | |
242 | _________111111111______ | |
243 | _____________________11_ | |
244 | _________________4______ | |
245 | ||
246 | Sanitized equivalent (no overlap): | |
247 | 1_______________________ | |
248 | _44_____________________ | |
249 | ___1____________________ | |
250 | ____22__________________ | |
251 | ______11________________ | |
252 | _________1______________ | |
253 | __________3_____________ | |
254 | ___________44___________ | |
255 | _____________33_________ | |
256 | _______________2________ | |
257 | ________________1_______ | |
258 | _________________4______ | |
259 | ___________________2____ | |
260 | ____________________33__ | |
261 | ______________________4_ | |
262 | */ | |
263 | /* if there's only one memory region, don't bother */ | |
264 | if (*pnr_map < 2) | |
265 | return -1; | |
266 | ||
267 | old_nr = *pnr_map; | |
268 | ||
269 | /* bail out if we find any unreasonable addresses in memmap */ | |
270 | for (i = 0; i < old_nr; i++) | |
271 | if (map[i].addr + map[i].size < map[i].addr) | |
272 | return -1; | |
273 | ||
274 | /* create pointers for initial change-point information (for sorting) */ | |
275 | for (i = 0; i < 2*old_nr; i++) | |
276 | change_point[i] = &change_point_list[i]; | |
277 | ||
278 | /* record all known change-points (starting and ending addresses), | |
279 | omitting those that are for empty memory regions */ | |
280 | chgidx = 0; | |
8f65873e | 281 | for (i = 0; i < old_nr; i++) { |
856783b3 YL |
282 | if (map[i].size != 0) { |
283 | change_point[chgidx]->addr = map[i].addr; | |
284 | change_point[chgidx++]->pentry = &map[i]; | |
285 | change_point[chgidx]->addr = map[i].addr + map[i].size; | |
286 | change_point[chgidx++]->pentry = &map[i]; | |
287 | } | |
288 | } | |
8f65873e | 289 | chg_nr = chgidx; /* true number of change-points */ |
856783b3 YL |
290 | |
291 | /* sort change-point list by memory addresses (low -> high) */ | |
292 | still_changing = 1; | |
8f65873e | 293 | while (still_changing) { |
856783b3 | 294 | still_changing = 0; |
8f65873e | 295 | for (i = 1; i < chg_nr; i++) { |
856783b3 YL |
296 | /* if <current_addr> > <last_addr>, swap */ |
297 | /* or, if current=<start_addr> & last=<end_addr>, swap */ | |
298 | if ((change_point[i]->addr < change_point[i-1]->addr) || | |
299 | ((change_point[i]->addr == change_point[i-1]->addr) && | |
300 | (change_point[i]->addr == change_point[i]->pentry->addr) && | |
301 | (change_point[i-1]->addr != change_point[i-1]->pentry->addr)) | |
302 | ) { | |
303 | change_tmp = change_point[i]; | |
304 | change_point[i] = change_point[i-1]; | |
305 | change_point[i-1] = change_tmp; | |
306 | still_changing = 1; | |
307 | } | |
308 | } | |
309 | } | |
310 | ||
311 | /* create a new memmap, removing overlaps */ | |
8f65873e GY |
312 | overlap_entries = 0; /* number of entries in the overlap table */ |
313 | new_entry = 0; /* index for creating new memmap entries */ | |
314 | last_type = 0; /* start with undefined memory type */ | |
315 | last_addr = 0; /* start with 0 as last starting address */ | |
856783b3 YL |
316 | /* loop through change-points, determining affect on the new memmap */ |
317 | for (chgidx = 0; chgidx < chg_nr; chgidx++) { | |
318 | /* keep track of all overlapping memmap entries */ | |
319 | if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) { | |
320 | /* add map entry to overlap list (> 1 entry implies an overlap) */ | |
321 | overlap_list[overlap_entries++] = change_point[chgidx]->pentry; | |
322 | } else { | |
323 | /* remove entry from list (order independent, so swap with last) */ | |
324 | for (i = 0; i < overlap_entries; i++) { | |
325 | if (overlap_list[i] == change_point[chgidx]->pentry) | |
326 | overlap_list[i] = overlap_list[overlap_entries-1]; | |
327 | } | |
328 | overlap_entries--; | |
329 | } | |
330 | /* if there are overlapping entries, decide which "type" to use */ | |
331 | /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */ | |
332 | current_type = 0; | |
333 | for (i = 0; i < overlap_entries; i++) | |
334 | if (overlap_list[i]->type > current_type) | |
335 | current_type = overlap_list[i]->type; | |
336 | /* continue building up new memmap based on this information */ | |
8f65873e | 337 | if (current_type != last_type) { |
856783b3 YL |
338 | if (last_type != 0) { |
339 | new_map[new_entry].size = | |
340 | change_point[chgidx]->addr - last_addr; | |
341 | /* move forward only if the new size was non-zero */ | |
342 | if (new_map[new_entry].size != 0) | |
343 | if (++new_entry >= BFIN_MEMMAP_MAX) | |
8f65873e | 344 | break; /* no more space left for new entries */ |
856783b3 YL |
345 | } |
346 | if (current_type != 0) { | |
347 | new_map[new_entry].addr = change_point[chgidx]->addr; | |
348 | new_map[new_entry].type = current_type; | |
349 | last_addr = change_point[chgidx]->addr; | |
350 | } | |
351 | last_type = current_type; | |
352 | } | |
353 | } | |
8f65873e | 354 | new_nr = new_entry; /* retain count for new entries */ |
856783b3 | 355 | |
8f65873e | 356 | /* copy new mapping into original location */ |
856783b3 YL |
357 | memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry)); |
358 | *pnr_map = new_nr; | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static void __init print_memory_map(char *who) | |
364 | { | |
365 | int i; | |
366 | ||
367 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
368 | printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who, | |
369 | bfin_memmap.map[i].addr, | |
370 | bfin_memmap.map[i].addr + bfin_memmap.map[i].size); | |
371 | switch (bfin_memmap.map[i].type) { | |
372 | case BFIN_MEMMAP_RAM: | |
373 | printk("(usable)\n"); | |
374 | break; | |
375 | case BFIN_MEMMAP_RESERVED: | |
376 | printk("(reserved)\n"); | |
377 | break; | |
378 | default: printk("type %lu\n", bfin_memmap.map[i].type); | |
379 | break; | |
380 | } | |
381 | } | |
382 | } | |
383 | ||
384 | static __init int parse_memmap(char *arg) | |
385 | { | |
386 | unsigned long long start_at, mem_size; | |
387 | ||
388 | if (!arg) | |
389 | return -EINVAL; | |
390 | ||
391 | mem_size = memparse(arg, &arg); | |
392 | if (*arg == '@') { | |
393 | start_at = memparse(arg+1, &arg); | |
394 | add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM); | |
395 | } else if (*arg == '$') { | |
396 | start_at = memparse(arg+1, &arg); | |
397 | add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED); | |
398 | } | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
1394f032 BW |
403 | /* |
404 | * Initial parsing of the command line. Currently, we support: | |
405 | * - Controlling the linux memory size: mem=xxx[KMG] | |
406 | * - Controlling the physical memory size: max_mem=xxx[KMG][$][#] | |
407 | * $ -> reserved memory is dcacheable | |
408 | * # -> reserved memory is icacheable | |
856783b3 YL |
409 | * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region |
410 | * @ from <start> to <start>+<mem>, type RAM | |
411 | * $ from <start> to <start>+<mem>, type RESERVED | |
1394f032 BW |
412 | */ |
413 | static __init void parse_cmdline_early(char *cmdline_p) | |
414 | { | |
415 | char c = ' ', *to = cmdline_p; | |
416 | unsigned int memsize; | |
417 | for (;;) { | |
418 | if (c == ' ') { | |
1394f032 BW |
419 | if (!memcmp(to, "mem=", 4)) { |
420 | to += 4; | |
421 | memsize = memparse(to, &to); | |
422 | if (memsize) | |
423 | _ramend = memsize; | |
424 | ||
425 | } else if (!memcmp(to, "max_mem=", 8)) { | |
426 | to += 8; | |
427 | memsize = memparse(to, &to); | |
428 | if (memsize) { | |
429 | physical_mem_end = memsize; | |
430 | if (*to != ' ') { | |
431 | if (*to == '$' | |
432 | || *(to + 1) == '$') | |
8f65873e | 433 | reserved_mem_dcache_on = 1; |
1394f032 BW |
434 | if (*to == '#' |
435 | || *(to + 1) == '#') | |
8f65873e | 436 | reserved_mem_icache_on = 1; |
1394f032 BW |
437 | } |
438 | } | |
7f1e2f98 MF |
439 | } else if (!memcmp(to, "clkin_hz=", 9)) { |
440 | to += 9; | |
441 | early_init_clkin_hz(to); | |
ce3afa1c RG |
442 | } else if (!memcmp(to, "earlyprintk=", 12)) { |
443 | to += 12; | |
444 | setup_early_printk(to); | |
856783b3 YL |
445 | } else if (!memcmp(to, "memmap=", 7)) { |
446 | to += 7; | |
447 | parse_memmap(to); | |
1394f032 | 448 | } |
1394f032 BW |
449 | } |
450 | c = *(to++); | |
451 | if (!c) | |
452 | break; | |
453 | } | |
454 | } | |
455 | ||
856783b3 YL |
456 | /* |
457 | * Setup memory defaults from user config. | |
458 | * The physical memory layout looks like: | |
459 | * | |
460 | * [_rambase, _ramstart]: kernel image | |
461 | * [memory_start, memory_end]: dynamic memory managed by kernel | |
462 | * [memory_end, _ramend]: reserved memory | |
3094c981 | 463 | * [memory_mtd_start(memory_end), |
856783b3 YL |
464 | * memory_mtd_start + mtd_size]: rootfs (if any) |
465 | * [_ramend - DMA_UNCACHED_REGION, | |
466 | * _ramend]: uncached DMA region | |
467 | * [_ramend, physical_mem_end]: memory not managed by kernel | |
856783b3 | 468 | */ |
8f65873e | 469 | static __init void memory_setup(void) |
1394f032 | 470 | { |
c0eab3b7 MF |
471 | #ifdef CONFIG_MTD_UCLINUX |
472 | unsigned long mtd_phys = 0; | |
473 | #endif | |
474 | ||
856783b3 | 475 | _rambase = (unsigned long)_stext; |
b7627acc | 476 | _ramstart = (unsigned long)_end; |
1394f032 | 477 | |
856783b3 YL |
478 | if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) { |
479 | console_init(); | |
d8804adf | 480 | panic("DMA region exceeds memory limit: %lu.", |
856783b3 | 481 | _ramend - _ramstart); |
1aafd909 | 482 | } |
1394f032 BW |
483 | memory_end = _ramend - DMA_UNCACHED_REGION; |
484 | ||
b97b8a99 | 485 | #ifdef CONFIG_MPU |
8f65873e | 486 | /* Round up to multiple of 4MB */ |
b97b8a99 BS |
487 | memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; |
488 | #else | |
1394f032 | 489 | memory_start = PAGE_ALIGN(_ramstart); |
b97b8a99 | 490 | #endif |
1394f032 BW |
491 | |
492 | #if defined(CONFIG_MTD_UCLINUX) | |
493 | /* generic memory mapped MTD driver */ | |
494 | memory_mtd_end = memory_end; | |
495 | ||
496 | mtd_phys = _ramstart; | |
497 | mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8))); | |
498 | ||
499 | # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS) | |
500 | if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC) | |
501 | mtd_size = | |
502 | PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10); | |
503 | # endif | |
504 | ||
505 | # if defined(CONFIG_CRAMFS) | |
506 | if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC) | |
507 | mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4))); | |
508 | # endif | |
509 | ||
510 | # if defined(CONFIG_ROMFS_FS) | |
511 | if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0 | |
512 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) | |
513 | mtd_size = | |
514 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); | |
3bebca2d | 515 | # if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) |
1394f032 BW |
516 | /* Due to a Hardware Anomaly we need to limit the size of usable |
517 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | |
518 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | |
519 | */ | |
520 | # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO)) | |
521 | if (memory_end >= 56 * 1024 * 1024) | |
522 | memory_end = 56 * 1024 * 1024; | |
523 | # else | |
524 | if (memory_end >= 60 * 1024 * 1024) | |
525 | memory_end = 60 * 1024 * 1024; | |
526 | # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */ | |
527 | # endif /* ANOMALY_05000263 */ | |
528 | # endif /* CONFIG_ROMFS_FS */ | |
529 | ||
530 | memory_end -= mtd_size; | |
531 | ||
532 | if (mtd_size == 0) { | |
533 | console_init(); | |
d8804adf | 534 | panic("Don't boot kernel without rootfs attached."); |
1394f032 BW |
535 | } |
536 | ||
537 | /* Relocate MTD image to the top of memory after the uncached memory area */ | |
b7627acc | 538 | dma_memcpy((char *)memory_end, _end, mtd_size); |
1394f032 BW |
539 | |
540 | memory_mtd_start = memory_end; | |
541 | _ebss = memory_mtd_start; /* define _ebss for compatible */ | |
542 | #endif /* CONFIG_MTD_UCLINUX */ | |
543 | ||
3bebca2d | 544 | #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) |
1394f032 BW |
545 | /* Due to a Hardware Anomaly we need to limit the size of usable |
546 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | |
547 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | |
548 | */ | |
549 | #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO)) | |
550 | if (memory_end >= 56 * 1024 * 1024) | |
551 | memory_end = 56 * 1024 * 1024; | |
552 | #else | |
553 | if (memory_end >= 60 * 1024 * 1024) | |
554 | memory_end = 60 * 1024 * 1024; | |
555 | #endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */ | |
556 | printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20); | |
557 | #endif /* ANOMALY_05000263 */ | |
558 | ||
b97b8a99 BS |
559 | #ifdef CONFIG_MPU |
560 | page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32; | |
561 | page_mask_order = get_order(3 * page_mask_nelts * sizeof(long)); | |
562 | #endif | |
563 | ||
1394f032 | 564 | #if !defined(CONFIG_MTD_UCLINUX) |
856783b3 YL |
565 | /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/ |
566 | memory_end -= SIZE_4K; | |
1394f032 | 567 | #endif |
856783b3 | 568 | |
1394f032 BW |
569 | init_mm.start_code = (unsigned long)_stext; |
570 | init_mm.end_code = (unsigned long)_etext; | |
571 | init_mm.end_data = (unsigned long)_edata; | |
572 | init_mm.brk = (unsigned long)0; | |
573 | ||
856783b3 YL |
574 | printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20); |
575 | printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20); | |
576 | ||
b7627acc | 577 | printk(KERN_INFO "Memory map:\n" |
8929ecf8 | 578 | KERN_INFO " fixedcode = 0x%p-0x%p\n" |
856783b3 YL |
579 | KERN_INFO " text = 0x%p-0x%p\n" |
580 | KERN_INFO " rodata = 0x%p-0x%p\n" | |
b7627acc | 581 | KERN_INFO " bss = 0x%p-0x%p\n" |
856783b3 YL |
582 | KERN_INFO " data = 0x%p-0x%p\n" |
583 | KERN_INFO " stack = 0x%p-0x%p\n" | |
584 | KERN_INFO " init = 0x%p-0x%p\n" | |
856783b3 YL |
585 | KERN_INFO " available = 0x%p-0x%p\n" |
586 | #ifdef CONFIG_MTD_UCLINUX | |
587 | KERN_INFO " rootfs = 0x%p-0x%p\n" | |
588 | #endif | |
589 | #if DMA_UNCACHED_REGION > 0 | |
590 | KERN_INFO " DMA Zone = 0x%p-0x%p\n" | |
591 | #endif | |
8929ecf8 MF |
592 | , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END, |
593 | _stext, _etext, | |
856783b3 | 594 | __start_rodata, __end_rodata, |
b7627acc | 595 | __bss_start, __bss_stop, |
856783b3 YL |
596 | _sdata, _edata, |
597 | (void *)&init_thread_union, | |
598 | (void *)((int)(&init_thread_union) + 0x2000), | |
b7627acc MF |
599 | __init_begin, __init_end, |
600 | (void *)_ramstart, (void *)memory_end | |
856783b3 YL |
601 | #ifdef CONFIG_MTD_UCLINUX |
602 | , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size) | |
603 | #endif | |
604 | #if DMA_UNCACHED_REGION > 0 | |
605 | , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend) | |
606 | #endif | |
607 | ); | |
608 | } | |
609 | ||
2e8d7965 YL |
610 | /* |
611 | * Find the lowest, highest page frame number we have available | |
612 | */ | |
613 | void __init find_min_max_pfn(void) | |
614 | { | |
615 | int i; | |
616 | ||
617 | max_pfn = 0; | |
618 | min_low_pfn = memory_end; | |
619 | ||
620 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
621 | unsigned long start, end; | |
622 | /* RAM? */ | |
623 | if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) | |
624 | continue; | |
625 | start = PFN_UP(bfin_memmap.map[i].addr); | |
626 | end = PFN_DOWN(bfin_memmap.map[i].addr + | |
627 | bfin_memmap.map[i].size); | |
628 | if (start >= end) | |
629 | continue; | |
630 | if (end > max_pfn) | |
631 | max_pfn = end; | |
632 | if (start < min_low_pfn) | |
633 | min_low_pfn = start; | |
634 | } | |
635 | } | |
636 | ||
856783b3 YL |
637 | static __init void setup_bootmem_allocator(void) |
638 | { | |
639 | int bootmap_size; | |
640 | int i; | |
2e8d7965 | 641 | unsigned long start_pfn, end_pfn; |
856783b3 YL |
642 | unsigned long curr_pfn, last_pfn, size; |
643 | ||
644 | /* mark memory between memory_start and memory_end usable */ | |
645 | add_memory_region(memory_start, | |
646 | memory_end - memory_start, BFIN_MEMMAP_RAM); | |
647 | /* sanity check for overlap */ | |
648 | sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map); | |
649 | print_memory_map("boot memmap"); | |
650 | ||
2e8d7965 YL |
651 | /* intialize globals in linux/bootmem.h */ |
652 | find_min_max_pfn(); | |
653 | /* pfn of the last usable page frame */ | |
654 | if (max_pfn > memory_end >> PAGE_SHIFT) | |
655 | max_pfn = memory_end >> PAGE_SHIFT; | |
656 | /* pfn of last page frame directly mapped by kernel */ | |
657 | max_low_pfn = max_pfn; | |
658 | /* pfn of the first usable page frame after kernel image*/ | |
659 | if (min_low_pfn < memory_start >> PAGE_SHIFT) | |
660 | min_low_pfn = memory_start >> PAGE_SHIFT; | |
661 | ||
662 | start_pfn = PAGE_OFFSET >> PAGE_SHIFT; | |
663 | end_pfn = memory_end >> PAGE_SHIFT; | |
856783b3 YL |
664 | |
665 | /* | |
8f65873e | 666 | * give all the memory to the bootmap allocator, tell it to put the |
856783b3 YL |
667 | * boot mem_map at the start of memory. |
668 | */ | |
669 | bootmap_size = init_bootmem_node(NODE_DATA(0), | |
670 | memory_start >> PAGE_SHIFT, /* map goes here */ | |
2e8d7965 | 671 | start_pfn, end_pfn); |
856783b3 YL |
672 | |
673 | /* register the memmap regions with the bootmem allocator */ | |
674 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
675 | /* | |
676 | * Reserve usable memory | |
677 | */ | |
678 | if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) | |
679 | continue; | |
680 | /* | |
681 | * We are rounding up the start address of usable memory: | |
682 | */ | |
683 | curr_pfn = PFN_UP(bfin_memmap.map[i].addr); | |
2e8d7965 | 684 | if (curr_pfn >= end_pfn) |
856783b3 YL |
685 | continue; |
686 | /* | |
687 | * ... and at the end of the usable range downwards: | |
688 | */ | |
689 | last_pfn = PFN_DOWN(bfin_memmap.map[i].addr + | |
690 | bfin_memmap.map[i].size); | |
691 | ||
2e8d7965 YL |
692 | if (last_pfn > end_pfn) |
693 | last_pfn = end_pfn; | |
856783b3 YL |
694 | |
695 | /* | |
696 | * .. finally, did all the rounding and playing | |
697 | * around just make the area go away? | |
698 | */ | |
699 | if (last_pfn <= curr_pfn) | |
700 | continue; | |
701 | ||
702 | size = last_pfn - curr_pfn; | |
703 | free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size)); | |
704 | } | |
705 | ||
706 | /* reserve memory before memory_start, including bootmap */ | |
707 | reserve_bootmem(PAGE_OFFSET, | |
708 | memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET, | |
709 | BOOTMEM_DEFAULT); | |
710 | } | |
711 | ||
a086ee22 MF |
712 | #define EBSZ_TO_MEG(ebsz) \ |
713 | ({ \ | |
714 | int meg = 0; \ | |
715 | switch (ebsz & 0xf) { \ | |
716 | case 0x1: meg = 16; break; \ | |
717 | case 0x3: meg = 32; break; \ | |
718 | case 0x5: meg = 64; break; \ | |
719 | case 0x7: meg = 128; break; \ | |
720 | case 0x9: meg = 256; break; \ | |
721 | case 0xb: meg = 512; break; \ | |
722 | } \ | |
723 | meg; \ | |
724 | }) | |
725 | static inline int __init get_mem_size(void) | |
726 | { | |
99d95bbd MH |
727 | #if defined(EBIU_SDBCTL) |
728 | # if defined(BF561_FAMILY) | |
a086ee22 MF |
729 | int ret = 0; |
730 | u32 sdbctl = bfin_read_EBIU_SDBCTL(); | |
731 | ret += EBSZ_TO_MEG(sdbctl >> 0); | |
732 | ret += EBSZ_TO_MEG(sdbctl >> 8); | |
733 | ret += EBSZ_TO_MEG(sdbctl >> 16); | |
734 | ret += EBSZ_TO_MEG(sdbctl >> 24); | |
735 | return ret; | |
99d95bbd | 736 | # else |
a086ee22 | 737 | return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL()); |
99d95bbd MH |
738 | # endif |
739 | #elif defined(EBIU_DDRCTL1) | |
1e78042c MH |
740 | u32 ddrctl = bfin_read_EBIU_DDRCTL1(); |
741 | int ret = 0; | |
742 | switch (ddrctl & 0xc0000) { | |
743 | case DEVSZ_64: ret = 64 / 8; | |
744 | case DEVSZ_128: ret = 128 / 8; | |
745 | case DEVSZ_256: ret = 256 / 8; | |
746 | case DEVSZ_512: ret = 512 / 8; | |
747 | } | |
748 | switch (ddrctl & 0x30000) { | |
749 | case DEVWD_4: ret *= 2; | |
750 | case DEVWD_8: ret *= 2; | |
751 | case DEVWD_16: break; | |
a086ee22 | 752 | } |
b1b154e5 MF |
753 | if ((ddrctl & 0xc000) == 0x4000) |
754 | ret *= 2; | |
1e78042c | 755 | return ret; |
a086ee22 MF |
756 | #endif |
757 | BUG(); | |
758 | } | |
759 | ||
856783b3 YL |
760 | void __init setup_arch(char **cmdline_p) |
761 | { | |
9f8e895d | 762 | unsigned long sclk, cclk; |
856783b3 YL |
763 | |
764 | #ifdef CONFIG_DUMMY_CONSOLE | |
765 | conswitchp = &dummy_con; | |
766 | #endif | |
767 | ||
768 | #if defined(CONFIG_CMDLINE_BOOL) | |
769 | strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line)); | |
770 | command_line[sizeof(command_line) - 1] = 0; | |
771 | #endif | |
772 | ||
773 | /* Keep a copy of command line */ | |
774 | *cmdline_p = &command_line[0]; | |
775 | memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); | |
776 | boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; | |
777 | ||
778 | /* setup memory defaults from the user config */ | |
779 | physical_mem_end = 0; | |
a086ee22 | 780 | _ramend = get_mem_size() * 1024 * 1024; |
856783b3 YL |
781 | |
782 | memset(&bfin_memmap, 0, sizeof(bfin_memmap)); | |
783 | ||
784 | parse_cmdline_early(&command_line[0]); | |
785 | ||
786 | if (physical_mem_end == 0) | |
787 | physical_mem_end = _ramend; | |
788 | ||
789 | memory_setup(); | |
790 | ||
7e64acab MF |
791 | /* Initialize Async memory banks */ |
792 | bfin_write_EBIU_AMBCTL0(AMBCTL0VAL); | |
793 | bfin_write_EBIU_AMBCTL1(AMBCTL1VAL); | |
794 | bfin_write_EBIU_AMGCTL(AMGCTLVAL); | |
795 | #ifdef CONFIG_EBIU_MBSCTLVAL | |
796 | bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL); | |
797 | bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL); | |
798 | bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL); | |
799 | #endif | |
800 | ||
856783b3 YL |
801 | cclk = get_cclk(); |
802 | sclk = get_sclk(); | |
803 | ||
7f3aee3c SZ |
804 | if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk) |
805 | panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK"); | |
856783b3 YL |
806 | |
807 | #ifdef BF561_FAMILY | |
808 | if (ANOMALY_05000266) { | |
809 | bfin_read_IMDMA_D0_IRQ_STATUS(); | |
810 | bfin_read_IMDMA_D1_IRQ_STATUS(); | |
811 | } | |
812 | #endif | |
813 | printk(KERN_INFO "Hardware Trace "); | |
814 | if (bfin_read_TBUFCTL() & 0x1) | |
815 | printk("Active "); | |
816 | else | |
817 | printk("Off "); | |
818 | if (bfin_read_TBUFCTL() & 0x2) | |
819 | printk("and Enabled\n"); | |
820 | else | |
821 | printk("and Disabled\n"); | |
822 | ||
823 | #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH) | |
824 | /* we need to initialize the Flashrom device here since we might | |
825 | * do things with flash early on in the boot | |
826 | */ | |
827 | flash_probe(); | |
828 | #endif | |
829 | ||
76e8fe4d RG |
830 | printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF); |
831 | ||
ed1fb604 MF |
832 | /* Newer parts mirror SWRST bits in SYSCR */ |
833 | #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \ | |
834 | defined(CONFIG_BF538) || defined(CONFIG_BF539) | |
7728ec33 | 835 | _bfin_swrst = bfin_read_SWRST(); |
ed1fb604 MF |
836 | #else |
837 | _bfin_swrst = bfin_read_SYSCR(); | |
838 | #endif | |
7728ec33 | 839 | |
0c7a6b21 RG |
840 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT |
841 | bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT); | |
842 | #endif | |
843 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET | |
844 | bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT); | |
845 | #endif | |
2d200980 | 846 | |
8f65873e GY |
847 | #ifdef CONFIG_SMP |
848 | if (_bfin_swrst & SWRST_DBL_FAULT_A) { | |
849 | #else | |
0c7a6b21 | 850 | if (_bfin_swrst & RESET_DOUBLE) { |
8f65873e | 851 | #endif |
0c7a6b21 RG |
852 | printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); |
853 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | |
854 | /* We assume the crashing kernel, and the current symbol table match */ | |
855 | printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", | |
856 | (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx); | |
857 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr); | |
858 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr); | |
859 | #endif | |
860 | printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", | |
861 | init_retx); | |
862 | } else if (_bfin_swrst & RESET_WDOG) | |
7728ec33 RG |
863 | printk(KERN_INFO "Recovering from Watchdog event\n"); |
864 | else if (_bfin_swrst & RESET_SOFTWARE) | |
865 | printk(KERN_NOTICE "Reset caused by Software reset\n"); | |
866 | ||
972de7d9 | 867 | printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n"); |
de3025f4 JZ |
868 | if (bfin_compiled_revid() == 0xffff) |
869 | printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU); | |
870 | else if (bfin_compiled_revid() == -1) | |
871 | printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU); | |
872 | else | |
873 | printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); | |
e482cad2 RG |
874 | |
875 | if (unlikely(CPUID != bfin_cpuid())) | |
876 | printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", | |
877 | CPU, bfin_cpuid(), bfin_revid()); | |
878 | else { | |
879 | if (bfin_revid() != bfin_compiled_revid()) { | |
880 | if (bfin_compiled_revid() == -1) | |
881 | printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", | |
882 | bfin_revid()); | |
7419a327 | 883 | else if (bfin_compiled_revid() != 0xffff) { |
e482cad2 RG |
884 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", |
885 | bfin_compiled_revid(), bfin_revid()); | |
7419a327 | 886 | if (bfin_compiled_revid() > bfin_revid()) |
d8804adf | 887 | panic("Error: you are missing anomaly workarounds for this rev"); |
7419a327 | 888 | } |
e482cad2 | 889 | } |
da986b9f | 890 | if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) |
e482cad2 RG |
891 | printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", |
892 | CPU, bfin_revid()); | |
de3025f4 | 893 | } |
0c0497c2 | 894 | |
00049522 RG |
895 | /* We can't run on BF548-0.1 due to ANOMALY 05000448 */ |
896 | if (bfin_cpuid() == 0x27de && bfin_revid() == 1) | |
d8804adf | 897 | panic("You can't run on this processor due to 05000448"); |
00049522 | 898 | |
1394f032 BW |
899 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); |
900 | ||
b5c0e2e8 | 901 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", |
8f65873e | 902 | cclk / 1000000, sclk / 1000000); |
1394f032 | 903 | |
856783b3 | 904 | setup_bootmem_allocator(); |
1394f032 | 905 | |
1394f032 BW |
906 | paging_init(); |
907 | ||
7adfb58f BS |
908 | /* Copy atomic sequences to their fixed location, and sanity check that |
909 | these locations are the ones that we advertise to userspace. */ | |
910 | memcpy((void *)FIXED_CODE_START, &fixed_code_start, | |
911 | FIXED_CODE_END - FIXED_CODE_START); | |
912 | BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start | |
913 | != SIGRETURN_STUB - FIXED_CODE_START); | |
914 | BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start | |
915 | != ATOMIC_XCHG32 - FIXED_CODE_START); | |
916 | BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start | |
917 | != ATOMIC_CAS32 - FIXED_CODE_START); | |
918 | BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start | |
919 | != ATOMIC_ADD32 - FIXED_CODE_START); | |
920 | BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start | |
921 | != ATOMIC_SUB32 - FIXED_CODE_START); | |
922 | BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start | |
923 | != ATOMIC_IOR32 - FIXED_CODE_START); | |
924 | BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start | |
925 | != ATOMIC_AND32 - FIXED_CODE_START); | |
926 | BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start | |
927 | != ATOMIC_XOR32 - FIXED_CODE_START); | |
9f336a53 RG |
928 | BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start |
929 | != SAFE_USER_INSTRUCTION - FIXED_CODE_START); | |
29440a2b | 930 | |
8f65873e GY |
931 | #ifdef CONFIG_SMP |
932 | platform_init_cpus(); | |
933 | #endif | |
8be80ed3 | 934 | init_exception_vectors(); |
8f65873e | 935 | bfin_cache_init(); /* Initialize caches for the boot CPU */ |
1394f032 BW |
936 | } |
937 | ||
1394f032 BW |
938 | static int __init topology_init(void) |
939 | { | |
8f65873e GY |
940 | unsigned int cpu; |
941 | /* Record CPU-private information for the boot processor. */ | |
942 | bfin_setup_cpudata(0); | |
6cda2e90 MH |
943 | |
944 | for_each_possible_cpu(cpu) { | |
8f65873e | 945 | register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu); |
6cda2e90 MH |
946 | } |
947 | ||
1394f032 | 948 | return 0; |
1394f032 BW |
949 | } |
950 | ||
951 | subsys_initcall(topology_init); | |
952 | ||
7f1e2f98 MF |
953 | /* Get the input clock frequency */ |
954 | static u_long cached_clkin_hz = CONFIG_CLKIN_HZ; | |
955 | static u_long get_clkin_hz(void) | |
956 | { | |
957 | return cached_clkin_hz; | |
958 | } | |
959 | static int __init early_init_clkin_hz(char *buf) | |
960 | { | |
961 | cached_clkin_hz = simple_strtoul(buf, NULL, 0); | |
508808cd MF |
962 | #ifdef BFIN_KERNEL_CLOCK |
963 | if (cached_clkin_hz != CONFIG_CLKIN_HZ) | |
964 | panic("cannot change clkin_hz when reprogramming clocks"); | |
965 | #endif | |
7f1e2f98 MF |
966 | return 1; |
967 | } | |
968 | early_param("clkin_hz=", early_init_clkin_hz); | |
969 | ||
3a2521fa | 970 | /* Get the voltage input multiplier */ |
52a07812 | 971 | static u_long get_vco(void) |
1394f032 | 972 | { |
e32f55d9 MF |
973 | static u_long cached_vco; |
974 | u_long msel, pll_ctl; | |
1394f032 | 975 | |
e32f55d9 MF |
976 | /* The assumption here is that VCO never changes at runtime. |
977 | * If, someday, we support that, then we'll have to change this. | |
978 | */ | |
979 | if (cached_vco) | |
3a2521fa | 980 | return cached_vco; |
3a2521fa | 981 | |
e32f55d9 | 982 | pll_ctl = bfin_read_PLL_CTL(); |
3a2521fa | 983 | msel = (pll_ctl >> 9) & 0x3F; |
1394f032 BW |
984 | if (0 == msel) |
985 | msel = 64; | |
986 | ||
7f1e2f98 | 987 | cached_vco = get_clkin_hz(); |
3a2521fa MF |
988 | cached_vco >>= (1 & pll_ctl); /* DF bit */ |
989 | cached_vco *= msel; | |
990 | return cached_vco; | |
1394f032 BW |
991 | } |
992 | ||
2f6cf7bf | 993 | /* Get the Core clock */ |
1394f032 BW |
994 | u_long get_cclk(void) |
995 | { | |
e32f55d9 | 996 | static u_long cached_cclk_pll_div, cached_cclk; |
1394f032 | 997 | u_long csel, ssel; |
3a2521fa | 998 | |
1394f032 | 999 | if (bfin_read_PLL_STAT() & 0x1) |
7f1e2f98 | 1000 | return get_clkin_hz(); |
1394f032 BW |
1001 | |
1002 | ssel = bfin_read_PLL_DIV(); | |
3a2521fa MF |
1003 | if (ssel == cached_cclk_pll_div) |
1004 | return cached_cclk; | |
1005 | else | |
1006 | cached_cclk_pll_div = ssel; | |
1007 | ||
1394f032 BW |
1008 | csel = ((ssel >> 4) & 0x03); |
1009 | ssel &= 0xf; | |
1010 | if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */ | |
3a2521fa MF |
1011 | cached_cclk = get_vco() / ssel; |
1012 | else | |
1013 | cached_cclk = get_vco() >> csel; | |
1014 | return cached_cclk; | |
1394f032 | 1015 | } |
1394f032 BW |
1016 | EXPORT_SYMBOL(get_cclk); |
1017 | ||
1018 | /* Get the System clock */ | |
1019 | u_long get_sclk(void) | |
1020 | { | |
e32f55d9 | 1021 | static u_long cached_sclk; |
1394f032 BW |
1022 | u_long ssel; |
1023 | ||
e32f55d9 MF |
1024 | /* The assumption here is that SCLK never changes at runtime. |
1025 | * If, someday, we support that, then we'll have to change this. | |
1026 | */ | |
1027 | if (cached_sclk) | |
1028 | return cached_sclk; | |
1029 | ||
1394f032 | 1030 | if (bfin_read_PLL_STAT() & 0x1) |
7f1e2f98 | 1031 | return get_clkin_hz(); |
1394f032 | 1032 | |
e32f55d9 | 1033 | ssel = bfin_read_PLL_DIV() & 0xf; |
1394f032 BW |
1034 | if (0 == ssel) { |
1035 | printk(KERN_WARNING "Invalid System Clock\n"); | |
1036 | ssel = 1; | |
1037 | } | |
1038 | ||
3a2521fa MF |
1039 | cached_sclk = get_vco() / ssel; |
1040 | return cached_sclk; | |
1394f032 | 1041 | } |
1394f032 BW |
1042 | EXPORT_SYMBOL(get_sclk); |
1043 | ||
2f6cf7bf MF |
1044 | unsigned long sclk_to_usecs(unsigned long sclk) |
1045 | { | |
1754a5d9 MF |
1046 | u64 tmp = USEC_PER_SEC * (u64)sclk; |
1047 | do_div(tmp, get_sclk()); | |
1048 | return tmp; | |
2f6cf7bf MF |
1049 | } |
1050 | EXPORT_SYMBOL(sclk_to_usecs); | |
1051 | ||
1052 | unsigned long usecs_to_sclk(unsigned long usecs) | |
1053 | { | |
1754a5d9 MF |
1054 | u64 tmp = get_sclk() * (u64)usecs; |
1055 | do_div(tmp, USEC_PER_SEC); | |
1056 | return tmp; | |
2f6cf7bf MF |
1057 | } |
1058 | EXPORT_SYMBOL(usecs_to_sclk); | |
1059 | ||
1394f032 BW |
1060 | /* |
1061 | * Get CPU information for use by the procfs. | |
1062 | */ | |
1063 | static int show_cpuinfo(struct seq_file *m, void *v) | |
1064 | { | |
066954a3 | 1065 | char *cpu, *mmu, *fpu, *vendor, *cache; |
1394f032 | 1066 | uint32_t revid; |
275123e8 | 1067 | int cpu_num = *(unsigned int *)v; |
a5f0717e | 1068 | u_long sclk, cclk; |
9de3a0b6 | 1069 | u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; |
275123e8 | 1070 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num); |
1394f032 BW |
1071 | |
1072 | cpu = CPU; | |
1073 | mmu = "none"; | |
1074 | fpu = "none"; | |
1075 | revid = bfin_revid(); | |
1394f032 | 1076 | |
1394f032 | 1077 | sclk = get_sclk(); |
a5f0717e | 1078 | cclk = get_cclk(); |
1394f032 | 1079 | |
73b0c0b0 | 1080 | switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) { |
066954a3 MF |
1081 | case 0xca: |
1082 | vendor = "Analog Devices"; | |
73b0c0b0 RG |
1083 | break; |
1084 | default: | |
066954a3 MF |
1085 | vendor = "unknown"; |
1086 | break; | |
73b0c0b0 | 1087 | } |
1394f032 | 1088 | |
275123e8 | 1089 | seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor); |
e482cad2 RG |
1090 | |
1091 | if (CPUID == bfin_cpuid()) | |
1092 | seq_printf(m, "cpu family\t: 0x%04x\n", CPUID); | |
1093 | else | |
1094 | seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n", | |
1095 | CPUID, bfin_cpuid()); | |
1096 | ||
1097 | seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" | |
1098 | "stepping\t: %d\n", | |
a5f0717e | 1099 | cpu, cclk/1000000, sclk/1000000, |
253bcf4f RG |
1100 | #ifdef CONFIG_MPU |
1101 | "mpu on", | |
1102 | #else | |
1103 | "mpu off", | |
1104 | #endif | |
73b0c0b0 RG |
1105 | revid); |
1106 | ||
1107 | seq_printf(m, "cpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", | |
a5f0717e | 1108 | cclk/1000000, cclk%1000000, |
73b0c0b0 RG |
1109 | sclk/1000000, sclk%1000000); |
1110 | seq_printf(m, "bogomips\t: %lu.%02lu\n" | |
1111 | "Calibration\t: %lu loops\n", | |
8f65873e GY |
1112 | (cpudata->loops_per_jiffy * HZ) / 500000, |
1113 | ((cpudata->loops_per_jiffy * HZ) / 5000) % 100, | |
1114 | (cpudata->loops_per_jiffy * HZ)); | |
73b0c0b0 RG |
1115 | |
1116 | /* Check Cache configutation */ | |
8f65873e | 1117 | switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) { |
1f83b8f1 | 1118 | case ACACHE_BSRAM: |
066954a3 | 1119 | cache = "dbank-A/B\t: cache/sram"; |
1f83b8f1 MF |
1120 | dcache_size = 16; |
1121 | dsup_banks = 1; | |
1122 | break; | |
1123 | case ACACHE_BCACHE: | |
066954a3 | 1124 | cache = "dbank-A/B\t: cache/cache"; |
1f83b8f1 MF |
1125 | dcache_size = 32; |
1126 | dsup_banks = 2; | |
1127 | break; | |
1128 | case ASRAM_BSRAM: | |
066954a3 | 1129 | cache = "dbank-A/B\t: sram/sram"; |
1f83b8f1 MF |
1130 | dcache_size = 0; |
1131 | dsup_banks = 0; | |
1132 | break; | |
1133 | default: | |
066954a3 | 1134 | cache = "unknown"; |
73b0c0b0 RG |
1135 | dcache_size = 0; |
1136 | dsup_banks = 0; | |
1394f032 BW |
1137 | break; |
1138 | } | |
1139 | ||
73b0c0b0 | 1140 | /* Is it turned on? */ |
8f65873e | 1141 | if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) |
73b0c0b0 | 1142 | dcache_size = 0; |
1394f032 | 1143 | |
8f65873e | 1144 | if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB)) |
9de3a0b6 RG |
1145 | icache_size = 0; |
1146 | ||
73b0c0b0 | 1147 | seq_printf(m, "cache size\t: %d KB(L1 icache) " |
27276ba2 | 1148 | "%d KB(L1 dcache%s) %d KB(L2 cache)\n", |
9de3a0b6 | 1149 | icache_size, dcache_size, |
73b0c0b0 | 1150 | #if defined CONFIG_BFIN_WB |
27276ba2 | 1151 | "-wb" |
73b0c0b0 | 1152 | #elif defined CONFIG_BFIN_WT |
27276ba2 | 1153 | "-wt" |
73b0c0b0 | 1154 | #endif |
da27abb7 | 1155 | "", 0); |
73b0c0b0 RG |
1156 | |
1157 | seq_printf(m, "%s\n", cache); | |
1158 | ||
9de3a0b6 RG |
1159 | if (icache_size) |
1160 | seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", | |
1161 | BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES); | |
1162 | else | |
1163 | seq_printf(m, "icache setup\t: off\n"); | |
1164 | ||
1394f032 | 1165 | seq_printf(m, |
73b0c0b0 | 1166 | "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", |
3bebca2d RG |
1167 | dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, |
1168 | BFIN_DLINES); | |
8f65873e | 1169 | #ifdef __ARCH_SYNC_CORE_DCACHE |
275123e8 | 1170 | seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count); |
8f65873e | 1171 | #endif |
3bebca2d | 1172 | #ifdef CONFIG_BFIN_ICACHE_LOCK |
8f65873e | 1173 | switch ((cpudata->imemctl >> 3) & WAYALL_L) { |
1394f032 BW |
1174 | case WAY0_L: |
1175 | seq_printf(m, "Way0 Locked-Down\n"); | |
1176 | break; | |
1177 | case WAY1_L: | |
1178 | seq_printf(m, "Way1 Locked-Down\n"); | |
1179 | break; | |
1180 | case WAY01_L: | |
1181 | seq_printf(m, "Way0,Way1 Locked-Down\n"); | |
1182 | break; | |
1183 | case WAY2_L: | |
1184 | seq_printf(m, "Way2 Locked-Down\n"); | |
1185 | break; | |
1186 | case WAY02_L: | |
1187 | seq_printf(m, "Way0,Way2 Locked-Down\n"); | |
1188 | break; | |
1189 | case WAY12_L: | |
1190 | seq_printf(m, "Way1,Way2 Locked-Down\n"); | |
1191 | break; | |
1192 | case WAY012_L: | |
1193 | seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n"); | |
1194 | break; | |
1195 | case WAY3_L: | |
1196 | seq_printf(m, "Way3 Locked-Down\n"); | |
1197 | break; | |
1198 | case WAY03_L: | |
1199 | seq_printf(m, "Way0,Way3 Locked-Down\n"); | |
1200 | break; | |
1201 | case WAY13_L: | |
1202 | seq_printf(m, "Way1,Way3 Locked-Down\n"); | |
1203 | break; | |
1204 | case WAY013_L: | |
1205 | seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n"); | |
1206 | break; | |
1207 | case WAY32_L: | |
1208 | seq_printf(m, "Way3,Way2 Locked-Down\n"); | |
1209 | break; | |
1210 | case WAY320_L: | |
1211 | seq_printf(m, "Way3,Way2,Way0 Locked-Down\n"); | |
1212 | break; | |
1213 | case WAY321_L: | |
1214 | seq_printf(m, "Way3,Way2,Way1 Locked-Down\n"); | |
1215 | break; | |
1216 | case WAYALL_L: | |
1217 | seq_printf(m, "All Ways are locked\n"); | |
1218 | break; | |
1219 | default: | |
1220 | seq_printf(m, "No Ways are locked\n"); | |
1221 | } | |
8f65873e | 1222 | #endif |
275123e8 MF |
1223 | |
1224 | if (cpu_num != num_possible_cpus() - 1) | |
8f65873e GY |
1225 | return 0; |
1226 | ||
275123e8 MF |
1227 | if (L2_LENGTH) |
1228 | seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); | |
066954a3 | 1229 | seq_printf(m, "board name\t: %s\n", bfin_board_name); |
73b0c0b0 RG |
1230 | seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", |
1231 | physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); | |
1232 | seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n", | |
1233 | ((int)memory_end - (int)_stext) >> 10, | |
1234 | _stext, | |
1235 | (void *)memory_end); | |
8f65873e | 1236 | seq_printf(m, "\n"); |
73b0c0b0 | 1237 | |
1394f032 BW |
1238 | return 0; |
1239 | } | |
1240 | ||
1241 | static void *c_start(struct seq_file *m, loff_t *pos) | |
1242 | { | |
55f2feae GY |
1243 | if (*pos == 0) |
1244 | *pos = first_cpu(cpu_online_map); | |
1245 | if (*pos >= num_online_cpus()) | |
1246 | return NULL; | |
1247 | ||
1248 | return pos; | |
1394f032 BW |
1249 | } |
1250 | ||
1251 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
1252 | { | |
55f2feae GY |
1253 | *pos = next_cpu(*pos, cpu_online_map); |
1254 | ||
1394f032 BW |
1255 | return c_start(m, pos); |
1256 | } | |
1257 | ||
1258 | static void c_stop(struct seq_file *m, void *v) | |
1259 | { | |
1260 | } | |
1261 | ||
03a44825 | 1262 | const struct seq_operations cpuinfo_op = { |
1394f032 BW |
1263 | .start = c_start, |
1264 | .next = c_next, | |
1265 | .stop = c_stop, | |
1266 | .show = show_cpuinfo, | |
1267 | }; | |
1268 | ||
5e10b4a6 | 1269 | void __init cmdline_init(const char *r0) |
1394f032 BW |
1270 | { |
1271 | if (r0) | |
52a07812 | 1272 | strncpy(command_line, r0, COMMAND_LINE_SIZE); |
1394f032 | 1273 | } |