[net-next-2.6.git] / arch / blackfin / kernel / cplb-nompu / cplbinit.c

/*
 * Blackfin CPLB initialization
 *
 *               Copyright 2004-2007 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/module.h>

#include <asm/blackfin.h>
#include <asm/cacheflush.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>

#define CPLB_MEM CONFIG_MAX_MEM_SIZE

/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* possibly 1 for L2 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
				 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)

/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* possibly 1 for L2 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)


u_long icplb_table[MAX_CPLBS + 1];
u_long dcplb_table[MAX_CPLBS + 1];

#ifdef CONFIG_CPLB_SWITCH_TAB_L1
# define PDT_ATTR __attribute__((l1_data))
#else
# define PDT_ATTR
#endif

u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;

#ifdef CONFIG_CPLB_INFO
u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
#endif

struct s_cplb {
	struct cplb_tab init_i;
	struct cplb_tab init_d;
	struct cplb_tab switch_i;
	struct cplb_tab switch_d;
};

#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
static struct cplb_desc cplb_data[] = {
	{
		.start = 0,
		.end = SIZE_1K,
		.psize = SIZE_1K,
		.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = SDRAM_OOPS,
		.d_conf = SDRAM_OOPS,
#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
		.valid = 1,
#else
		.valid = 0,
#endif
		.name = "Zero Pointer Guard Page",
	},
	{
		.start = L1_CODE_START,
		.end = L1_CODE_START + L1_CODE_LENGTH,
		.psize = SIZE_4M,
		.attr = INITIAL_T | SWITCH_T | I_CPLB,
		.i_conf = L1_IMEMORY,
		.d_conf = 0,
		.valid = 1,
		.name = "L1 I-Memory",
	},
	{
		.start = L1_DATA_A_START,
		.end = L1_DATA_B_START + L1_DATA_B_LENGTH,
		.psize = SIZE_4M,
		.attr = INITIAL_T | SWITCH_T | D_CPLB,
		.i_conf = 0,
		.d_conf = L1_DMEMORY,
#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
		.valid = 1,
#else
		.valid = 0,
#endif
		.name = "L1 D-Memory",
	},
	{
		.start = 0,
		.end = 0,  /* dynamic */
		.psize = 0,
		.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = SDRAM_IGENERIC,
		.d_conf = SDRAM_DGENERIC,
		.valid = 1,
		.name = "Kernel Memory",
	},
	{
		.start = 0, /* dynamic */
		.end = 0, /* dynamic */
		.psize = 0,
		.attr = INITIAL_T | SWITCH_T | D_CPLB,
		.i_conf = SDRAM_IGENERIC,
		.d_conf = SDRAM_DNON_CHBL,
		.valid = 1,
		.name = "uClinux MTD Memory",
	},
	{
		.start = 0, /* dynamic */
		.end = 0,   /* dynamic */
		.psize = SIZE_1M,
		.attr = INITIAL_T | SWITCH_T | D_CPLB,
		.d_conf = SDRAM_DNON_CHBL,
		.valid = 1,
		.name = "Uncached DMA Zone",
	},
	{
		.start = 0, /* dynamic */
		.end = 0, /* dynamic */
		.psize = 0,
		.attr = SWITCH_T | D_CPLB,
		.i_conf = 0, /* dynamic */
		.d_conf = 0, /* dynamic */
		.valid = 1,
		.name = "Reserved Memory",
	},
	{
		.start = ASYNC_BANK0_BASE,
		.end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
		.psize = 0,
		.attr = SWITCH_T | D_CPLB,
		.d_conf = SDRAM_EBIU,
		.valid = 1,
		.name = "Asynchronous Memory Banks",
	},
	{
		.start = L2_START,
		.end = L2_START + L2_LENGTH,
		.psize = SIZE_1M,
		.attr = SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = L2_IMEMORY,
		.d_conf = L2_DMEMORY,
		.valid = (L2_LENGTH > 0),
		.name = "L2 Memory",
	},
	{
		.start = BOOT_ROM_START,
		.end = BOOT_ROM_START + BOOT_ROM_LENGTH,
		.psize = SIZE_1M,
		.attr = SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = SDRAM_IGENERIC,
		.d_conf = SDRAM_DGENERIC,
		.valid = 1,
		.name = "On-Chip BootROM",
	},
};

static u16 __init lock_kernel_check(u32 start, u32 end)
{
	if (start >= (u32)_end || end <= (u32)_stext)
		return 0;

	/* This cplb block overlapped with kernel area. */
	return IN_KERNEL;
}

static unsigned short __init
fill_cplbtab(struct cplb_tab *table,
	     unsigned long start, unsigned long end,
	     unsigned long block_size, unsigned long cplb_data)
{
	int i;

	switch (block_size) {
	case SIZE_4M:
		i = 3;
		break;
	case SIZE_1M:
		i = 2;
		break;
	case SIZE_4K:
		i = 1;
		break;
	case SIZE_1K:
	default:
		i = 0;
		break;
	}

	cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);

	while ((start < end) && (table->pos < table->size)) {

		table->tab[table->pos++] = start;

		if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
			table->tab[table->pos++] =
			    cplb_data | CPLB_LOCK | CPLB_DIRTY;
		else
			table->tab[table->pos++] = cplb_data;

		start += block_size;
	}
	return 0;
}

static unsigned short __init
close_cplbtab(struct cplb_tab *table)
{

	while (table->pos < table->size) {

		table->tab[table->pos++] = 0;
		table->tab[table->pos++] = 0; /* !CPLB_VALID */
	}
	return 0;
}

/* helper function */
static void __init
__fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
{
	if (cplb_data[i].psize) {
		fill_cplbtab(t,
				cplb_data[i].start,
				cplb_data[i].end,
				cplb_data[i].psize,
				cplb_data[i].i_conf);
	} else {
#if defined(CONFIG_BFIN_ICACHE)
		if (ANOMALY_05000263 && i == SDRAM_KERN) {
			fill_cplbtab(t,
					cplb_data[i].start,
					cplb_data[i].end,
					SIZE_4M,
					cplb_data[i].i_conf);
		} else
#endif
		{
			fill_cplbtab(t,
					cplb_data[i].start,
					a_start,
					SIZE_1M,
					cplb_data[i].i_conf);
			fill_cplbtab(t,
					a_start,
					a_end,
					SIZE_4M,
					cplb_data[i].i_conf);
			fill_cplbtab(t, a_end,
					cplb_data[i].end,
					SIZE_1M,
					cplb_data[i].i_conf);
		}
	}
}

static void __init
__fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
{
	if (cplb_data[i].psize) {
		fill_cplbtab(t,
				cplb_data[i].start,
				cplb_data[i].end,
				cplb_data[i].psize,
				cplb_data[i].d_conf);
	} else {
		fill_cplbtab(t,
				cplb_data[i].start,
				a_start, SIZE_1M,
				cplb_data[i].d_conf);
		fill_cplbtab(t, a_start,
				a_end, SIZE_4M,
				cplb_data[i].d_conf);
		fill_cplbtab(t, a_end,
				cplb_data[i].end,
				SIZE_1M,
				cplb_data[i].d_conf);
	}
}

void __init generate_cplb_tables(void)
{

	u16 i, j, process;
	u32 a_start, a_end, as, ae, as_1m;

	struct cplb_tab *t_i = NULL;
	struct cplb_tab *t_d = NULL;
	struct s_cplb cplb;

	printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");

	cplb.init_i.size = MAX_CPLBS;
	cplb.init_d.size = MAX_CPLBS;
	cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
	cplb.switch_d.size = MAX_SWITCH_D_CPLBS;

	cplb.init_i.pos = 0;
	cplb.init_d.pos = 0;
	cplb.switch_i.pos = 0;
	cplb.switch_d.pos = 0;

	cplb.init_i.tab = icplb_table;
	cplb.init_d.tab = dcplb_table;
	cplb.switch_i.tab = ipdt_table;
	cplb.switch_d.tab = dpdt_table;

	cplb_data[SDRAM_KERN].end = memory_end;

#ifdef CONFIG_MTD_UCLINUX
	cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
	cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
	cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
# if defined(CONFIG_ROMFS_FS)
	cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;

	/*
	 * The ROMFS_FS size is often not multiple of 1MB.
	 * This can cause multiple CPLB sets covering the same memory area.
	 * This will then cause multiple CPLB hit exceptions.
	 * Workaround: We ensure a contiguous memory area by extending the kernel
	 * memory section over the mtd section.
	 * For ROMFS_FS memory must be covered with ICPLBs anyways.
	 * So there is no difference between kernel and mtd memory setup.
	 */

	cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
	cplb_data[SDRAM_RAM_MTD].valid = 0;

# endif
#else
	cplb_data[SDRAM_RAM_MTD].valid = 0;
#endif

	cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
	cplb_data[SDRAM_DMAZ].end = _ramend;

	cplb_data[RES_MEM].start = _ramend;
	cplb_data[RES_MEM].end = physical_mem_end;

	if (reserved_mem_dcache_on)
		cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
	else
		cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;

	if (reserved_mem_icache_on)
		cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
	else
		cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;

	for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
		if (!cplb_data[i].valid)
			continue;

		as_1m = cplb_data[i].start % SIZE_1M;

		/* We need to make sure all sections are properly 1M aligned
		 * However between Kernel Memory and the Kernel mtd section, depending on the
		 * rootfs size, there can be overlapping memory areas.
		 */

		if (as_1m && i != L1I_MEM && i != L1D_MEM) {
#ifdef CONFIG_MTD_UCLINUX
			if (i == SDRAM_RAM_MTD) {
				if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
					cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
				else
					cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
			} else
#endif
				printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
				       cplb_data[i].name, cplb_data[i].start);
		}

		as = cplb_data[i].start % SIZE_4M;
		ae = cplb_data[i].end % SIZE_4M;

		if (as)
			a_start = cplb_data[i].start + (SIZE_4M - (as));
		else
			a_start = cplb_data[i].start;

		a_end = cplb_data[i].end - ae;

		for (j = INITIAL_T; j <= SWITCH_T; j++) {

			switch (j) {
			case INITIAL_T:
				if (cplb_data[i].attr & INITIAL_T) {
					t_i = &cplb.init_i;
					t_d = &cplb.init_d;
					process = 1;
				} else
					process = 0;
				break;
			case SWITCH_T:
				if (cplb_data[i].attr & SWITCH_T) {
					t_i = &cplb.switch_i;
					t_d = &cplb.switch_d;
					process = 1;
				} else
					process = 0;
				break;
			default:
					process = 0;
				break;
			}

			if (!process)
				continue;
			if (cplb_data[i].attr & I_CPLB)
				__fill_code_cplbtab(t_i, i, a_start, a_end);

			if (cplb_data[i].attr & D_CPLB)
				__fill_data_cplbtab(t_d, i, a_start, a_end);
		}
	}

/* close tables */

	close_cplbtab(&cplb.init_i);
	close_cplbtab(&cplb.init_d);

	cplb.init_i.tab[cplb.init_i.pos] = -1;
	cplb.init_d.tab[cplb.init_d.pos] = -1;
	cplb.switch_i.tab[cplb.switch_i.pos] = -1;
	cplb.switch_d.tab[cplb.switch_d.pos] = -1;

}

#endif
Commit	Line	Data
29440a2b BS	1	/*
	2	* Blackfin CPLB initialization
	3	*
	4	* Copyright 2004-2007 Analog Devices Inc.
	5	*
	6	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, see the file COPYING, or write
	20	* to the Free Software Foundation, Inc.,
	21	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	22	*/
	23	#include <linux/module.h>
	24
	25	#include <asm/blackfin.h>
04be80ef	26	#include <asm/cacheflush.h>
3bebca2d	27	#include <asm/cplb.h>
29440a2b BS	28	#include <asm/cplbinit.h>
29440a2b BS	29
99d95bbd	30	#define CPLB_MEM CONFIG_MAX_MEM_SIZE
a086ee22	31
0e184c6b MF	32	/*
	33	* Number of required data CPLB switchtable entries
	34	* MEMSIZE / 4 (we mostly install 4M page size CPLBs
	35	* approx 16 for smaller 1MB page size CPLBs for allignment purposes
	36	* 1 for L1 Data Memory
	37	* possibly 1 for L2 Data Memory
	38	* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
	39	* 1 for ASYNC Memory
	40	*/
a086ee22	41	#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
0e184c6b MF	42	+ ASYNC_MEMORY_CPLB_COVERAGE) * 2)
	43
	44	/*
	45	* Number of required instruction CPLB switchtable entries
	46	* MEMSIZE / 4 (we mostly install 4M page size CPLBs
	47	* approx 12 for smaller 1MB page size CPLBs for allignment purposes
	48	* 1 for L1 Instruction Memory
	49	* possibly 1 for L2 Instruction Memory
	50	* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
	51	*/
a086ee22	52	#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
0e184c6b MF	53
0e184c6b MF	54
81a487a5 MF	55	u_long icplb_table[MAX_CPLBS + 1];
81a487a5 MF	56	u_long dcplb_table[MAX_CPLBS + 1];
29440a2b BS	57
29440a2b BS	58	#ifdef CONFIG_CPLB_SWITCH_TAB_L1
81a487a5	59	# define PDT_ATTR __attribute__((l1_data))
29440a2b	60	#else
81a487a5 MF	61	# define PDT_ATTR
81a487a5 MF	62	#endif
29440a2b	63
81a487a5 MF	64	u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
81a487a5 MF	65	u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
29440a2b BS	66
29440a2b BS	67	#ifdef CONFIG_CPLB_INFO
81a487a5 MF	68	u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
	69	u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
	70	#endif
29440a2b BS	71
	72	struct s_cplb {
	73	struct cplb_tab init_i;
	74	struct cplb_tab init_d;
	75	struct cplb_tab switch_i;
	76	struct cplb_tab switch_d;
	77	};
	78
3bebca2d	79	#if defined(CONFIG_BFIN_DCACHE) \|\| defined(CONFIG_BFIN_ICACHE)
29440a2b BS	80	static struct cplb_desc cplb_data[] = {
	81	{
	82	.start = 0,
	83	.end = SIZE_1K,
	84	.psize = SIZE_1K,
	85	.attr = INITIAL_T \| SWITCH_T \| I_CPLB \| D_CPLB,
	86	.i_conf = SDRAM_OOPS,
	87	.d_conf = SDRAM_OOPS,
	88	#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
	89	.valid = 1,
	90	#else
	91	.valid = 0,
	92	#endif
c3a9f435	93	.name = "Zero Pointer Guard Page",
29440a2b BS	94	},
	95	{
	96	.start = L1_CODE_START,
	97	.end = L1_CODE_START + L1_CODE_LENGTH,
	98	.psize = SIZE_4M,
	99	.attr = INITIAL_T \| SWITCH_T \| I_CPLB,
	100	.i_conf = L1_IMEMORY,
	101	.d_conf = 0,
	102	.valid = 1,
	103	.name = "L1 I-Memory",
	104	},
	105	{
	106	.start = L1_DATA_A_START,
	107	.end = L1_DATA_B_START + L1_DATA_B_LENGTH,
	108	.psize = SIZE_4M,
	109	.attr = INITIAL_T \| SWITCH_T \| D_CPLB,
	110	.i_conf = 0,
	111	.d_conf = L1_DMEMORY,
	112	#if ((L1_DATA_A_LENGTH > 0) \|\| (L1_DATA_B_LENGTH > 0))
	113	.valid = 1,
	114	#else
	115	.valid = 0,
	116	#endif
	117	.name = "L1 D-Memory",
	118	},
	119	{
	120	.start = 0,
	121	.end = 0, /* dynamic */
	122	.psize = 0,
	123	.attr = INITIAL_T \| SWITCH_T \| I_CPLB \| D_CPLB,
c3a9f435 MF	124	.i_conf = SDRAM_IGENERIC,
c3a9f435 MF	125	.d_conf = SDRAM_DGENERIC,
29440a2b	126	.valid = 1,
c3a9f435	127	.name = "Kernel Memory",
29440a2b BS	128	},
	129	{
	130	.start = 0, /* dynamic */
	131	.end = 0, /* dynamic */
	132	.psize = 0,
	133	.attr = INITIAL_T \| SWITCH_T \| D_CPLB,
c3a9f435 MF	134	.i_conf = SDRAM_IGENERIC,
c3a9f435 MF	135	.d_conf = SDRAM_DNON_CHBL,
29440a2b	136	.valid = 1,
c3a9f435	137	.name = "uClinux MTD Memory",
29440a2b BS	138	},
	139	{
	140	.start = 0, /* dynamic */
	141	.end = 0, /* dynamic */
	142	.psize = SIZE_1M,
	143	.attr = INITIAL_T \| SWITCH_T \| D_CPLB,
	144	.d_conf = SDRAM_DNON_CHBL,
	145	.valid = 1,
c3a9f435	146	.name = "Uncached DMA Zone",
29440a2b BS	147	},
	148	{
	149	.start = 0, /* dynamic */
	150	.end = 0, /* dynamic */
	151	.psize = 0,
	152	.attr = SWITCH_T \| D_CPLB,
	153	.i_conf = 0, /* dynamic */
	154	.d_conf = 0, /* dynamic */
	155	.valid = 1,
c3a9f435	156	.name = "Reserved Memory",
29440a2b BS	157	},
	158	{
	159	.start = ASYNC_BANK0_BASE,
	160	.end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
	161	.psize = 0,
	162	.attr = SWITCH_T \| D_CPLB,
	163	.d_conf = SDRAM_EBIU,
	164	.valid = 1,
c3a9f435	165	.name = "Asynchronous Memory Banks",
29440a2b BS	166	},
29440a2b BS	167	{
c3a9f435 MF	168	.start = L2_START,
c3a9f435 MF	169	.end = L2_START + L2_LENGTH,
29440a2b	170	.psize = SIZE_1M,
c3a9f435	171	.attr = SWITCH_T \| I_CPLB \| D_CPLB,
f099f39a SZ	172	.i_conf = L2_IMEMORY,
f099f39a SZ	173	.d_conf = L2_DMEMORY,
07aa7be5	174	.valid = (L2_LENGTH > 0),
29440a2b	175	.name = "L2 Memory",
c3a9f435 MF	176	},
	177	{
	178	.start = BOOT_ROM_START,
	179	.end = BOOT_ROM_START + BOOT_ROM_LENGTH,
	180	.psize = SIZE_1M,
	181	.attr = SWITCH_T \| I_CPLB \| D_CPLB,
	182	.i_conf = SDRAM_IGENERIC,
	183	.d_conf = SDRAM_DGENERIC,
	184	.valid = 1,
	185	.name = "On-Chip BootROM",
	186	},
29440a2b BS	187	};
	188
	189	static u16 __init lock_kernel_check(u32 start, u32 end)
	190	{
6776cf44 GY	191	if (start >= (u32)_end \|\| end <= (u32)_stext)
	192	return 0;
	193
	194	/* This cplb block overlapped with kernel area. */
	195	return IN_KERNEL;
29440a2b BS	196	}
	197
	198	static unsigned short __init
	199	fill_cplbtab(struct cplb_tab *table,
	200	unsigned long start, unsigned long end,
	201	unsigned long block_size, unsigned long cplb_data)
	202	{
	203	int i;
	204
	205	switch (block_size) {
	206	case SIZE_4M:
	207	i = 3;
	208	break;
	209	case SIZE_1M:
	210	i = 2;
	211	break;
	212	case SIZE_4K:
	213	i = 1;
	214	break;
	215	case SIZE_1K:
	216	default:
	217	i = 0;
	218	break;
	219	}
	220
	221	cplb_data = (cplb_data & ~(3 << 16)) \| (i << 16);
	222
	223	while ((start < end) && (table->pos < table->size)) {
	224
	225	table->tab[table->pos++] = start;
	226
	227	if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
	228	table->tab[table->pos++] =
	229	cplb_data \| CPLB_LOCK \| CPLB_DIRTY;
	230	else
	231	table->tab[table->pos++] = cplb_data;
	232
	233	start += block_size;
	234	}
	235	return 0;
	236	}
	237
	238	static unsigned short __init
	239	close_cplbtab(struct cplb_tab *table)
	240	{
	241
	242	while (table->pos < table->size) {
	243
	244	table->tab[table->pos++] = 0;
	245	table->tab[table->pos++] = 0; /* !CPLB_VALID */
	246	}
	247	return 0;
	248	}
	249
	250	/* helper function */
8d0a6003 BW	251	static void __init
8d0a6003 BW	252	__fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
29440a2b BS	253	{
	254	if (cplb_data[i].psize) {
	255	fill_cplbtab(t,
	256	cplb_data[i].start,
	257	cplb_data[i].end,
	258	cplb_data[i].psize,
	259	cplb_data[i].i_conf);
	260	} else {
3bebca2d	261	#if defined(CONFIG_BFIN_ICACHE)
1aafd909	262	if (ANOMALY_05000263 && i == SDRAM_KERN) {
29440a2b BS	263	fill_cplbtab(t,
	264	cplb_data[i].start,
	265	cplb_data[i].end,
	266	SIZE_4M,
	267	cplb_data[i].i_conf);
	268	} else
	269	#endif
	270	{
	271	fill_cplbtab(t,
	272	cplb_data[i].start,
	273	a_start,
	274	SIZE_1M,
	275	cplb_data[i].i_conf);
	276	fill_cplbtab(t,
	277	a_start,
	278	a_end,
	279	SIZE_4M,
	280	cplb_data[i].i_conf);
	281	fill_cplbtab(t, a_end,
	282	cplb_data[i].end,
	283	SIZE_1M,
	284	cplb_data[i].i_conf);
	285	}
	286	}
	287	}
	288
8d0a6003 BW	289	static void __init
8d0a6003 BW	290	__fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
29440a2b BS	291	{
	292	if (cplb_data[i].psize) {
	293	fill_cplbtab(t,
	294	cplb_data[i].start,
	295	cplb_data[i].end,
	296	cplb_data[i].psize,
	297	cplb_data[i].d_conf);
	298	} else {
	299	fill_cplbtab(t,
	300	cplb_data[i].start,
	301	a_start, SIZE_1M,
	302	cplb_data[i].d_conf);
	303	fill_cplbtab(t, a_start,
	304	a_end, SIZE_4M,
	305	cplb_data[i].d_conf);
	306	fill_cplbtab(t, a_end,
	307	cplb_data[i].end,
	308	SIZE_1M,
	309	cplb_data[i].d_conf);
	310	}
	311	}
	312
5b04f271	313	void __init generate_cplb_tables(void)
29440a2b BS	314	{
	315
	316	u16 i, j, process;
	317	u32 a_start, a_end, as, ae, as_1m;
	318
	319	struct cplb_tab *t_i = NULL;
	320	struct cplb_tab *t_d = NULL;
	321	struct s_cplb cplb;
	322
8cab0288 MF	323	printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");
8cab0288 MF	324
29440a2b BS	325	cplb.init_i.size = MAX_CPLBS;
	326	cplb.init_d.size = MAX_CPLBS;
	327	cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
	328	cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
	329
	330	cplb.init_i.pos = 0;
	331	cplb.init_d.pos = 0;
	332	cplb.switch_i.pos = 0;
	333	cplb.switch_d.pos = 0;
	334
	335	cplb.init_i.tab = icplb_table;
	336	cplb.init_d.tab = dcplb_table;
	337	cplb.switch_i.tab = ipdt_table;
	338	cplb.switch_d.tab = dpdt_table;
	339
	340	cplb_data[SDRAM_KERN].end = memory_end;
	341
	342	#ifdef CONFIG_MTD_UCLINUX
	343	cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
	344	cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
	345	cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
	346	# if defined(CONFIG_ROMFS_FS)
	347	cplb_data[SDRAM_RAM_MTD].attr \|= I_CPLB;
	348
	349	/*
	350	* The ROMFS_FS size is often not multiple of 1MB.
	351	* This can cause multiple CPLB sets covering the same memory area.
	352	* This will then cause multiple CPLB hit exceptions.
	353	* Workaround: We ensure a contiguous memory area by extending the kernel
	354	* memory section over the mtd section.
	355	* For ROMFS_FS memory must be covered with ICPLBs anyways.
	356	* So there is no difference between kernel and mtd memory setup.
	357	*/
	358
	359	cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
	360	cplb_data[SDRAM_RAM_MTD].valid = 0;
	361
	362	# endif
	363	#else
	364	cplb_data[SDRAM_RAM_MTD].valid = 0;
	365	#endif
	366
	367	cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
	368	cplb_data[SDRAM_DMAZ].end = _ramend;
	369
	370	cplb_data[RES_MEM].start = _ramend;
	371	cplb_data[RES_MEM].end = physical_mem_end;
	372
	373	if (reserved_mem_dcache_on)
	374	cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
	375	else
	376	cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
	377
	378	if (reserved_mem_icache_on)
	379	cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
	380	else
	381	cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
	382
c3a9f435	383	for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
29440a2b BS	384	if (!cplb_data[i].valid)
	385	continue;
	386
	387	as_1m = cplb_data[i].start % SIZE_1M;
	388
	389	/* We need to make sure all sections are properly 1M aligned
	390	* However between Kernel Memory and the Kernel mtd section, depending on the
	391	* rootfs size, there can be overlapping memory areas.
	392	*/
	393
	394	if (as_1m && i != L1I_MEM && i != L1D_MEM) {
	395	#ifdef CONFIG_MTD_UCLINUX
	396	if (i == SDRAM_RAM_MTD) {
	397	if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
	398	cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
	399	else
	400	cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
	401	} else
	402	#endif
	403	printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
	404	cplb_data[i].name, cplb_data[i].start);
	405	}
	406
	407	as = cplb_data[i].start % SIZE_4M;
	408	ae = cplb_data[i].end % SIZE_4M;
	409
	410	if (as)
	411	a_start = cplb_data[i].start + (SIZE_4M - (as));
	412	else
	413	a_start = cplb_data[i].start;
	414
	415	a_end = cplb_data[i].end - ae;
	416
	417	for (j = INITIAL_T; j <= SWITCH_T; j++) {
	418
	419	switch (j) {
	420	case INITIAL_T:
	421	if (cplb_data[i].attr & INITIAL_T) {
	422	t_i = &cplb.init_i;
	423	t_d = &cplb.init_d;
	424	process = 1;
	425	} else
	426	process = 0;
	427	break;
	428	case SWITCH_T:
	429	if (cplb_data[i].attr & SWITCH_T) {
	430	t_i = &cplb.switch_i;
	431	t_d = &cplb.switch_d;
	432	process = 1;
	433	} else
	434	process = 0;
	435	break;
	436	default:
	437	process = 0;
	438	break;
	439	}
	440
	441	if (!process)
	442	continue;
	443	if (cplb_data[i].attr & I_CPLB)
	444	__fill_code_cplbtab(t_i, i, a_start, a_end);
	445
	446	if (cplb_data[i].attr & D_CPLB)
	447	__fill_data_cplbtab(t_d, i, a_start, a_end);
448	}
449	}
450
451	/* close tables */
452
453	close_cplbtab(&cplb.init_i);
454	close_cplbtab(&cplb.init_d);
455
456	cplb.init_i.tab[cplb.init_i.pos] = -1;
457	cplb.init_d.tab[cplb.init_d.pos] = -1;
458	cplb.switch_i.tab[cplb.switch_i.pos] = -1;
459	cplb.switch_d.tab[cplb.switch_d.pos] = -1;
460
461	}
462
463	#endif
464