[net-next-2.6.git] / arch / blackfin / kernel / cplb-mpu / cplbmgr.c

/*
 * Blackfin CPLB exception handling for when MPU in on
 *
 * Copyright 2008-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/mm.h>

#include <asm/blackfin.h>
#include <asm/cacheflush.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>
#include <asm/mmu_context.h>

/*
 * WARNING
 *
 * This file is compiled with certain -ffixed-reg options.  We have to
 * make sure not to call any functions here that could clobber these
 * registers.
 */

int page_mask_nelts;
int page_mask_order;
unsigned long *current_rwx_mask[NR_CPUS];

int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
int nr_cplb_flush[NR_CPUS];

#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
#define MGR_ATTR __attribute__((l1_text))
#else
#define MGR_ATTR
#endif

/*
 * Given the contents of the status register, return the index of the
 * CPLB that caused the fault.
 */
static inline int faulting_cplb_index(int status)
{
	int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
	return 30 - signbits;
}

/*
 * Given the contents of the status register and the DCPLB_DATA contents,
 * return true if a write access should be permitted.
 */
static inline int write_permitted(int status, unsigned long data)
{
	if (status & FAULT_USERSUPV)
		return !!(data & CPLB_SUPV_WR);
	else
		return !!(data & CPLB_USER_WR);
}

/* Counters to implement round-robin replacement.  */
static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];

/*
 * Find an ICPLB entry to be evicted and return its index.
 */
MGR_ATTR static int evict_one_icplb(unsigned int cpu)
{
	int i;
	for (i = first_switched_icplb; i < MAX_CPLBS; i++)
		if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
			return i;
	i = first_switched_icplb + icplb_rr_index[cpu];
	if (i >= MAX_CPLBS) {
		i -= MAX_CPLBS - first_switched_icplb;
		icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
	}
	icplb_rr_index[cpu]++;
	return i;
}

MGR_ATTR static int evict_one_dcplb(unsigned int cpu)
{
	int i;
	for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
		if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
			return i;
	i = first_switched_dcplb + dcplb_rr_index[cpu];
	if (i >= MAX_CPLBS) {
		i -= MAX_CPLBS - first_switched_dcplb;
		dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
	}
	dcplb_rr_index[cpu]++;
	return i;
}

MGR_ATTR static noinline int dcplb_miss(unsigned int cpu)
{
	unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
	int status = bfin_read_DCPLB_STATUS();
	unsigned long *mask;
	int idx;
	unsigned long d_data;

	nr_dcplb_miss[cpu]++;

	d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
	if (bfin_addr_dcacheable(addr)) {
		d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
		d_data |= CPLB_L1_AOW | CPLB_WT;
# endif
	}
#endif

	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
		addr = L2_START;
		d_data = L2_DMEMORY;
	} else if (addr >= physical_mem_end) {
		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
			mask = current_rwx_mask[cpu];
			if (mask) {
				int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
				int idx = page >> 5;
				int bit = 1 << (page & 31);

				if (mask[idx] & bit)
					d_data |= CPLB_USER_RD;
			}
		} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
		    && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
			addr &= ~(1 * 1024 * 1024 - 1);
			d_data &= ~PAGE_SIZE_4KB;
			d_data |= PAGE_SIZE_1MB;
		} else
			return CPLB_PROT_VIOL;
	} else if (addr >= _ramend) {
		d_data |= CPLB_USER_RD | CPLB_USER_WR;
		if (reserved_mem_dcache_on)
			d_data |= CPLB_L1_CHBL;
	} else {
		mask = current_rwx_mask[cpu];
		if (mask) {
			int page = addr >> PAGE_SHIFT;
			int idx = page >> 5;
			int bit = 1 << (page & 31);

			if (mask[idx] & bit)
				d_data |= CPLB_USER_RD;

			mask += page_mask_nelts;
			if (mask[idx] & bit)
				d_data |= CPLB_USER_WR;
		}
	}
	idx = evict_one_dcplb(cpu);

	addr &= PAGE_MASK;
	dcplb_tbl[cpu][idx].addr = addr;
	dcplb_tbl[cpu][idx].data = d_data;

	_disable_dcplb();
	bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
	bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
	_enable_dcplb();

	return 0;
}

MGR_ATTR static noinline int icplb_miss(unsigned int cpu)
{
	unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
	int status = bfin_read_ICPLB_STATUS();
	int idx;
	unsigned long i_data;

	nr_icplb_miss[cpu]++;

	/* If inside the uncached DMA region, fault.  */
	if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
		return CPLB_PROT_VIOL;

	if (status & FAULT_USERSUPV)
		nr_icplb_supv_miss[cpu]++;

	/*
	 * First, try to find a CPLB that matches this address.  If we
	 * find one, then the fact that we're in the miss handler means
	 * that the instruction crosses a page boundary.
	 */
	for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
		if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
			unsigned long this_addr = icplb_tbl[cpu][idx].addr;
			if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
				addr += PAGE_SIZE;
				break;
			}
		}
	}

	i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;

#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
	/*
	 * Normal RAM, and possibly the reserved memory area, are
	 * cacheable.
	 */
	if (addr < _ramend ||
	    (addr < physical_mem_end && reserved_mem_icache_on))
		i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
#endif

	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
		addr = L2_START;
		i_data = L2_IMEMORY;
	} else if (addr >= physical_mem_end) {
		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
			if (!(status & FAULT_USERSUPV)) {
				unsigned long *mask = current_rwx_mask[cpu];

				if (mask) {
					int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
					int idx = page >> 5;
					int bit = 1 << (page & 31);

					mask += 2 * page_mask_nelts;
					if (mask[idx] & bit)
						i_data |= CPLB_USER_RD;
				}
			}
		} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
		    && (status & FAULT_USERSUPV)) {
			addr &= ~(1 * 1024 * 1024 - 1);
			i_data &= ~PAGE_SIZE_4KB;
			i_data |= PAGE_SIZE_1MB;
		} else
		    return CPLB_PROT_VIOL;
	} else if (addr >= _ramend) {
		i_data |= CPLB_USER_RD;
		if (reserved_mem_icache_on)
			i_data |= CPLB_L1_CHBL;
	} else {
		/*
		 * Two cases to distinguish - a supervisor access must
		 * necessarily be for a module page; we grant it
		 * unconditionally (could do better here in the future).
		 * Otherwise, check the x bitmap of the current process.
		 */
		if (!(status & FAULT_USERSUPV)) {
			unsigned long *mask = current_rwx_mask[cpu];

			if (mask) {
				int page = addr >> PAGE_SHIFT;
				int idx = page >> 5;
				int bit = 1 << (page & 31);

				mask += 2 * page_mask_nelts;
				if (mask[idx] & bit)
					i_data |= CPLB_USER_RD;
			}
		}
	}
	idx = evict_one_icplb(cpu);
	addr &= PAGE_MASK;
	icplb_tbl[cpu][idx].addr = addr;
	icplb_tbl[cpu][idx].data = i_data;

	_disable_icplb();
	bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
	bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
	_enable_icplb();

	return 0;
}

MGR_ATTR static noinline int dcplb_protection_fault(unsigned int cpu)
{
	int status = bfin_read_DCPLB_STATUS();

	nr_dcplb_prot[cpu]++;

	if (status & FAULT_RW) {
		int idx = faulting_cplb_index(status);
		unsigned long data = dcplb_tbl[cpu][idx].data;
		if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
		    write_permitted(status, data)) {
			data |= CPLB_DIRTY;
			dcplb_tbl[cpu][idx].data = data;
			bfin_write32(DCPLB_DATA0 + idx * 4, data);
			return 0;
		}
	}
	return CPLB_PROT_VIOL;
}

MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
{
	int cause = seqstat & 0x3f;
	unsigned int cpu = raw_smp_processor_id();
	switch (cause) {
	case 0x23:
		return dcplb_protection_fault(cpu);
	case 0x2C:
		return icplb_miss(cpu);
	case 0x26:
		return dcplb_miss(cpu);
	default:
		return 1;
	}
}

void flush_switched_cplbs(unsigned int cpu)
{
	int i;
	unsigned long flags;

	nr_cplb_flush[cpu]++;

	local_irq_save_hw(flags);
	_disable_icplb();
	for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
		icplb_tbl[cpu][i].data = 0;
		bfin_write32(ICPLB_DATA0 + i * 4, 0);
	}
	_enable_icplb();

	_disable_dcplb();
	for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
		dcplb_tbl[cpu][i].data = 0;
		bfin_write32(DCPLB_DATA0 + i * 4, 0);
	}
	_enable_dcplb();
	local_irq_restore_hw(flags);

}

void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
{
	int i;
	unsigned long addr = (unsigned long)masks;
	unsigned long d_data;
	unsigned long flags;

	if (!masks) {
		current_rwx_mask[cpu] = masks;
		return;
	}

	local_irq_save_hw(flags);
	current_rwx_mask[cpu] = masks;

	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
		addr = L2_START;
		d_data = L2_DMEMORY;
	} else {
		d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
		d_data |= CPLB_L1_CHBL;
# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
		d_data |= CPLB_L1_AOW | CPLB_WT;
# endif
#endif
	}

	_disable_dcplb();
	for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
		dcplb_tbl[cpu][i].addr = addr;
		dcplb_tbl[cpu][i].data = d_data;
		bfin_write32(DCPLB_DATA0 + i * 4, d_data);
		bfin_write32(DCPLB_ADDR0 + i * 4, addr);
		addr += PAGE_SIZE;
	}
	_enable_dcplb();
	local_irq_restore_hw(flags);
}
Commit	Line	Data
b97b8a99	1	/*
96f1050d	2	* Blackfin CPLB exception handling for when MPU in on
b97b8a99	3	*
96f1050d	4	* Copyright 2008-2009 Analog Devices Inc.
b97b8a99	5	*
96f1050d	6	* Licensed under the GPL-2 or later.
b97b8a99	7	*/
96f1050d	8
b97b8a99 BS	9	#include <linux/module.h>
	10	#include <linux/mm.h>
	11
	12	#include <asm/blackfin.h>
a92946bc	13	#include <asm/cacheflush.h>
eb7bd9c4	14	#include <asm/cplb.h>
b97b8a99 BS	15	#include <asm/cplbinit.h>
	16	#include <asm/mmu_context.h>
	17
dbdf20db BS	18	/*
	19	* WARNING
	20	*
	21	* This file is compiled with certain -ffixed-reg options. We have to
	22	* make sure not to call any functions here that could clobber these
	23	* registers.
	24	*/
b97b8a99 BS	25
	26	int page_mask_nelts;
	27	int page_mask_order;
b8a98989	28	unsigned long *current_rwx_mask[NR_CPUS];
b97b8a99	29
b8a98989 GY	30	int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
	31	int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
	32	int nr_cplb_flush[NR_CPUS];
b97b8a99	33
726e9656 BS	34	#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
	35	#define MGR_ATTR __attribute__((l1_text))
	36	#else
	37	#define MGR_ATTR
	38	#endif
	39
b97b8a99 BS	40	/*
	41	* Given the contents of the status register, return the index of the
	42	* CPLB that caused the fault.
	43	*/
	44	static inline int faulting_cplb_index(int status)
	45	{
	46	int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
	47	return 30 - signbits;
	48	}
	49
	50	/*
	51	* Given the contents of the status register and the DCPLB_DATA contents,
	52	* return true if a write access should be permitted.
	53	*/
	54	static inline int write_permitted(int status, unsigned long data)
	55	{
	56	if (status & FAULT_USERSUPV)
	57	return !!(data & CPLB_SUPV_WR);
	58	else
	59	return !!(data & CPLB_USER_WR);
	60	}
	61
	62	/* Counters to implement round-robin replacement. */
b8a98989	63	static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
b97b8a99 BS	64
	65	/*
	66	* Find an ICPLB entry to be evicted and return its index.
	67	*/
726e9656	68	MGR_ATTR static int evict_one_icplb(unsigned int cpu)
b97b8a99 BS	69	{
	70	int i;
	71	for (i = first_switched_icplb; i < MAX_CPLBS; i++)
b8a98989	72	if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
b97b8a99	73	return i;
b8a98989	74	i = first_switched_icplb + icplb_rr_index[cpu];
b97b8a99 BS	75	if (i >= MAX_CPLBS) {
b97b8a99 BS	76	i -= MAX_CPLBS - first_switched_icplb;
b8a98989	77	icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
b97b8a99	78	}
b8a98989	79	icplb_rr_index[cpu]++;
b97b8a99 BS	80	return i;
	81	}
	82
726e9656	83	MGR_ATTR static int evict_one_dcplb(unsigned int cpu)
b97b8a99 BS	84	{
	85	int i;
	86	for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
b8a98989	87	if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
b97b8a99	88	return i;
b8a98989	89	i = first_switched_dcplb + dcplb_rr_index[cpu];
b97b8a99 BS	90	if (i >= MAX_CPLBS) {
b97b8a99 BS	91	i -= MAX_CPLBS - first_switched_dcplb;
b8a98989	92	dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
b97b8a99	93	}
b8a98989	94	dcplb_rr_index[cpu]++;
b97b8a99 BS	95	return i;
	96	}
	97
726e9656	98	MGR_ATTR static noinline int dcplb_miss(unsigned int cpu)
b97b8a99 BS	99	{
	100	unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
	101	int status = bfin_read_DCPLB_STATUS();
	102	unsigned long *mask;
	103	int idx;
	104	unsigned long d_data;
	105
b8a98989	106	nr_dcplb_miss[cpu]++;
b97b8a99 BS	107
b97b8a99 BS	108	d_data = CPLB_SUPV_WR \| CPLB_VALID \| CPLB_DIRTY \| PAGE_SIZE_4KB;
41ba653f	109	#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
67834fa9	110	if (bfin_addr_dcacheable(addr)) {
b4bb68f7	111	d_data \|= CPLB_L1_CHBL \| ANOMALY_05000158_WORKAROUND;
41ba653f	112	# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
b4bb68f7	113	d_data \|= CPLB_L1_AOW \| CPLB_WT;
41ba653f	114	# endif
b97b8a99	115	}
b4bb68f7	116	#endif
41ba653f JZ	117
	118	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
	119	addr = L2_START;
	120	d_data = L2_DMEMORY;
	121	} else if (addr >= physical_mem_end) {
e187837b	122	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
e18e7dd3 BS	123	mask = current_rwx_mask[cpu];
	124	if (mask) {
	125	int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
	126	int idx = page >> 5;
	127	int bit = 1 << (page & 31);
	128
	129	if (mask[idx] & bit)
	130	d_data \|= CPLB_USER_RD;
	131	}
4e354b54 MF	132	} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
	133	&& (status & (FAULT_RW \| FAULT_USERSUPV)) == FAULT_USERSUPV) {
	134	addr &= ~(1 * 1024 * 1024 - 1);
	135	d_data &= ~PAGE_SIZE_4KB;
4bea8b20	136	d_data \|= PAGE_SIZE_1MB;
b4bb68f7 BS	137	} else
b4bb68f7 BS	138	return CPLB_PROT_VIOL;
1ebc723c	139	} else if (addr >= _ramend) {
5792ab2a SZ	140	d_data \|= CPLB_USER_RD \| CPLB_USER_WR;
	141	if (reserved_mem_dcache_on)
	142	d_data \|= CPLB_L1_CHBL;
b4bb68f7	143	} else {
b8a98989	144	mask = current_rwx_mask[cpu];
b4bb68f7 BS	145	if (mask) {
b4bb68f7 BS	146	int page = addr >> PAGE_SHIFT;
b8a98989	147	int idx = page >> 5;
b4bb68f7 BS	148	int bit = 1 << (page & 31);
b4bb68f7 BS	149
b8a98989	150	if (mask[idx] & bit)
b4bb68f7	151	d_data \|= CPLB_USER_RD;
b97b8a99	152
b4bb68f7	153	mask += page_mask_nelts;
b8a98989	154	if (mask[idx] & bit)
b4bb68f7 BS	155	d_data \|= CPLB_USER_WR;
	156	}
	157	}
b8a98989	158	idx = evict_one_dcplb(cpu);
b97b8a99 BS	159
b97b8a99 BS	160	addr &= PAGE_MASK;
b8a98989 GY	161	dcplb_tbl[cpu][idx].addr = addr;
b8a98989 GY	162	dcplb_tbl[cpu][idx].data = d_data;
b97b8a99	163
eb7bd9c4	164	_disable_dcplb();
b97b8a99 BS	165	bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
b97b8a99 BS	166	bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
eb7bd9c4	167	_enable_dcplb();
b97b8a99 BS	168
	169	return 0;
	170	}
	171
726e9656	172	MGR_ATTR static noinline int icplb_miss(unsigned int cpu)
b97b8a99 BS	173	{
	174	unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
	175	int status = bfin_read_ICPLB_STATUS();
	176	int idx;
	177	unsigned long i_data;
	178
b8a98989	179	nr_icplb_miss[cpu]++;
b97b8a99	180
1ebc723c BS	181	/* If inside the uncached DMA region, fault. */
1ebc723c BS	182	if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
b97b8a99 BS	183	return CPLB_PROT_VIOL;
b97b8a99 BS	184
1ebc723c	185	if (status & FAULT_USERSUPV)
b8a98989	186	nr_icplb_supv_miss[cpu]++;
1ebc723c	187
b97b8a99 BS	188	/*
	189	* First, try to find a CPLB that matches this address. If we
	190	* find one, then the fact that we're in the miss handler means
	191	* that the instruction crosses a page boundary.
	192	*/
	193	for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
b8a98989 GY	194	if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
b8a98989 GY	195	unsigned long this_addr = icplb_tbl[cpu][idx].addr;
b97b8a99 BS	196	if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
	197	addr += PAGE_SIZE;
	198	break;
	199	}
	200	}
	201	}
	202
	203	i_data = CPLB_VALID \| CPLB_PORTPRIO \| PAGE_SIZE_4KB;
b97b8a99	204
41ba653f	205	#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
b97b8a99	206	/*
1ebc723c BS	207	* Normal RAM, and possibly the reserved memory area, are
1ebc723c BS	208	* cacheable.
b97b8a99	209	*/
1ebc723c BS	210	if (addr < _ramend \|\|
	211	(addr < physical_mem_end && reserved_mem_icache_on))
	212	i_data \|= CPLB_L1_CHBL \| ANOMALY_05000158_WORKAROUND;
	213	#endif
b97b8a99	214
41ba653f JZ	215	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
	216	addr = L2_START;
	217	i_data = L2_IMEMORY;
	218	} else if (addr >= physical_mem_end) {
e187837b	219	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
e18e7dd3 BS	220	if (!(status & FAULT_USERSUPV)) {
	221	unsigned long *mask = current_rwx_mask[cpu];
	222
	223	if (mask) {
	224	int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
	225	int idx = page >> 5;
	226	int bit = 1 << (page & 31);
	227
	228	mask += 2 * page_mask_nelts;
	229	if (mask[idx] & bit)
	230	i_data \|= CPLB_USER_RD;
	231	}
	232	}
e187837b	233	} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
4bea8b20 MF	234	&& (status & FAULT_USERSUPV)) {
	235	addr &= ~(1 * 1024 * 1024 - 1);
	236	i_data &= ~PAGE_SIZE_4KB;
	237	i_data \|= PAGE_SIZE_1MB;
	238	} else
	239	return CPLB_PROT_VIOL;
1ebc723c BS	240	} else if (addr >= _ramend) {
1ebc723c BS	241	i_data \|= CPLB_USER_RD;
5792ab2a SZ	242	if (reserved_mem_icache_on)
5792ab2a SZ	243	i_data \|= CPLB_L1_CHBL;
1ebc723c BS	244	} else {
	245	/*
	246	* Two cases to distinguish - a supervisor access must
	247	* necessarily be for a module page; we grant it
	248	* unconditionally (could do better here in the future).
	249	* Otherwise, check the x bitmap of the current process.
	250	*/
	251	if (!(status & FAULT_USERSUPV)) {
b8a98989	252	unsigned long *mask = current_rwx_mask[cpu];
1ebc723c BS	253
	254	if (mask) {
	255	int page = addr >> PAGE_SHIFT;
b8a98989	256	int idx = page >> 5;
1ebc723c BS	257	int bit = 1 << (page & 31);
	258
	259	mask += 2 * page_mask_nelts;
b8a98989	260	if (mask[idx] & bit)
1ebc723c BS	261	i_data \|= CPLB_USER_RD;
1ebc723c BS	262	}
b97b8a99 BS	263	}
b97b8a99 BS	264	}
b8a98989	265	idx = evict_one_icplb(cpu);
b97b8a99	266	addr &= PAGE_MASK;
b8a98989 GY	267	icplb_tbl[cpu][idx].addr = addr;
b8a98989 GY	268	icplb_tbl[cpu][idx].data = i_data;
b97b8a99	269
eb7bd9c4	270	_disable_icplb();
b97b8a99 BS	271	bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
b97b8a99 BS	272	bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
eb7bd9c4	273	_enable_icplb();
b97b8a99 BS	274
	275	return 0;
	276	}
	277
726e9656	278	MGR_ATTR static noinline int dcplb_protection_fault(unsigned int cpu)
b97b8a99	279	{
b97b8a99 BS	280	int status = bfin_read_DCPLB_STATUS();
b97b8a99 BS	281
b8a98989	282	nr_dcplb_prot[cpu]++;
b97b8a99 BS	283
	284	if (status & FAULT_RW) {
	285	int idx = faulting_cplb_index(status);
b8a98989	286	unsigned long data = dcplb_tbl[cpu][idx].data;
b97b8a99 BS	287	if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
	288	write_permitted(status, data)) {
	289	data \|= CPLB_DIRTY;
b8a98989	290	dcplb_tbl[cpu][idx].data = data;
b97b8a99 BS	291	bfin_write32(DCPLB_DATA0 + idx * 4, data);
	292	return 0;
	293	}
	294	}
	295	return CPLB_PROT_VIOL;
	296	}
	297
726e9656	298	MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
b97b8a99 BS	299	{
b97b8a99 BS	300	int cause = seqstat & 0x3f;
b6dbde27	301	unsigned int cpu = raw_smp_processor_id();
b97b8a99 BS	302	switch (cause) {
b97b8a99 BS	303	case 0x23:
b8a98989	304	return dcplb_protection_fault(cpu);
b97b8a99	305	case 0x2C:
b8a98989	306	return icplb_miss(cpu);
b97b8a99	307	case 0x26:
b8a98989	308	return dcplb_miss(cpu);
b97b8a99	309	default:
b4bb68f7	310	return 1;
b97b8a99 BS	311	}
	312	}
	313
b8a98989	314	void flush_switched_cplbs(unsigned int cpu)
b97b8a99 BS	315	{
b97b8a99 BS	316	int i;
5d2e3213	317	unsigned long flags;
b97b8a99	318
b8a98989	319	nr_cplb_flush[cpu]++;
b97b8a99	320
6a01f230	321	local_irq_save_hw(flags);
eb7bd9c4	322	_disable_icplb();
b97b8a99	323	for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
b8a98989	324	icplb_tbl[cpu][i].data = 0;
b97b8a99 BS	325	bfin_write32(ICPLB_DATA0 + i * 4, 0);
b97b8a99 BS	326	}
eb7bd9c4	327	_enable_icplb();
b97b8a99	328
eb7bd9c4	329	_disable_dcplb();
d56daae9	330	for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
b8a98989	331	dcplb_tbl[cpu][i].data = 0;
b97b8a99 BS	332	bfin_write32(DCPLB_DATA0 + i * 4, 0);
b97b8a99 BS	333	}
eb7bd9c4	334	_enable_dcplb();
6a01f230	335	local_irq_restore_hw(flags);
5d2e3213	336
b97b8a99 BS	337	}
b97b8a99 BS	338
b8a98989	339	void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
b97b8a99 BS	340	{
	341	int i;
	342	unsigned long addr = (unsigned long)masks;
	343	unsigned long d_data;
5d2e3213	344	unsigned long flags;
b97b8a99	345
5d2e3213	346	if (!masks) {
b8a98989	347	current_rwx_mask[cpu] = masks;
b97b8a99	348	return;
5d2e3213 BS	349	}
5d2e3213 BS	350
6a01f230	351	local_irq_save_hw(flags);
b8a98989	352	current_rwx_mask[cpu] = masks;
b97b8a99	353
41ba653f JZ	354	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
	355	addr = L2_START;
	356	d_data = L2_DMEMORY;
	357	} else {
	358	d_data = CPLB_SUPV_WR \| CPLB_VALID \| CPLB_DIRTY \| PAGE_SIZE_4KB;
	359	#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
	360	d_data \|= CPLB_L1_CHBL;
	361	# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
	362	d_data \|= CPLB_L1_AOW \| CPLB_WT;
	363	# endif
b97b8a99	364	#endif
41ba653f	365	}
b97b8a99	366
eb7bd9c4	367	_disable_dcplb();
b97b8a99	368	for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
b8a98989 GY	369	dcplb_tbl[cpu][i].addr = addr;
b8a98989 GY	370	dcplb_tbl[cpu][i].data = d_data;
b97b8a99 BS	371	bfin_write32(DCPLB_DATA0 + i * 4, d_data);
	372	bfin_write32(DCPLB_ADDR0 + i * 4, addr);
	373	addr += PAGE_SIZE;
	374	}
eb7bd9c4	375	_enable_dcplb();
6a01f230	376	local_irq_restore_hw(flags);
b97b8a99	377	}