[net-next-2.6.git] / arch / blackfin / kernel / cplb-mpu / cplbinit.c

/*
 * Blackfin CPLB initialization
 *
 *               Copyright 2004-2007 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/module.h>

#include <asm/blackfin.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>

#if ANOMALY_05000263
# error the MPU will not function safely while Anomaly 05000263 applies
#endif

struct cplb_entry icplb_tbl[MAX_CPLBS];
struct cplb_entry dcplb_tbl[MAX_CPLBS];

int first_switched_icplb, first_switched_dcplb;
int first_mask_dcplb;

void __init generate_cplb_tables(void)
{
	int i_d, i_i;
	unsigned long addr;
	unsigned long d_data, i_data;
	unsigned long d_cache = 0, i_cache = 0;

	printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");

#ifdef CONFIG_BFIN_ICACHE
	i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
#endif

#ifdef CONFIG_BFIN_DCACHE
	d_cache = CPLB_L1_CHBL;
#ifdef CONFIG_BFIN_WT
	d_cache |= CPLB_L1_AOW | CPLB_WT;
#endif
#endif
	i_d = i_i = 0;

	/* Set up the zero page.  */
	dcplb_tbl[i_d].addr = 0;
	dcplb_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;

#if 0
	icplb_tbl[i_i].addr = 0;
	icplb_tbl[i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
#endif

	/* Cover kernel memory with 4M pages.  */
	addr = 0;
	d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
	i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;

	for (; addr < memory_start; addr += 4 * 1024 * 1024) {
		dcplb_tbl[i_d].addr = addr;
		dcplb_tbl[i_d++].data = d_data;
		icplb_tbl[i_i].addr = addr;
		icplb_tbl[i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
	}

	/* Cover L1 memory.  One 4M area for code and data each is enough.  */
#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
	dcplb_tbl[i_d].addr = L1_DATA_A_START;
	dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
#endif
#if L1_CODE_LENGTH > 0
	icplb_tbl[i_i].addr = L1_CODE_START;
	icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
#endif

	/* Cover L2 memory */
#if L2_LENGTH > 0
	dcplb_tbl[i_d].addr = L2_START;
	dcplb_tbl[i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
	icplb_tbl[i_i].addr = L2_START;
	icplb_tbl[i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
#endif

	first_mask_dcplb = i_d;
	first_switched_dcplb = i_d + (1 << page_mask_order);
	first_switched_icplb = i_i;

	while (i_d < MAX_CPLBS)
		dcplb_tbl[i_d++].data = 0;
	while (i_i < MAX_CPLBS)
		icplb_tbl[i_i++].data = 0;
}
Commit	Line	Data
b97b8a99 BS	1	/*
	2	* Blackfin CPLB initialization
	3	*
	4	* Copyright 2004-2007 Analog Devices Inc.
	5	*
	6	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, see the file COPYING, or write
	20	* to the Free Software Foundation, Inc.,
	21	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	22	*/
	23	#include <linux/module.h>
	24
	25	#include <asm/blackfin.h>
	26	#include <asm/cplb.h>
	27	#include <asm/cplbinit.h>
	28
c605999b MF	29	#if ANOMALY_05000263
	30	# error the MPU will not function safely while Anomaly 05000263 applies
	31	#endif
	32
b97b8a99 BS	33	struct cplb_entry icplb_tbl[MAX_CPLBS];
	34	struct cplb_entry dcplb_tbl[MAX_CPLBS];
	35
	36	int first_switched_icplb, first_switched_dcplb;
	37	int first_mask_dcplb;
	38
5b04f271	39	void __init generate_cplb_tables(void)
b97b8a99 BS	40	{
	41	int i_d, i_i;
	42	unsigned long addr;
	43	unsigned long d_data, i_data;
	44	unsigned long d_cache = 0, i_cache = 0;
	45
8cab0288 MF	46	printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
8cab0288 MF	47
b97b8a99 BS	48	#ifdef CONFIG_BFIN_ICACHE
	49	i_cache = CPLB_L1_CHBL \| ANOMALY_05000158_WORKAROUND;
	50	#endif
	51
	52	#ifdef CONFIG_BFIN_DCACHE
	53	d_cache = CPLB_L1_CHBL;
dbfe44f0	54	#ifdef CONFIG_BFIN_WT
b97b8a99 BS	55	d_cache \|= CPLB_L1_AOW \| CPLB_WT;
	56	#endif
	57	#endif
	58	i_d = i_i = 0;
	59
	60	/* Set up the zero page. */
	61	dcplb_tbl[i_d].addr = 0;
	62	dcplb_tbl[i_d++].data = SDRAM_OOPS \| PAGE_SIZE_1KB;
	63
	64	#if 0
	65	icplb_tbl[i_i].addr = 0;
	66	icplb_tbl[i_i++].data = i_cache \| CPLB_USER_RD \| PAGE_SIZE_4KB;
	67	#endif
	68
	69	/* Cover kernel memory with 4M pages. */
	70	addr = 0;
	71	d_data = d_cache \| CPLB_SUPV_WR \| CPLB_VALID \| PAGE_SIZE_4MB \| CPLB_DIRTY;
	72	i_data = i_cache \| CPLB_VALID \| CPLB_PORTPRIO \| PAGE_SIZE_4MB;
	73
	74	for (; addr < memory_start; addr += 4 * 1024 * 1024) {
	75	dcplb_tbl[i_d].addr = addr;
	76	dcplb_tbl[i_d++].data = d_data;
	77	icplb_tbl[i_i].addr = addr;
	78	icplb_tbl[i_i++].data = i_data \| (addr == 0 ? CPLB_USER_RD : 0);
	79	}
	80
	81	/* Cover L1 memory. One 4M area for code and data each is enough. */
	82	#if L1_DATA_A_LENGTH > 0 \|\| L1_DATA_B_LENGTH > 0
	83	dcplb_tbl[i_d].addr = L1_DATA_A_START;
	84	dcplb_tbl[i_d++].data = L1_DMEMORY \| PAGE_SIZE_4MB;
	85	#endif
f099f39a	86	#if L1_CODE_LENGTH > 0
b97b8a99 BS	87	icplb_tbl[i_i].addr = L1_CODE_START;
b97b8a99 BS	88	icplb_tbl[i_i++].data = L1_IMEMORY \| PAGE_SIZE_4MB;
f099f39a SZ	89	#endif
	90
	91	/* Cover L2 memory */
	92	#if L2_LENGTH > 0
	93	dcplb_tbl[i_d].addr = L2_START;
	94	dcplb_tbl[i_d++].data = L2_DMEMORY \| PAGE_SIZE_1MB;
	95	icplb_tbl[i_i].addr = L2_START;
	96	icplb_tbl[i_i++].data = L2_IMEMORY \| PAGE_SIZE_1MB;
	97	#endif
b97b8a99 BS	98
	99	first_mask_dcplb = i_d;
	100	first_switched_dcplb = i_d + (1 << page_mask_order);
	101	first_switched_icplb = i_i;
	102
	103	while (i_d < MAX_CPLBS)
	104	dcplb_tbl[i_d++].data = 0;
	105	while (i_i < MAX_CPLBS)
	106	icplb_tbl[i_i++].data = 0;
	107	}