[net-next-2.6.git] / arch / blackfin / include / asm / cache.h

/*
 * include/asm-blackfin/cache.h
 */
#ifndef __ARCH_BLACKFIN_CACHE_H
#define __ARCH_BLACKFIN_CACHE_H

/*
 * Bytes per L1 cache line
 * Blackfin loads 32 bytes for cache
 */
#define L1_CACHE_SHIFT	5
#define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
#define SMP_CACHE_BYTES	L1_CACHE_BYTES

#ifdef CONFIG_SMP
#define __cacheline_aligned
#else
#define ____cacheline_aligned

/*
 * Put cacheline_aliged data to L1 data memory
 */
#ifdef CONFIG_CACHELINE_ALIGNED_L1
#define __cacheline_aligned				\
	  __attribute__((__aligned__(L1_CACHE_BYTES),	\
		__section__(".data_l1.cacheline_aligned")))
#endif

#endif

/*
 * largest L1 which this arch supports
 */
#define L1_CACHE_SHIFT_MAX	5

#if defined(CONFIG_SMP) && \
    !defined(CONFIG_BFIN_CACHE_COHERENT)
# if defined(CONFIG_BFIN_ICACHE)
# define __ARCH_SYNC_CORE_ICACHE
# endif
# if defined(CONFIG_BFIN_DCACHE)
# define __ARCH_SYNC_CORE_DCACHE
# endif
#ifndef __ASSEMBLY__
asmlinkage void __raw_smp_mark_barrier_asm(void);
asmlinkage void __raw_smp_check_barrier_asm(void);

static inline void smp_mark_barrier(void)
{
	__raw_smp_mark_barrier_asm();
}
static inline void smp_check_barrier(void)
{
	__raw_smp_check_barrier_asm();
}

void resync_core_dcache(void);
void resync_core_icache(void);
#endif
#endif


#endif
Commit	Line	Data
1394f032 BW	1	/*
	2	* include/asm-blackfin/cache.h
	3	*/
	4	#ifndef __ARCH_BLACKFIN_CACHE_H
	5	#define __ARCH_BLACKFIN_CACHE_H
	6
	7	/*
	8	* Bytes per L1 cache line
	9	* Blackfin loads 32 bytes for cache
	10	*/
	11	#define L1_CACHE_SHIFT 5
	12	#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
	13	#define SMP_CACHE_BYTES L1_CACHE_BYTES
	14
6b3087c6 GY	15	#ifdef CONFIG_SMP
	16	#define __cacheline_aligned
	17	#else
	18	#define ____cacheline_aligned
	19
1394f032 BW	20	/*
	21	* Put cacheline_aliged data to L1 data memory
	22	*/
	23	#ifdef CONFIG_CACHELINE_ALIGNED_L1
	24	#define __cacheline_aligned \
	25	__attribute__((__aligned__(L1_CACHE_BYTES), \
	26	__section__(".data_l1.cacheline_aligned")))
	27	#endif
	28
6b3087c6 GY	29	#endif
6b3087c6 GY	30
1394f032 BW	31	/*
	32	* largest L1 which this arch supports
	33	*/
	34	#define L1_CACHE_SHIFT_MAX 5
	35
6b3087c6	36	#if defined(CONFIG_SMP) && \
47e9dedb SZ	37	!defined(CONFIG_BFIN_CACHE_COHERENT)
	38	# if defined(CONFIG_BFIN_ICACHE)
	39	# define __ARCH_SYNC_CORE_ICACHE
	40	# endif
	41	# if defined(CONFIG_BFIN_DCACHE)
	42	# define __ARCH_SYNC_CORE_DCACHE
	43	# endif
6b3087c6 GY	44	#ifndef __ASSEMBLY__
	45	asmlinkage void __raw_smp_mark_barrier_asm(void);
	46	asmlinkage void __raw_smp_check_barrier_asm(void);
	47
	48	static inline void smp_mark_barrier(void)
	49	{
	50	__raw_smp_mark_barrier_asm();
	51	}
	52	static inline void smp_check_barrier(void)
	53	{
	54	__raw_smp_check_barrier_asm();
	55	}
	56
	57	void resync_core_dcache(void);
47e9dedb	58	void resync_core_icache(void);
6b3087c6 GY	59	#endif
	60	#endif
	61
	62
1394f032	63	#endif