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Commit | Line | Data |
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1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 | 7 | |
9e1b9b80 AJ |
8 | config SYMBOL_PREFIX |
9 | string | |
10 | default "_" | |
11 | ||
1394f032 | 12 | config MMU |
bac7d89e | 13 | def_bool n |
1394f032 BW |
14 | |
15 | config FPU | |
bac7d89e | 16 | def_bool n |
1394f032 BW |
17 | |
18 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 19 | def_bool y |
1394f032 BW |
20 | |
21 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 22 | def_bool n |
1394f032 BW |
23 | |
24 | config BLACKFIN | |
bac7d89e | 25 | def_bool y |
1ee76d7e | 26 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 27 | select HAVE_FUNCTION_TRACER |
aebfef03 | 28 | select HAVE_FUNCTION_TRACE_MCOUNT_TEST |
ec7748b5 | 29 | select HAVE_IDE |
d86bfb16 BS |
30 | select HAVE_KERNEL_GZIP if RAMKERNEL |
31 | select HAVE_KERNEL_BZIP2 if RAMKERNEL | |
32 | select HAVE_KERNEL_LZMA if RAMKERNEL | |
42d4b839 | 33 | select HAVE_OPROFILE |
a4f0b32c | 34 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 35 | |
ddf9ddac MF |
36 | config GENERIC_CSUM |
37 | def_bool y | |
38 | ||
70f12567 MF |
39 | config GENERIC_BUG |
40 | def_bool y | |
41 | depends on BUG | |
42 | ||
e3defffe | 43 | config ZONE_DMA |
bac7d89e | 44 | def_bool y |
e3defffe | 45 | |
1394f032 | 46 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 47 | def_bool y |
1394f032 | 48 | |
1394f032 | 49 | config GENERIC_HARDIRQS |
bac7d89e | 50 | def_bool y |
1394f032 BW |
51 | |
52 | config GENERIC_IRQ_PROBE | |
bac7d89e | 53 | def_bool y |
1394f032 | 54 | |
796dada9 MH |
55 | config GENERIC_HARDIRQS_NO__DO_IRQ |
56 | def_bool y | |
57 | ||
b2d1583f | 58 | config GENERIC_GPIO |
bac7d89e | 59 | def_bool y |
1394f032 BW |
60 | |
61 | config FORCE_MAX_ZONEORDER | |
62 | int | |
63 | default "14" | |
64 | ||
65 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 66 | def_bool y |
1394f032 | 67 | |
6fa68e7a MF |
68 | config LOCKDEP_SUPPORT |
69 | def_bool y | |
70 | ||
c7b412f4 MF |
71 | config STACKTRACE_SUPPORT |
72 | def_bool y | |
73 | ||
8f86001f MF |
74 | config TRACE_IRQFLAGS_SUPPORT |
75 | def_bool y | |
1394f032 | 76 | |
1394f032 | 77 | source "init/Kconfig" |
dc52ddc0 | 78 | |
1394f032 BW |
79 | source "kernel/Kconfig.preempt" |
80 | ||
dc52ddc0 MH |
81 | source "kernel/Kconfig.freezer" |
82 | ||
1394f032 BW |
83 | menu "Blackfin Processor Options" |
84 | ||
85 | comment "Processor and Board Settings" | |
86 | ||
87 | choice | |
88 | prompt "CPU" | |
89 | default BF533 | |
90 | ||
2f6f4bcd BW |
91 | config BF512 |
92 | bool "BF512" | |
93 | help | |
94 | BF512 Processor Support. | |
95 | ||
96 | config BF514 | |
97 | bool "BF514" | |
98 | help | |
99 | BF514 Processor Support. | |
100 | ||
101 | config BF516 | |
102 | bool "BF516" | |
103 | help | |
104 | BF516 Processor Support. | |
105 | ||
106 | config BF518 | |
107 | bool "BF518" | |
108 | help | |
109 | BF518 Processor Support. | |
110 | ||
59003145 MH |
111 | config BF522 |
112 | bool "BF522" | |
113 | help | |
114 | BF522 Processor Support. | |
115 | ||
1545a111 MF |
116 | config BF523 |
117 | bool "BF523" | |
118 | help | |
119 | BF523 Processor Support. | |
120 | ||
121 | config BF524 | |
122 | bool "BF524" | |
123 | help | |
124 | BF524 Processor Support. | |
125 | ||
59003145 MH |
126 | config BF525 |
127 | bool "BF525" | |
128 | help | |
129 | BF525 Processor Support. | |
130 | ||
1545a111 MF |
131 | config BF526 |
132 | bool "BF526" | |
133 | help | |
134 | BF526 Processor Support. | |
135 | ||
59003145 MH |
136 | config BF527 |
137 | bool "BF527" | |
138 | help | |
139 | BF527 Processor Support. | |
140 | ||
1394f032 BW |
141 | config BF531 |
142 | bool "BF531" | |
143 | help | |
144 | BF531 Processor Support. | |
145 | ||
146 | config BF532 | |
147 | bool "BF532" | |
148 | help | |
149 | BF532 Processor Support. | |
150 | ||
151 | config BF533 | |
152 | bool "BF533" | |
153 | help | |
154 | BF533 Processor Support. | |
155 | ||
156 | config BF534 | |
157 | bool "BF534" | |
158 | help | |
159 | BF534 Processor Support. | |
160 | ||
161 | config BF536 | |
162 | bool "BF536" | |
163 | help | |
164 | BF536 Processor Support. | |
165 | ||
166 | config BF537 | |
167 | bool "BF537" | |
168 | help | |
169 | BF537 Processor Support. | |
170 | ||
dc26aec2 MH |
171 | config BF538 |
172 | bool "BF538" | |
173 | help | |
174 | BF538 Processor Support. | |
175 | ||
176 | config BF539 | |
177 | bool "BF539" | |
178 | help | |
179 | BF539 Processor Support. | |
180 | ||
5df326ac | 181 | config BF542_std |
24a07a12 RH |
182 | bool "BF542" |
183 | help | |
184 | BF542 Processor Support. | |
185 | ||
2f89c063 MF |
186 | config BF542M |
187 | bool "BF542m" | |
188 | help | |
189 | BF542 Processor Support. | |
190 | ||
5df326ac | 191 | config BF544_std |
24a07a12 RH |
192 | bool "BF544" |
193 | help | |
194 | BF544 Processor Support. | |
195 | ||
2f89c063 MF |
196 | config BF544M |
197 | bool "BF544m" | |
198 | help | |
199 | BF544 Processor Support. | |
200 | ||
5df326ac | 201 | config BF547_std |
7c7fd170 MF |
202 | bool "BF547" |
203 | help | |
204 | BF547 Processor Support. | |
205 | ||
2f89c063 MF |
206 | config BF547M |
207 | bool "BF547m" | |
208 | help | |
209 | BF547 Processor Support. | |
210 | ||
5df326ac | 211 | config BF548_std |
24a07a12 RH |
212 | bool "BF548" |
213 | help | |
214 | BF548 Processor Support. | |
215 | ||
2f89c063 MF |
216 | config BF548M |
217 | bool "BF548m" | |
218 | help | |
219 | BF548 Processor Support. | |
220 | ||
5df326ac | 221 | config BF549_std |
24a07a12 RH |
222 | bool "BF549" |
223 | help | |
224 | BF549 Processor Support. | |
225 | ||
2f89c063 MF |
226 | config BF549M |
227 | bool "BF549m" | |
228 | help | |
229 | BF549 Processor Support. | |
230 | ||
1394f032 BW |
231 | config BF561 |
232 | bool "BF561" | |
233 | help | |
cd88b4dc | 234 | BF561 Processor Support. |
1394f032 BW |
235 | |
236 | endchoice | |
237 | ||
46fa5eec GY |
238 | config SMP |
239 | depends on BF561 | |
0d152c27 | 240 | select TICKSOURCE_CORETMR |
46fa5eec GY |
241 | bool "Symmetric multi-processing support" |
242 | ---help--- | |
243 | This enables support for systems with more than one CPU, | |
244 | like the dual core BF561. If you have a system with only one | |
245 | CPU, say N. If you have a system with more than one CPU, say Y. | |
246 | ||
247 | If you don't know what to do here, say N. | |
248 | ||
249 | config NR_CPUS | |
250 | int | |
251 | depends on SMP | |
252 | default 2 if BF561 | |
253 | ||
0b39db28 GY |
254 | config HOTPLUG_CPU |
255 | bool "Support for hot-pluggable CPUs" | |
256 | depends on SMP && HOTPLUG | |
257 | default y | |
258 | ||
46fa5eec GY |
259 | config IRQ_PER_CPU |
260 | bool | |
261 | depends on SMP | |
262 | default y | |
263 | ||
ead9b115 GY |
264 | config HAVE_LEGACY_PER_CPU_AREA |
265 | def_bool y | |
266 | depends on SMP | |
267 | ||
0c0497c2 MF |
268 | config BF_REV_MIN |
269 | int | |
2f89c063 | 270 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 271 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 272 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 273 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
274 | |
275 | config BF_REV_MAX | |
276 | int | |
2f89c063 MF |
277 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
278 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 279 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
280 | default 6 if (BF533 || BF532 || BF531) |
281 | ||
1394f032 BW |
282 | choice |
283 | prompt "Silicon Rev" | |
f8b55651 MF |
284 | default BF_REV_0_0 if (BF51x || BF52x) |
285 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 286 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
287 | |
288 | config BF_REV_0_0 | |
289 | bool "0.0" | |
2f89c063 | 290 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
291 | |
292 | config BF_REV_0_1 | |
d07f4380 | 293 | bool "0.1" |
3d15f302 | 294 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
295 | |
296 | config BF_REV_0_2 | |
297 | bool "0.2" | |
2f89c063 | 298 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
299 | |
300 | config BF_REV_0_3 | |
301 | bool "0.3" | |
2f89c063 | 302 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
303 | |
304 | config BF_REV_0_4 | |
305 | bool "0.4" | |
dc26aec2 | 306 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
307 | |
308 | config BF_REV_0_5 | |
309 | bool "0.5" | |
dc26aec2 | 310 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 311 | |
49f7253c MF |
312 | config BF_REV_0_6 |
313 | bool "0.6" | |
314 | depends on (BF533 || BF532 || BF531) | |
315 | ||
de3025f4 JZ |
316 | config BF_REV_ANY |
317 | bool "any" | |
318 | ||
319 | config BF_REV_NONE | |
320 | bool "none" | |
321 | ||
1394f032 BW |
322 | endchoice |
323 | ||
24a07a12 RH |
324 | config BF53x |
325 | bool | |
326 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
327 | default y | |
328 | ||
1394f032 BW |
329 | config MEM_GENERIC_BOARD |
330 | bool | |
331 | depends on GENERIC_BOARD | |
332 | default y | |
333 | ||
334 | config MEM_MT48LC64M4A2FB_7E | |
335 | bool | |
336 | depends on (BFIN533_STAMP) | |
337 | default y | |
338 | ||
339 | config MEM_MT48LC16M16A2TG_75 | |
340 | bool | |
341 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
342 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
343 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
344 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
345 | default y |
346 | ||
347 | config MEM_MT48LC32M8A2_75 | |
348 | bool | |
dc26aec2 | 349 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
350 | default y |
351 | ||
352 | config MEM_MT48LC8M32B2B5_7 | |
353 | bool | |
354 | depends on (BFIN561_BLUETECHNIX_CM) | |
355 | default y | |
356 | ||
59003145 MH |
357 | config MEM_MT48LC32M16A2TG_75 |
358 | bool | |
6924dfb0 | 359 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) |
59003145 MH |
360 | default y |
361 | ||
4934540d SZ |
362 | config MEM_MT48LC32M8A2_75 |
363 | bool | |
364 | depends on (BFIN518F_EZBRD) | |
365 | default y | |
366 | ||
ee48efb5 GY |
367 | config MEM_MT48H32M16LFCJ_75 |
368 | bool | |
369 | depends on (BFIN526_EZBRD) | |
370 | default y | |
371 | ||
2f6f4bcd | 372 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 373 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
374 | source "arch/blackfin/mach-bf533/Kconfig" |
375 | source "arch/blackfin/mach-bf561/Kconfig" | |
376 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 377 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 378 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
379 | |
380 | menu "Board customizations" | |
381 | ||
382 | config CMDLINE_BOOL | |
383 | bool "Default bootloader kernel arguments" | |
384 | ||
385 | config CMDLINE | |
386 | string "Initial kernel command string" | |
387 | depends on CMDLINE_BOOL | |
388 | default "console=ttyBF0,57600" | |
389 | help | |
390 | If you don't have a boot loader capable of passing a command line string | |
391 | to the kernel, you may specify one here. As a minimum, you should specify | |
392 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
393 | ||
5f004c20 MF |
394 | config BOOT_LOAD |
395 | hex "Kernel load address for booting" | |
396 | default "0x1000" | |
397 | range 0x1000 0x20000000 | |
398 | help | |
399 | This option allows you to set the load address of the kernel. | |
400 | This can be useful if you are on a board which has a small amount | |
401 | of memory or you wish to reserve some memory at the beginning of | |
402 | the address space. | |
403 | ||
404 | Note that you need to keep this value above 4k (0x1000) as this | |
405 | memory region is used to capture NULL pointer references as well | |
406 | as some core kernel functions. | |
407 | ||
8cc7117e MH |
408 | config ROM_BASE |
409 | hex "Kernel ROM Base" | |
86249911 | 410 | depends on ROMKERNEL |
d86bfb16 | 411 | default "0x20040040" |
8cc7117e MH |
412 | range 0x20000000 0x20400000 if !(BF54x || BF561) |
413 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
414 | help | |
d86bfb16 BS |
415 | Make sure your ROM base does not include any file-header |
416 | information that is prepended to the kernel. | |
417 | ||
418 | For example, the bootable U-Boot format (created with | |
419 | mkimage) has a 64 byte header (0x40). So while the image | |
420 | you write to flash might start at say 0x20080000, you have | |
421 | to add 0x40 to get the kernel's ROM base as it will come | |
422 | after the header. | |
8cc7117e | 423 | |
f16295e7 | 424 | comment "Clock/PLL Setup" |
1394f032 BW |
425 | |
426 | config CLKIN_HZ | |
2fb6cb41 | 427 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 428 | default "10000000" if BFIN532_IP0X |
1394f032 | 429 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
430 | default "24576000" if PNAV10 |
431 | default "25000000" # most people use this | |
1394f032 | 432 | default "27000000" if BFIN533_EZKIT |
1394f032 | 433 | default "30000000" if BFIN561_EZKIT |
1394f032 BW |
434 | help |
435 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
436 | Warning: This value should match the crystal on the board. Otherwise, |
437 | peripherals won't work properly. | |
1394f032 | 438 | |
f16295e7 RG |
439 | config BFIN_KERNEL_CLOCK |
440 | bool "Re-program Clocks while Kernel boots?" | |
441 | default n | |
442 | help | |
443 | This option decides if kernel clocks are re-programed from the | |
444 | bootloader settings. If the clocks are not set, the SDRAM settings | |
445 | are also not changed, and the Bootloader does 100% of the hardware | |
446 | configuration. | |
447 | ||
448 | config PLL_BYPASS | |
e4e9a7ad MF |
449 | bool "Bypass PLL" |
450 | depends on BFIN_KERNEL_CLOCK | |
451 | default n | |
f16295e7 RG |
452 | |
453 | config CLKIN_HALF | |
454 | bool "Half Clock In" | |
455 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
456 | default n | |
457 | help | |
458 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
459 | ||
460 | config VCO_MULT | |
461 | int "VCO Multiplier" | |
462 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
463 | range 1 64 | |
464 | default "22" if BFIN533_EZKIT | |
465 | default "45" if BFIN533_STAMP | |
6924dfb0 | 466 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 467 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 468 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 469 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 470 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
471 | help |
472 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
473 | PLL Frequency = (Crystal Frequency) * (this setting) | |
474 | ||
475 | choice | |
476 | prompt "Core Clock Divider" | |
477 | depends on BFIN_KERNEL_CLOCK | |
478 | default CCLK_DIV_1 | |
479 | help | |
480 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
481 | Core Frequency = (PLL frequency) / (this setting) | |
482 | ||
483 | config CCLK_DIV_1 | |
484 | bool "1" | |
485 | ||
486 | config CCLK_DIV_2 | |
487 | bool "2" | |
488 | ||
489 | config CCLK_DIV_4 | |
490 | bool "4" | |
491 | ||
492 | config CCLK_DIV_8 | |
493 | bool "8" | |
494 | endchoice | |
495 | ||
496 | config SCLK_DIV | |
497 | int "System Clock Divider" | |
498 | depends on BFIN_KERNEL_CLOCK | |
499 | range 1 15 | |
5f004c20 | 500 | default 5 |
f16295e7 RG |
501 | help |
502 | This sets the frequency of the system clock (including SDRAM or DDR). | |
503 | This can be between 1 and 15 | |
504 | System Clock = (PLL frequency) / (this setting) | |
505 | ||
5f004c20 MF |
506 | choice |
507 | prompt "DDR SDRAM Chip Type" | |
508 | depends on BFIN_KERNEL_CLOCK | |
509 | depends on BF54x | |
510 | default MEM_MT46V32M16_5B | |
511 | ||
512 | config MEM_MT46V32M16_6T | |
513 | bool "MT46V32M16_6T" | |
514 | ||
515 | config MEM_MT46V32M16_5B | |
516 | bool "MT46V32M16_5B" | |
517 | endchoice | |
518 | ||
73feb5c0 MH |
519 | choice |
520 | prompt "DDR/SDRAM Timing" | |
521 | depends on BFIN_KERNEL_CLOCK | |
522 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
523 | help | |
524 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
525 | The calculated SDRAM timing parameters may not be 100% | |
526 | accurate - This option is therefore marked experimental. | |
527 | ||
528 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
529 | bool "Calculate Timings (EXPERIMENTAL)" | |
530 | depends on EXPERIMENTAL | |
531 | ||
532 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
533 | bool "Provide accurate Timings based on target SCLK" | |
534 | help | |
535 | Please consult the Blackfin Hardware Reference Manuals as well | |
536 | as the memory device datasheet. | |
537 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
538 | endchoice | |
539 | ||
540 | menu "Memory Init Control" | |
541 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
542 | ||
543 | config MEM_DDRCTL0 | |
544 | depends on BF54x | |
545 | hex "DDRCTL0" | |
546 | default 0x0 | |
547 | ||
548 | config MEM_DDRCTL1 | |
549 | depends on BF54x | |
550 | hex "DDRCTL1" | |
551 | default 0x0 | |
552 | ||
553 | config MEM_DDRCTL2 | |
554 | depends on BF54x | |
555 | hex "DDRCTL2" | |
556 | default 0x0 | |
557 | ||
558 | config MEM_EBIU_DDRQUE | |
559 | depends on BF54x | |
560 | hex "DDRQUE" | |
561 | default 0x0 | |
562 | ||
563 | config MEM_SDRRC | |
564 | depends on !BF54x | |
565 | hex "SDRRC" | |
566 | default 0x0 | |
567 | ||
568 | config MEM_SDGCTL | |
569 | depends on !BF54x | |
570 | hex "SDGCTL" | |
571 | default 0x0 | |
572 | endmenu | |
573 | ||
f16295e7 RG |
574 | # |
575 | # Max & Min Speeds for various Chips | |
576 | # | |
577 | config MAX_VCO_HZ | |
578 | int | |
2f6f4bcd BW |
579 | default 400000000 if BF512 |
580 | default 400000000 if BF514 | |
581 | default 400000000 if BF516 | |
582 | default 400000000 if BF518 | |
7b06263b MF |
583 | default 400000000 if BF522 |
584 | default 600000000 if BF523 | |
1545a111 | 585 | default 400000000 if BF524 |
f16295e7 | 586 | default 600000000 if BF525 |
1545a111 | 587 | default 400000000 if BF526 |
f16295e7 RG |
588 | default 600000000 if BF527 |
589 | default 400000000 if BF531 | |
590 | default 400000000 if BF532 | |
591 | default 750000000 if BF533 | |
592 | default 500000000 if BF534 | |
593 | default 400000000 if BF536 | |
594 | default 600000000 if BF537 | |
f72eecb9 RG |
595 | default 533333333 if BF538 |
596 | default 533333333 if BF539 | |
f16295e7 | 597 | default 600000000 if BF542 |
f72eecb9 | 598 | default 533333333 if BF544 |
1545a111 MF |
599 | default 600000000 if BF547 |
600 | default 600000000 if BF548 | |
f72eecb9 | 601 | default 533333333 if BF549 |
f16295e7 RG |
602 | default 600000000 if BF561 |
603 | ||
604 | config MIN_VCO_HZ | |
605 | int | |
606 | default 50000000 | |
607 | ||
608 | config MAX_SCLK_HZ | |
609 | int | |
f72eecb9 | 610 | default 133333333 |
f16295e7 RG |
611 | |
612 | config MIN_SCLK_HZ | |
613 | int | |
614 | default 27000000 | |
615 | ||
616 | comment "Kernel Timer/Scheduler" | |
617 | ||
618 | source kernel/Kconfig.hz | |
619 | ||
8b5f79f9 | 620 | config GENERIC_TIME |
10f03f1a | 621 | def_bool y |
8b5f79f9 VM |
622 | |
623 | config GENERIC_CLOCKEVENTS | |
624 | bool "Generic clock events" | |
8b5f79f9 VM |
625 | default y |
626 | ||
0d152c27 | 627 | menu "Clock event device" |
1fa9be72 | 628 | depends on GENERIC_CLOCKEVENTS |
1fa9be72 | 629 | config TICKSOURCE_GPTMR0 |
0d152c27 YL |
630 | bool "GPTimer0" |
631 | depends on !SMP | |
1fa9be72 | 632 | select BFIN_GPTIMERS |
1fa9be72 GY |
633 | |
634 | config TICKSOURCE_CORETMR | |
0d152c27 YL |
635 | bool "Core timer" |
636 | default y | |
637 | endmenu | |
1fa9be72 | 638 | |
0d152c27 | 639 | menu "Clock souce" |
8b5f79f9 | 640 | depends on GENERIC_CLOCKEVENTS |
0d152c27 YL |
641 | config CYCLES_CLOCKSOURCE |
642 | bool "CYCLES" | |
643 | default y | |
8b5f79f9 | 644 | depends on !BFIN_SCRATCH_REG_CYCLES |
1fa9be72 | 645 | depends on !SMP |
8b5f79f9 VM |
646 | help |
647 | If you say Y here, you will enable support for using the 'cycles' | |
648 | registers as a clock source. Doing so means you will be unable to | |
649 | safely write to the 'cycles' register during runtime. You will | |
650 | still be able to read it (such as for performance monitoring), but | |
651 | writing the registers will most likely crash the kernel. | |
652 | ||
1fa9be72 | 653 | config GPTMR0_CLOCKSOURCE |
0d152c27 | 654 | bool "GPTimer0" |
3aca47c0 | 655 | select BFIN_GPTIMERS |
1fa9be72 | 656 | depends on !TICKSOURCE_GPTMR0 |
0d152c27 | 657 | endmenu |
1fa9be72 | 658 | |
10f03f1a JS |
659 | config ARCH_USES_GETTIMEOFFSET |
660 | depends on !GENERIC_CLOCKEVENTS | |
661 | def_bool y | |
662 | ||
8b5f79f9 VM |
663 | source kernel/time/Kconfig |
664 | ||
5f004c20 | 665 | comment "Misc" |
971d5bc4 | 666 | |
f0b5d12f MF |
667 | choice |
668 | prompt "Blackfin Exception Scratch Register" | |
669 | default BFIN_SCRATCH_REG_RETN | |
670 | help | |
671 | Select the resource to reserve for the Exception handler: | |
672 | - RETN: Non-Maskable Interrupt (NMI) | |
673 | - RETE: Exception Return (JTAG/ICE) | |
674 | - CYCLES: Performance counter | |
675 | ||
676 | If you are unsure, please select "RETN". | |
677 | ||
678 | config BFIN_SCRATCH_REG_RETN | |
679 | bool "RETN" | |
680 | help | |
681 | Use the RETN register in the Blackfin exception handler | |
682 | as a stack scratch register. This means you cannot | |
683 | safely use NMI on the Blackfin while running Linux, but | |
684 | you can debug the system with a JTAG ICE and use the | |
685 | CYCLES performance registers. | |
686 | ||
687 | If you are unsure, please select "RETN". | |
688 | ||
689 | config BFIN_SCRATCH_REG_RETE | |
690 | bool "RETE" | |
691 | help | |
692 | Use the RETE register in the Blackfin exception handler | |
693 | as a stack scratch register. This means you cannot | |
694 | safely use a JTAG ICE while debugging a Blackfin board, | |
695 | but you can safely use the CYCLES performance registers | |
696 | and the NMI. | |
697 | ||
698 | If you are unsure, please select "RETN". | |
699 | ||
700 | config BFIN_SCRATCH_REG_CYCLES | |
701 | bool "CYCLES" | |
702 | help | |
703 | Use the CYCLES register in the Blackfin exception handler | |
704 | as a stack scratch register. This means you cannot | |
705 | safely use the CYCLES performance registers on a Blackfin | |
706 | board at anytime, but you can debug the system with a JTAG | |
707 | ICE and use the NMI. | |
708 | ||
709 | If you are unsure, please select "RETN". | |
710 | ||
711 | endchoice | |
712 | ||
1394f032 BW |
713 | endmenu |
714 | ||
715 | ||
716 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 717 | depends on !SMP |
1394f032 | 718 | |
1394f032 BW |
719 | comment "Memory Optimizations" |
720 | ||
721 | config I_ENTRY_L1 | |
722 | bool "Locate interrupt entry code in L1 Memory" | |
723 | default y | |
724 | help | |
01dd2fbf ML |
725 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
726 | into L1 instruction memory. (less latency) | |
1394f032 BW |
727 | |
728 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 729 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
730 | default y |
731 | help | |
01dd2fbf | 732 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 733 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 734 | (less latency) |
1394f032 BW |
735 | |
736 | config DO_IRQ_L1 | |
737 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
738 | default y | |
739 | help | |
01dd2fbf ML |
740 | If enabled, the frequently called do_irq dispatcher function is linked |
741 | into L1 instruction memory. (less latency) | |
1394f032 BW |
742 | |
743 | config CORE_TIMER_IRQ_L1 | |
744 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
745 | default y | |
746 | help | |
01dd2fbf ML |
747 | If enabled, the frequently called timer_interrupt() function is linked |
748 | into L1 instruction memory. (less latency) | |
1394f032 BW |
749 | |
750 | config IDLE_L1 | |
751 | bool "Locate frequently idle function in L1 Memory" | |
752 | default y | |
753 | help | |
01dd2fbf ML |
754 | If enabled, the frequently called idle function is linked |
755 | into L1 instruction memory. (less latency) | |
1394f032 BW |
756 | |
757 | config SCHEDULE_L1 | |
758 | bool "Locate kernel schedule function in L1 Memory" | |
759 | default y | |
760 | help | |
01dd2fbf ML |
761 | If enabled, the frequently called kernel schedule is linked |
762 | into L1 instruction memory. (less latency) | |
1394f032 BW |
763 | |
764 | config ARITHMETIC_OPS_L1 | |
765 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
766 | default y | |
767 | help | |
01dd2fbf ML |
768 | If enabled, arithmetic functions are linked |
769 | into L1 instruction memory. (less latency) | |
1394f032 BW |
770 | |
771 | config ACCESS_OK_L1 | |
772 | bool "Locate access_ok function in L1 Memory" | |
773 | default y | |
774 | help | |
01dd2fbf ML |
775 | If enabled, the access_ok function is linked |
776 | into L1 instruction memory. (less latency) | |
1394f032 BW |
777 | |
778 | config MEMSET_L1 | |
779 | bool "Locate memset function in L1 Memory" | |
780 | default y | |
781 | help | |
01dd2fbf ML |
782 | If enabled, the memset function is linked |
783 | into L1 instruction memory. (less latency) | |
1394f032 BW |
784 | |
785 | config MEMCPY_L1 | |
786 | bool "Locate memcpy function in L1 Memory" | |
787 | default y | |
788 | help | |
01dd2fbf ML |
789 | If enabled, the memcpy function is linked |
790 | into L1 instruction memory. (less latency) | |
1394f032 BW |
791 | |
792 | config SYS_BFIN_SPINLOCK_L1 | |
793 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
794 | default y | |
795 | help | |
01dd2fbf ML |
796 | If enabled, sys_bfin_spinlock function is linked |
797 | into L1 instruction memory. (less latency) | |
1394f032 BW |
798 | |
799 | config IP_CHECKSUM_L1 | |
800 | bool "Locate IP Checksum function in L1 Memory" | |
801 | default n | |
802 | help | |
01dd2fbf ML |
803 | If enabled, the IP Checksum function is linked |
804 | into L1 instruction memory. (less latency) | |
1394f032 BW |
805 | |
806 | config CACHELINE_ALIGNED_L1 | |
807 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
808 | default y if !BF54x |
809 | default n if BF54x | |
1394f032 BW |
810 | depends on !BF531 |
811 | help | |
692105b8 | 812 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 813 | into L1 data memory. (less latency) |
1394f032 BW |
814 | |
815 | config SYSCALL_TAB_L1 | |
816 | bool "Locate Syscall Table L1 Data Memory" | |
817 | default n | |
818 | depends on !BF531 | |
819 | help | |
01dd2fbf ML |
820 | If enabled, the Syscall LUT is linked |
821 | into L1 data memory. (less latency) | |
1394f032 BW |
822 | |
823 | config CPLB_SWITCH_TAB_L1 | |
824 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
825 | default n | |
826 | depends on !BF531 | |
827 | help | |
01dd2fbf ML |
828 | If enabled, the CPLB Switch Tables are linked |
829 | into L1 data memory. (less latency) | |
1394f032 | 830 | |
ca87b7ad GY |
831 | config APP_STACK_L1 |
832 | bool "Support locating application stack in L1 Scratch Memory" | |
833 | default y | |
834 | help | |
835 | If enabled the application stack can be located in L1 | |
836 | scratch memory (less latency). | |
837 | ||
838 | Currently only works with FLAT binaries. | |
839 | ||
6ad2b84c MF |
840 | config EXCEPTION_L1_SCRATCH |
841 | bool "Locate exception stack in L1 Scratch Memory" | |
842 | default n | |
f82e0a0c | 843 | depends on !APP_STACK_L1 |
6ad2b84c MF |
844 | help |
845 | Whenever an exception occurs, use the L1 Scratch memory for | |
846 | stack storage. You cannot place the stacks of FLAT binaries | |
847 | in L1 when using this option. | |
848 | ||
849 | If you don't use L1 Scratch, then you should say Y here. | |
850 | ||
251383c7 RG |
851 | comment "Speed Optimizations" |
852 | config BFIN_INS_LOWOVERHEAD | |
853 | bool "ins[bwl] low overhead, higher interrupt latency" | |
854 | default y | |
855 | help | |
856 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
857 | they can be interrupted at any time (even after they have been issued | |
858 | on to the external bus), and re-issued after the interrupt occurs. | |
859 | For memory - this is not a big deal, since memory does not change if | |
860 | it sees a read. | |
861 | ||
862 | If a FIFO is sitting on the end of the read, it will see two reads, | |
863 | when the core only sees one since the FIFO receives both the read | |
864 | which is cancelled (and not delivered to the core) and the one which | |
865 | is re-issued (which is delivered to the core). | |
866 | ||
867 | To solve this, interrupts are turned off before reads occur to | |
868 | I/O space. This option controls which the overhead/latency of | |
869 | controlling interrupts during this time | |
870 | "n" turns interrupts off every read | |
871 | (higher overhead, but lower interrupt latency) | |
872 | "y" turns interrupts off every loop | |
873 | (low overhead, but longer interrupt latency) | |
874 | ||
875 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
876 | interrupt latency issues, it is safe and OK to turn this off. | |
877 | ||
1394f032 BW |
878 | endmenu |
879 | ||
1394f032 BW |
880 | choice |
881 | prompt "Kernel executes from" | |
882 | help | |
883 | Choose the memory type that the kernel will be running in. | |
884 | ||
885 | config RAMKERNEL | |
886 | bool "RAM" | |
887 | help | |
888 | The kernel will be resident in RAM when running. | |
889 | ||
890 | config ROMKERNEL | |
891 | bool "ROM" | |
892 | help | |
893 | The kernel will be resident in FLASH/ROM when running. | |
894 | ||
895 | endchoice | |
896 | ||
897 | source "mm/Kconfig" | |
898 | ||
780431e3 MF |
899 | config BFIN_GPTIMERS |
900 | tristate "Enable Blackfin General Purpose Timers API" | |
901 | default n | |
902 | help | |
903 | Enable support for the General Purpose Timers API. If you | |
904 | are unsure, say N. | |
905 | ||
906 | To compile this driver as a module, choose M here: the module | |
4737f097 | 907 | will be called gptimers. |
780431e3 | 908 | |
1394f032 | 909 | choice |
d292b000 | 910 | prompt "Uncached DMA region" |
1394f032 | 911 | default DMA_UNCACHED_1M |
86ad7932 CC |
912 | config DMA_UNCACHED_4M |
913 | bool "Enable 4M DMA region" | |
1394f032 BW |
914 | config DMA_UNCACHED_2M |
915 | bool "Enable 2M DMA region" | |
916 | config DMA_UNCACHED_1M | |
917 | bool "Enable 1M DMA region" | |
c45c0659 BS |
918 | config DMA_UNCACHED_512K |
919 | bool "Enable 512K DMA region" | |
920 | config DMA_UNCACHED_256K | |
921 | bool "Enable 256K DMA region" | |
922 | config DMA_UNCACHED_128K | |
923 | bool "Enable 128K DMA region" | |
1394f032 BW |
924 | config DMA_UNCACHED_NONE |
925 | bool "Disable DMA region" | |
926 | endchoice | |
927 | ||
928 | ||
929 | comment "Cache Support" | |
41ba653f | 930 | |
3bebca2d | 931 | config BFIN_ICACHE |
1394f032 | 932 | bool "Enable ICACHE" |
41ba653f | 933 | default y |
41ba653f JZ |
934 | config BFIN_EXTMEM_ICACHEABLE |
935 | bool "Enable ICACHE for external memory" | |
936 | depends on BFIN_ICACHE | |
937 | default y | |
938 | config BFIN_L2_ICACHEABLE | |
939 | bool "Enable ICACHE for L2 SRAM" | |
940 | depends on BFIN_ICACHE | |
941 | depends on BF54x || BF561 | |
942 | default n | |
943 | ||
3bebca2d | 944 | config BFIN_DCACHE |
1394f032 | 945 | bool "Enable DCACHE" |
41ba653f | 946 | default y |
3bebca2d | 947 | config BFIN_DCACHE_BANKA |
1394f032 | 948 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 949 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 950 | default n |
41ba653f JZ |
951 | config BFIN_EXTMEM_DCACHEABLE |
952 | bool "Enable DCACHE for external memory" | |
3bebca2d | 953 | depends on BFIN_DCACHE |
41ba653f JZ |
954 | default y |
955 | choice | |
956 | prompt "External memory DCACHE policy" | |
957 | depends on BFIN_EXTMEM_DCACHEABLE | |
958 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
959 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
960 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 961 | bool "Write back" |
46fa5eec | 962 | depends on !SMP |
1394f032 BW |
963 | help |
964 | Write Back Policy: | |
965 | Cached data will be written back to SDRAM only when needed. | |
966 | This can give a nice increase in performance, but beware of | |
967 | broken drivers that do not properly invalidate/flush their | |
968 | cache. | |
969 | ||
970 | Write Through Policy: | |
971 | Cached data will always be written back to SDRAM when the | |
972 | cache is updated. This is a completely safe setting, but | |
973 | performance is worse than Write Back. | |
974 | ||
975 | If you are unsure of the options and you want to be safe, | |
976 | then go with Write Through. | |
977 | ||
41ba653f | 978 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
979 | bool "Write through" |
980 | help | |
981 | Write Back Policy: | |
982 | Cached data will be written back to SDRAM only when needed. | |
983 | This can give a nice increase in performance, but beware of | |
984 | broken drivers that do not properly invalidate/flush their | |
985 | cache. | |
986 | ||
987 | Write Through Policy: | |
988 | Cached data will always be written back to SDRAM when the | |
989 | cache is updated. This is a completely safe setting, but | |
990 | performance is worse than Write Back. | |
991 | ||
992 | If you are unsure of the options and you want to be safe, | |
993 | then go with Write Through. | |
994 | ||
995 | endchoice | |
996 | ||
41ba653f JZ |
997 | config BFIN_L2_DCACHEABLE |
998 | bool "Enable DCACHE for L2 SRAM" | |
999 | depends on BFIN_DCACHE | |
9c954f89 | 1000 | depends on (BF54x || BF561) && !SMP |
41ba653f | 1001 | default n |
5ba76675 | 1002 | choice |
41ba653f JZ |
1003 | prompt "L2 SRAM DCACHE policy" |
1004 | depends on BFIN_L2_DCACHEABLE | |
1005 | default BFIN_L2_WRITEBACK | |
1006 | config BFIN_L2_WRITEBACK | |
5ba76675 | 1007 | bool "Write back" |
5ba76675 | 1008 | |
41ba653f | 1009 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 1010 | bool "Write through" |
5ba76675 | 1011 | endchoice |
f099f39a | 1012 | |
41ba653f JZ |
1013 | |
1014 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1015 | config MPU |
1016 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1017 | default n | |
1018 | help | |
1019 | Use the processor's MPU to protect applications from accessing | |
1020 | memory they do not own. This comes at a performance penalty | |
1021 | and is recommended only for debugging. | |
1022 | ||
692105b8 | 1023 | comment "Asynchronous Memory Configuration" |
1394f032 | 1024 | |
ddf416b2 | 1025 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
1026 | config C_AMCKEN |
1027 | bool "Enable CLKOUT" | |
1028 | default y | |
1029 | ||
1030 | config C_CDPRIO | |
1031 | bool "DMA has priority over core for ext. accesses" | |
1032 | default n | |
1033 | ||
1034 | config C_B0PEN | |
1035 | depends on BF561 | |
1036 | bool "Bank 0 16 bit packing enable" | |
1037 | default y | |
1038 | ||
1039 | config C_B1PEN | |
1040 | depends on BF561 | |
1041 | bool "Bank 1 16 bit packing enable" | |
1042 | default y | |
1043 | ||
1044 | config C_B2PEN | |
1045 | depends on BF561 | |
1046 | bool "Bank 2 16 bit packing enable" | |
1047 | default y | |
1048 | ||
1049 | config C_B3PEN | |
1050 | depends on BF561 | |
1051 | bool "Bank 3 16 bit packing enable" | |
1052 | default n | |
1053 | ||
1054 | choice | |
692105b8 | 1055 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1056 | default C_AMBEN_ALL |
1057 | ||
1058 | config C_AMBEN | |
1059 | bool "Disable All Banks" | |
1060 | ||
1061 | config C_AMBEN_B0 | |
1062 | bool "Enable Bank 0" | |
1063 | ||
1064 | config C_AMBEN_B0_B1 | |
1065 | bool "Enable Bank 0 & 1" | |
1066 | ||
1067 | config C_AMBEN_B0_B1_B2 | |
1068 | bool "Enable Bank 0 & 1 & 2" | |
1069 | ||
1070 | config C_AMBEN_ALL | |
1071 | bool "Enable All Banks" | |
1072 | endchoice | |
1073 | endmenu | |
1074 | ||
1075 | menu "EBIU_AMBCTL Control" | |
1076 | config BANK_0 | |
c8342f87 | 1077 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1078 | default 0x7BB0 |
c8342f87 MF |
1079 | help |
1080 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1081 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1082 | |
1083 | config BANK_1 | |
c8342f87 | 1084 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1085 | default 0x7BB0 |
197fba56 | 1086 | default 0x5558 if BF54x |
c8342f87 MF |
1087 | help |
1088 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1089 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1090 | |
1091 | config BANK_2 | |
c8342f87 | 1092 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1093 | default 0x7BB0 |
c8342f87 MF |
1094 | help |
1095 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1096 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1097 | |
1098 | config BANK_3 | |
c8342f87 | 1099 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1100 | default 0x99B3 |
c8342f87 MF |
1101 | help |
1102 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1103 | used to control the Asynchronous Memory Bank 3 settings. | |
1104 | ||
1394f032 BW |
1105 | endmenu |
1106 | ||
e40540b3 SZ |
1107 | config EBIU_MBSCTLVAL |
1108 | hex "EBIU Bank Select Control Register" | |
1109 | depends on BF54x | |
1110 | default 0 | |
1111 | ||
1112 | config EBIU_MODEVAL | |
1113 | hex "Flash Memory Mode Control Register" | |
1114 | depends on BF54x | |
1115 | default 1 | |
1116 | ||
1117 | config EBIU_FCTLVAL | |
1118 | hex "Flash Memory Bank Control Register" | |
1119 | depends on BF54x | |
1120 | default 6 | |
1394f032 BW |
1121 | endmenu |
1122 | ||
1123 | ############################################################################# | |
1124 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1125 | ||
1126 | config PCI | |
1127 | bool "PCI support" | |
a95ca3b2 | 1128 | depends on BROKEN |
1394f032 BW |
1129 | help |
1130 | Support for PCI bus. | |
1131 | ||
1132 | source "drivers/pci/Kconfig" | |
1133 | ||
1394f032 BW |
1134 | source "drivers/pcmcia/Kconfig" |
1135 | ||
1136 | source "drivers/pci/hotplug/Kconfig" | |
1137 | ||
1138 | endmenu | |
1139 | ||
1140 | menu "Executable file formats" | |
1141 | ||
1142 | source "fs/Kconfig.binfmt" | |
1143 | ||
1144 | endmenu | |
1145 | ||
1146 | menu "Power management options" | |
ad46163a | 1147 | |
1394f032 BW |
1148 | source "kernel/power/Kconfig" |
1149 | ||
f4cb5700 JB |
1150 | config ARCH_SUSPEND_POSSIBLE |
1151 | def_bool y | |
f4cb5700 | 1152 | |
1394f032 | 1153 | choice |
1efc80b5 | 1154 | prompt "Standby Power Saving Mode" |
1394f032 | 1155 | depends on PM |
cfefe3c6 MH |
1156 | default PM_BFIN_SLEEP_DEEPER |
1157 | config PM_BFIN_SLEEP_DEEPER | |
1158 | bool "Sleep Deeper" | |
1159 | help | |
1160 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1161 | power dissipation by disabling the clock to the processor core (CCLK). | |
1162 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1163 | to 0.85 V to provide the greatest power savings, while preserving the | |
1164 | processor state. | |
1165 | The PLL and system clock (SCLK) continue to operate at a very low | |
1166 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1167 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1168 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1169 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1170 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1171 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1172 | ||
1efc80b5 MH |
1173 | If unsure, select "Sleep Deeper". |
1174 | ||
cfefe3c6 MH |
1175 | config PM_BFIN_SLEEP |
1176 | bool "Sleep" | |
1177 | help | |
1178 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1179 | dissipation by disabling the clock to the processor core (CCLK). | |
1180 | The PLL and system clock (SCLK), however, continue to operate in | |
1181 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1182 | up the processor. When in the sleep mode, system DMA access to L1 |
1183 | memory is not supported. | |
1184 | ||
1185 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1186 | endchoice |
1394f032 | 1187 | |
1394f032 | 1188 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1189 | bool "Allow Wakeup from Standby by GPIO" |
ff19fed4 | 1190 | depends on PM && !BF54x |
1394f032 BW |
1191 | |
1192 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1193 | int "GPIO number" |
1394f032 BW |
1194 | range 0 47 |
1195 | depends on PM_WAKEUP_BY_GPIO | |
d1a3336e | 1196 | default 2 |
1394f032 BW |
1197 | |
1198 | choice | |
1199 | prompt "GPIO Polarity" | |
1200 | depends on PM_WAKEUP_BY_GPIO | |
1201 | default PM_WAKEUP_GPIO_POLAR_H | |
1202 | config PM_WAKEUP_GPIO_POLAR_H | |
1203 | bool "Active High" | |
1204 | config PM_WAKEUP_GPIO_POLAR_L | |
1205 | bool "Active Low" | |
1206 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1207 | bool "Falling EDGE" | |
1208 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1209 | bool "Rising EDGE" | |
1210 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1211 | bool "Both EDGE" | |
1212 | endchoice | |
1213 | ||
1efc80b5 MH |
1214 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1215 | depends on PM | |
1216 | ||
1efc80b5 MH |
1217 | config PM_BFIN_WAKE_PH6 |
1218 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1219 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1220 | default n |
1221 | help | |
1222 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1223 | ||
1efc80b5 MH |
1224 | config PM_BFIN_WAKE_GP |
1225 | bool "Allow Wake-Up from GPIOs" | |
1226 | depends on PM && BF54x | |
1227 | default n | |
1228 | help | |
1229 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1230 | (all processors, except ADSP-BF549). This option sets |
1231 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1232 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1233 | On ADSP-BF549 this option enables the the same functionality on the | |
1234 | /MRXON pin also PH7. | |
1235 | ||
1394f032 BW |
1236 | endmenu |
1237 | ||
1394f032 | 1238 | menu "CPU Frequency scaling" |
ad46163a | 1239 | depends on !SMP |
1394f032 BW |
1240 | |
1241 | source "drivers/cpufreq/Kconfig" | |
1242 | ||
5ad2ca5f MH |
1243 | config BFIN_CPU_FREQ |
1244 | bool | |
1245 | depends on CPU_FREQ | |
1246 | select CPU_FREQ_TABLE | |
1247 | default y | |
1248 | ||
14b03204 MH |
1249 | config CPU_VOLTAGE |
1250 | bool "CPU Voltage scaling" | |
73feb5c0 | 1251 | depends on EXPERIMENTAL |
14b03204 MH |
1252 | depends on CPU_FREQ |
1253 | default n | |
1254 | help | |
1255 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1256 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1257 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1258 | the PLL may unlock. |
1259 | ||
1394f032 BW |
1260 | endmenu |
1261 | ||
1394f032 BW |
1262 | source "net/Kconfig" |
1263 | ||
1264 | source "drivers/Kconfig" | |
1265 | ||
872d024b MF |
1266 | source "drivers/firmware/Kconfig" |
1267 | ||
1394f032 BW |
1268 | source "fs/Kconfig" |
1269 | ||
74ce8322 | 1270 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1271 | |
1272 | source "security/Kconfig" | |
1273 | ||
1274 | source "crypto/Kconfig" | |
1275 | ||
1276 | source "lib/Kconfig" |