[net-next-2.6.git] / arch / arm / plat-samsung / clock.c

/* linux/arch/arm/plat-s3c24xx/clock.c
 *
 * Copyright 2004-2005 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX Core clock control support
 *
 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
 **
 **  Copyright (C) 2004 ARM Limited.
 **  Written by Deep Blue Solutions Limited.
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#include <plat/cpu-freq.h>

#include <plat/clock.h>
#include <plat/cpu.h>

/* clock information */

static LIST_HEAD(clocks);

/* We originally used an mutex here, but some contexts (see resume)
 * are calling functions such as clk_set_parent() with IRQs disabled
 * causing an BUG to be triggered.
 */
DEFINE_SPINLOCK(clocks_lock);

/* enable and disable calls for use with the clk struct */

static int clk_null_enable(struct clk *clk, int enable)
{
	return 0;
}

/* Clock API calls */

struct clk *clk_get(struct device *dev, const char *id)
{
	struct clk *p;
	struct clk *clk = ERR_PTR(-ENOENT);
	int idno;

	if (dev == NULL || dev->bus != &platform_bus_type)
		idno = -1;
	else
		idno = to_platform_device(dev)->id;

	spin_lock(&clocks_lock);

	list_for_each_entry(p, &clocks, list) {
		if (p->id == idno &&
		    strcmp(id, p->name) == 0 &&
		    try_module_get(p->owner)) {
			clk = p;
			break;
		}
	}

	/* check for the case where a device was supplied, but the
	 * clock that was being searched for is not device specific */

	if (IS_ERR(clk)) {
		list_for_each_entry(p, &clocks, list) {
			if (p->id == -1 && strcmp(id, p->name) == 0 &&
			    try_module_get(p->owner)) {
				clk = p;
				break;
			}
		}
	}

	spin_unlock(&clocks_lock);
	return clk;
}

void clk_put(struct clk *clk)
{
	module_put(clk->owner);
}

int clk_enable(struct clk *clk)
{
	if (IS_ERR(clk) || clk == NULL)
		return -EINVAL;

	clk_enable(clk->parent);

	spin_lock(&clocks_lock);

	if ((clk->usage++) == 0)
		(clk->enable)(clk, 1);

	spin_unlock(&clocks_lock);
	return 0;
}

void clk_disable(struct clk *clk)
{
	if (IS_ERR(clk) || clk == NULL)
		return;

	spin_lock(&clocks_lock);

	if ((--clk->usage) == 0)
		(clk->enable)(clk, 0);

	spin_unlock(&clocks_lock);
	clk_disable(clk->parent);
}


unsigned long clk_get_rate(struct clk *clk)
{
	if (IS_ERR(clk))
		return 0;

	if (clk->rate != 0)
		return clk->rate;

	if (clk->ops != NULL && clk->ops->get_rate != NULL)
		return (clk->ops->get_rate)(clk);

	if (clk->parent != NULL)
		return clk_get_rate(clk->parent);

	return clk->rate;
}

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
		return (clk->ops->round_rate)(clk, rate);

	return rate;
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	int ret;

	if (IS_ERR(clk))
		return -EINVAL;

	/* We do not default just do a clk->rate = rate as
	 * the clock may have been made this way by choice.
	 */

	WARN_ON(clk->ops == NULL);
	WARN_ON(clk->ops && clk->ops->set_rate == NULL);

	if (clk->ops == NULL || clk->ops->set_rate == NULL)
		return -EINVAL;

	spin_lock(&clocks_lock);
	ret = (clk->ops->set_rate)(clk, rate);
	spin_unlock(&clocks_lock);

	return ret;
}

struct clk *clk_get_parent(struct clk *clk)
{
	return clk->parent;
}

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	int ret = 0;

	if (IS_ERR(clk))
		return -EINVAL;

	spin_lock(&clocks_lock);

	if (clk->ops && clk->ops->set_parent)
		ret = (clk->ops->set_parent)(clk, parent);

	spin_unlock(&clocks_lock);

	return ret;
}

EXPORT_SYMBOL(clk_get);
EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
EXPORT_SYMBOL(clk_round_rate);
EXPORT_SYMBOL(clk_set_rate);
EXPORT_SYMBOL(clk_get_parent);
EXPORT_SYMBOL(clk_set_parent);

/* base clocks */

int clk_default_setrate(struct clk *clk, unsigned long rate)
{
	clk->rate = rate;
	return 0;
}

struct clk_ops clk_ops_def_setrate = {
	.set_rate	= clk_default_setrate,
};

struct clk clk_xtal = {
	.name		= "xtal",
	.id		= -1,
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
};

struct clk clk_ext = {
	.name		= "ext",
	.id		= -1,
};

struct clk clk_epll = {
	.name		= "epll",
	.id		= -1,
};

struct clk clk_mpll = {
	.name		= "mpll",
	.id		= -1,
	.ops		= &clk_ops_def_setrate,
};

struct clk clk_upll = {
	.name		= "upll",
	.id		= -1,
	.parent		= NULL,
	.ctrlbit	= 0,
};

struct clk clk_f = {
	.name		= "fclk",
	.id		= -1,
	.rate		= 0,
	.parent		= &clk_mpll,
	.ctrlbit	= 0,
};

struct clk clk_h = {
	.name		= "hclk",
	.id		= -1,
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
	.ops		= &clk_ops_def_setrate,
};

struct clk clk_p = {
	.name		= "pclk",
	.id		= -1,
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
	.ops		= &clk_ops_def_setrate,
};

struct clk clk_usb_bus = {
	.name		= "usb-bus",
	.id		= -1,
	.rate		= 0,
	.parent		= &clk_upll,
};


struct clk s3c24xx_uclk = {
	.name		= "uclk",
	.id		= -1,
};

/* initialise the clock system */

int s3c24xx_register_clock(struct clk *clk)
{
	if (clk->enable == NULL)
		clk->enable = clk_null_enable;

	/* add to the list of available clocks */

	/* Quick check to see if this clock has already been registered. */
	BUG_ON(clk->list.prev != clk->list.next);

	spin_lock(&clocks_lock);
	list_add(&clk->list, &clocks);
	spin_unlock(&clocks_lock);

	return 0;
}

int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
{
	int fails = 0;

	for (; nr_clks > 0; nr_clks--, clks++) {
		if (s3c24xx_register_clock(*clks) < 0)
			fails++;
	}

	return fails;
}

/**
 * s3c_register_clocks() - register an array of clocks
 * @clkp: Pointer to the first clock in the array.
 * @nr_clks: Number of clocks to register.
 *
 * Call s3c24xx_register_clock() on the @clkp array given, printing an
 * error if it fails to register the clock (unlikely).
 */
void __initdata s3c_register_clocks(struct clk *clkp, int nr_clks)
{
	int ret;

	for (; nr_clks > 0; nr_clks--, clkp++) {
		ret = s3c24xx_register_clock(clkp);

		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}
	}
}

/* initalise all the clocks */

int __init s3c24xx_register_baseclocks(unsigned long xtal)
{
	printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");

	clk_xtal.rate = xtal;

	/* register our clocks */

	if (s3c24xx_register_clock(&clk_xtal) < 0)
		printk(KERN_ERR "failed to register master xtal\n");

	if (s3c24xx_register_clock(&clk_mpll) < 0)
		printk(KERN_ERR "failed to register mpll clock\n");

	if (s3c24xx_register_clock(&clk_upll) < 0)
		printk(KERN_ERR "failed to register upll clock\n");

	if (s3c24xx_register_clock(&clk_f) < 0)
		printk(KERN_ERR "failed to register cpu fclk\n");

	if (s3c24xx_register_clock(&clk_h) < 0)
		printk(KERN_ERR "failed to register cpu hclk\n");

	if (s3c24xx_register_clock(&clk_p) < 0)
		printk(KERN_ERR "failed to register cpu pclk\n");

	return 0;
}
Commit	Line	Data
adbefaa5 BD	1	/* linux/arch/arm/plat-s3c24xx/clock.c
adbefaa5 BD	2	*
50f430e3	3	* Copyright 2004-2005 Simtec Electronics
adbefaa5 BD	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C24XX Core clock control support
	7	*
	8	* Based on, and code from linux/arch/arm/mach-versatile/clock.c
	9	**
	10	** Copyright (C) 2004 ARM Limited.
	11	** Written by Deep Blue Solutions Limited.
	12	*
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	27	*/
	28
	29	#include <linux/init.h>
	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
	32	#include <linux/list.h>
	33	#include <linux/errno.h>
	34	#include <linux/err.h>
	35	#include <linux/platform_device.h>
	36	#include <linux/sysdev.h>
	37	#include <linux/interrupt.h>
	38	#include <linux/ioport.h>
	39	#include <linux/clk.h>
	40	#include <linux/spinlock.h>
adbefaa5 BD	41	#include <linux/io.h>
	42
	43	#include <mach/hardware.h>
	44	#include <asm/irq.h>
	45
	46	#include <plat/cpu-freq.h>
	47
	48	#include <plat/clock.h>
	49	#include <plat/cpu.h>
	50
	51	/* clock information */
	52
	53	static LIST_HEAD(clocks);
	54
	55	/* We originally used an mutex here, but some contexts (see resume)
	56	* are calling functions such as clk_set_parent() with IRQs disabled
	57	* causing an BUG to be triggered.
	58	*/
	59	DEFINE_SPINLOCK(clocks_lock);
	60
	61	/* enable and disable calls for use with the clk struct */
	62
	63	static int clk_null_enable(struct clk *clk, int enable)
	64	{
	65	return 0;
	66	}
	67
	68	/* Clock API calls */
	69
	70	struct clk clk_get(struct device dev, const char *id)
	71	{
	72	struct clk *p;
	73	struct clk *clk = ERR_PTR(-ENOENT);
	74	int idno;
	75
	76	if (dev == NULL \|\| dev->bus != &platform_bus_type)
	77	idno = -1;
	78	else
	79	idno = to_platform_device(dev)->id;
	80
	81	spin_lock(&clocks_lock);
	82
	83	list_for_each_entry(p, &clocks, list) {
	84	if (p->id == idno &&
	85	strcmp(id, p->name) == 0 &&
	86	try_module_get(p->owner)) {
	87	clk = p;
	88	break;
	89	}
	90	}
	91
	92	/* check for the case where a device was supplied, but the
	93	* clock that was being searched for is not device specific */
	94
	95	if (IS_ERR(clk)) {
	96	list_for_each_entry(p, &clocks, list) {
	97	if (p->id == -1 && strcmp(id, p->name) == 0 &&
	98	try_module_get(p->owner)) {
	99	clk = p;
	100	break;
	101	}
	102	}
	103	}
	104
105	spin_unlock(&clocks_lock);
106	return clk;
107	}
108
109	void clk_put(struct clk *clk)
110	{
111	module_put(clk->owner);
112	}
113
114	int clk_enable(struct clk *clk)
115	{
116	if (IS_ERR(clk) \|\| clk == NULL)
117	return -EINVAL;
118
119	clk_enable(clk->parent);
120
121	spin_lock(&clocks_lock);
122
123	if ((clk->usage++) == 0)
124	(clk->enable)(clk, 1);
125
126	spin_unlock(&clocks_lock);
127	return 0;
128	}
129
130	void clk_disable(struct clk *clk)
131	{
132	if (IS_ERR(clk) \|\| clk == NULL)
133	return;
134
135	spin_lock(&clocks_lock);
136
137	if ((--clk->usage) == 0)
138	(clk->enable)(clk, 0);
139
140	spin_unlock(&clocks_lock);
141	clk_disable(clk->parent);
142	}
143
144
145	unsigned long clk_get_rate(struct clk *clk)
146	{
147	if (IS_ERR(clk))
148	return 0;
149
150	if (clk->rate != 0)
151	return clk->rate;
152
b3bf41be BD	153	if (clk->ops != NULL && clk->ops->get_rate != NULL)
b3bf41be BD	154	return (clk->ops->get_rate)(clk);
adbefaa5 BD	155
	156	if (clk->parent != NULL)
	157	return clk_get_rate(clk->parent);
	158
	159	return clk->rate;
	160	}
	161
	162	long clk_round_rate(struct clk *clk, unsigned long rate)
	163	{
b3bf41be BD	164	if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
b3bf41be BD	165	return (clk->ops->round_rate)(clk, rate);
adbefaa5 BD	166
	167	return rate;
	168	}
	169
	170	int clk_set_rate(struct clk *clk, unsigned long rate)
	171	{
	172	int ret;
	173
	174	if (IS_ERR(clk))
	175	return -EINVAL;
	176
	177	/* We do not default just do a clk->rate = rate as
	178	* the clock may have been made this way by choice.
	179	*/
	180
b3bf41be BD	181	WARN_ON(clk->ops == NULL);
b3bf41be BD	182	WARN_ON(clk->ops && clk->ops->set_rate == NULL);
adbefaa5	183
b3bf41be	184	if (clk->ops == NULL \|\| clk->ops->set_rate == NULL)
adbefaa5 BD	185	return -EINVAL;
	186
	187	spin_lock(&clocks_lock);
b3bf41be	188	ret = (clk->ops->set_rate)(clk, rate);
adbefaa5 BD	189	spin_unlock(&clocks_lock);
	190
	191	return ret;
	192	}
	193
	194	struct clk clk_get_parent(struct clk clk)
	195	{
	196	return clk->parent;
	197	}
	198
	199	int clk_set_parent(struct clk clk, struct clk parent)
	200	{
	201	int ret = 0;
	202
	203	if (IS_ERR(clk))
	204	return -EINVAL;
	205
	206	spin_lock(&clocks_lock);
	207
b3bf41be BD	208	if (clk->ops && clk->ops->set_parent)
b3bf41be BD	209	ret = (clk->ops->set_parent)(clk, parent);
adbefaa5 BD	210
	211	spin_unlock(&clocks_lock);
	212
	213	return ret;
	214	}
	215
	216	EXPORT_SYMBOL(clk_get);
	217	EXPORT_SYMBOL(clk_put);
	218	EXPORT_SYMBOL(clk_enable);
	219	EXPORT_SYMBOL(clk_disable);
	220	EXPORT_SYMBOL(clk_get_rate);
	221	EXPORT_SYMBOL(clk_round_rate);
	222	EXPORT_SYMBOL(clk_set_rate);
	223	EXPORT_SYMBOL(clk_get_parent);
	224	EXPORT_SYMBOL(clk_set_parent);
	225
	226	/* base clocks */
	227
ed276849	228	int clk_default_setrate(struct clk *clk, unsigned long rate)
adbefaa5 BD	229	{
	230	clk->rate = rate;
	231	return 0;
	232	}
	233
ed276849	234	struct clk_ops clk_ops_def_setrate = {
b3bf41be BD	235	.set_rate = clk_default_setrate,
	236	};
	237
adbefaa5 BD	238	struct clk clk_xtal = {
	239	.name = "xtal",
	240	.id = -1,
	241	.rate = 0,
	242	.parent = NULL,
	243	.ctrlbit = 0,
	244	};
	245
4b31d8b2 BD	246	struct clk clk_ext = {
	247	.name = "ext",
	248	.id = -1,
	249	};
	250
	251	struct clk clk_epll = {
	252	.name = "epll",
	253	.id = -1,
	254	};
	255
adbefaa5 BD	256	struct clk clk_mpll = {
	257	.name = "mpll",
	258	.id = -1,
b3bf41be	259	.ops = &clk_ops_def_setrate,
adbefaa5 BD	260	};
	261
	262	struct clk clk_upll = {
	263	.name = "upll",
	264	.id = -1,
	265	.parent = NULL,
	266	.ctrlbit = 0,
	267	};
	268
	269	struct clk clk_f = {
	270	.name = "fclk",
	271	.id = -1,
	272	.rate = 0,
	273	.parent = &clk_mpll,
	274	.ctrlbit = 0,
adbefaa5 BD	275	};
	276
	277	struct clk clk_h = {
	278	.name = "hclk",
	279	.id = -1,
	280	.rate = 0,
	281	.parent = NULL,
	282	.ctrlbit = 0,
b3bf41be	283	.ops = &clk_ops_def_setrate,
adbefaa5 BD	284	};
	285
	286	struct clk clk_p = {
	287	.name = "pclk",
	288	.id = -1,
	289	.rate = 0,
	290	.parent = NULL,
	291	.ctrlbit = 0,
b3bf41be	292	.ops = &clk_ops_def_setrate,
adbefaa5 BD	293	};
	294
	295	struct clk clk_usb_bus = {
	296	.name = "usb-bus",
	297	.id = -1,
	298	.rate = 0,
	299	.parent = &clk_upll,
	300	};
	301
	302
adbefaa5 BD	303	struct clk s3c24xx_uclk = {
	304	.name = "uclk",
	305	.id = -1,
	306	};
	307
	308	/* initialise the clock system */
	309
	310	int s3c24xx_register_clock(struct clk *clk)
	311	{
adbefaa5 BD	312	if (clk->enable == NULL)
	313	clk->enable = clk_null_enable;
	314
	315	/* add to the list of available clocks */
	316
cec444b7 BD	317	/* Quick check to see if this clock has already been registered. */
	318	BUG_ON(clk->list.prev != clk->list.next);
	319
adbefaa5 BD	320	spin_lock(&clocks_lock);
	321	list_add(&clk->list, &clocks);
	322	spin_unlock(&clocks_lock);
	323
	324	return 0;
	325	}
	326
	327	int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
	328	{
	329	int fails = 0;
	330
	331	for (; nr_clks > 0; nr_clks--, clks++) {
	332	if (s3c24xx_register_clock(*clks) < 0)
	333	fails++;
	334	}
	335
	336	return fails;
	337	}
	338
1d9f13c4 BD	339	/**
	340	* s3c_register_clocks() - register an array of clocks
	341	* @clkp: Pointer to the first clock in the array.
	342	* @nr_clks: Number of clocks to register.
	343	*
	344	* Call s3c24xx_register_clock() on the @clkp array given, printing an
	345	* error if it fails to register the clock (unlikely).
	346	*/
	347	void __initdata s3c_register_clocks(struct clk *clkp, int nr_clks)
	348	{
	349	int ret;
	350
	351	for (; nr_clks > 0; nr_clks--, clkp++) {
	352	ret = s3c24xx_register_clock(clkp);
	353
	354	if (ret < 0) {
	355	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	356	clkp->name, ret);
	357	}
	358	}
	359	}
	360
adbefaa5 BD	361	/* initalise all the clocks */
	362
	363	int __init s3c24xx_register_baseclocks(unsigned long xtal)
	364	{
50f430e3	365	printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
adbefaa5 BD	366
	367	clk_xtal.rate = xtal;
	368
	369	/* register our clocks */
	370
	371	if (s3c24xx_register_clock(&clk_xtal) < 0)
	372	printk(KERN_ERR "failed to register master xtal\n");
	373
	374	if (s3c24xx_register_clock(&clk_mpll) < 0)
	375	printk(KERN_ERR "failed to register mpll clock\n");
	376
	377	if (s3c24xx_register_clock(&clk_upll) < 0)
	378	printk(KERN_ERR "failed to register upll clock\n");
	379
	380	if (s3c24xx_register_clock(&clk_f) < 0)
	381	printk(KERN_ERR "failed to register cpu fclk\n");
	382
	383	if (s3c24xx_register_clock(&clk_h) < 0)
	384	printk(KERN_ERR "failed to register cpu hclk\n");
	385
	386	if (s3c24xx_register_clock(&clk_p) < 0)
	387	printk(KERN_ERR "failed to register cpu pclk\n");
	388
	389	return 0;
	390	}
	391