[net-next-2.6.git] / arch / arm / plat-s5pc1xx / clock.c

/* linux/arch/arm/plat-s5pc1xx/clock.c
 *
 * Copyright 2009 Samsung Electronics Co.
 *
 * S5PC1XX Base clock support
 *
 * Based on plat-s3c64xx/clock.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/map.h>

#include <plat/regs-clock.h>
#include <plat/devs.h>
#include <plat/clock.h>

struct clk clk_27m = {
	.name		= "clk_27m",
	.id		= -1,
	.rate		= 27000000,
};

static int clk_48m_ctrl(struct clk *clk, int enable)
{
	unsigned long flags;
	u32 val;

	/* can't rely on clock lock, this register has other usages */
	local_irq_save(flags);

	val = __raw_readl(S5PC100_CLKSRC1);
	if (enable)
		val |= S5PC100_CLKSRC1_CLK48M_MASK;
	else
		val &= ~S5PC100_CLKSRC1_CLK48M_MASK;

	__raw_writel(val, S5PC100_CLKSRC1);
	local_irq_restore(flags);

	return 0;
}

struct clk clk_48m = {
	.name		= "clk_48m",
	.id		= -1,
	.rate		= 48000000,
	.enable		= clk_48m_ctrl,
};

struct clk clk_54m = {
	.name		= "clk_54m",
	.id		= -1,
	.rate		= 54000000,
};

static int clk_dummy_enable(struct clk *clk, int enable)
{
	return 0;
}

struct clk clk_hd0 = {
	.name		= "hclkd0",
	.id		= -1,
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
	.enable		= clk_dummy_enable,
	.ops		= &clk_ops_def_setrate,
};

struct clk clk_pd0 = {
	.name		= "pclkd0",
	.id		= -1,
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
	.ops		= &clk_ops_def_setrate,
	.enable		= clk_dummy_enable,
};

static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
{
	unsigned int ctrlbit = clk->ctrlbit;
	u32 con;

	con = __raw_readl(reg);
	if (enable)
		con |= ctrlbit;
	else
		con &= ~ctrlbit;
	__raw_writel(con, reg);

	return 0;
}

static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
}

static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
}

static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
}

static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
}

static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
}

static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
}

static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
}

static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
}

static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
}

static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
}

int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
}

int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
{
	return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
}

static struct clk s5pc100_init_clocks_disable[] = {
	{
		.name		= "dsi",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d11_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D11_DSI,
	}, {
		.name		= "csi",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s5pc100_clk_d11_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D11_CSI,
	}, {
		.name		= "ccan",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_CCAN0,
	}, {
		.name		= "ccan",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_CCAN1,
	}, {
		.name		= "keypad",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_KEYIF,
	}, {
		.name		= "hclkd2",
		.id		= -1,
		.parent		= NULL,
		.enable		= s5pc100_clk_d20_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D20_HCLKD2,
	}, {
		.name		= "iis-d2",
		.id		= -1,
		.parent		= NULL,
		.enable		= s5pc100_clk_d20_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D20_I2SD2,
	},
};

static struct clk s5pc100_init_clocks[] = {
	/* System1 (D0_0) devices */
	{
		.name		= "intc",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d00_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D00_INTC,
	}, {
		.name		= "tzic",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d00_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D00_TZIC,
	}, {
		.name		= "cf-ata",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d00_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D00_CFCON,
	}, {
		.name		= "mdma",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d00_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D00_MDMA,
	}, {
		.name		= "g2d",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d00_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D00_G2D,
	}, {
		.name		= "secss",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d00_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D00_SECSS,
	}, {
		.name		= "cssys",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d00_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D00_CSSYS,
	},

	/* Memory (D0_1) devices */
	{
		.name		= "dmc",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d01_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D01_DMC,
	}, {
		.name		= "sromc",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d01_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D01_SROMC,
	}, {
		.name		= "onenand",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d01_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D01_ONENAND,
	}, {
		.name		= "nand",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d01_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D01_NFCON,
	}, {
		.name		= "intmem",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d01_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D01_INTMEM,
	}, {
		.name		= "ebi",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d01_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D01_EBI,
	},

	/* System2 (D0_2) devices */
	{
		.name		= "seckey",
		.id		= -1,
		.parent		= &clk_pd0,
		.enable		= s5pc100_clk_d02_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D02_SECKEY,
	}, {
		.name		= "sdm",
		.id		= -1,
		.parent		= &clk_hd0,
		.enable		= s5pc100_clk_d02_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D02_SDM,
	},

	/* File (D1_0) devices */
	{
		.name		= "pdma",
		.id		= 0,
		.parent		= &clk_h,
		.enable		= s5pc100_clk_d10_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D10_PDMA0,
	}, {
		.name		= "pdma",
		.id		= 1,
		.parent		= &clk_h,
		.enable		= s5pc100_clk_d10_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D10_PDMA1,
	}, {
		.name		= "usb-host",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s5pc100_clk_d10_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D10_USBHOST,
	}, {
		.name		= "otg",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s5pc100_clk_d10_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D10_USBOTG,
	}, {
		.name		= "modem",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s5pc100_clk_d10_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D10_MODEMIF,
	}, {
		.name		= "hsmmc",
		.id		= 0,
		.parent		= &clk_48m,
		.enable		= s5pc100_clk_d10_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D10_HSMMC0,
	}, {
		.name		= "hsmmc",
		.id		= 1,
		.parent		= &clk_48m,
		.enable		= s5pc100_clk_d10_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D10_HSMMC1,
	}, {
		.name		= "hsmmc",
		.id		= 2,
		.parent		= &clk_48m,
		.enable		= s5pc100_clk_d10_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D10_HSMMC2,
	},

	/* Multimedia1 (D1_1) devices */
	{
		.name		= "lcd",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d11_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D11_LCD,
	}, {
		.name		= "rotator",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d11_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D11_ROTATOR,
	}, {
		.name		= "fimc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d11_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D11_FIMC0,
	}, {
		.name		= "fimc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d11_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D11_FIMC1,
	}, {
		.name		= "fimc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d11_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D11_FIMC2,
	}, {
		.name		= "jpeg",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d11_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D11_JPEG,
	}, {
		.name		= "g3d",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d11_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D11_G3D,
	},

	/* Multimedia2 (D1_2) devices */
	{
		.name		= "tv",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d12_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D12_TV,
	}, {
		.name		= "vp",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d12_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D12_VP,
	}, {
		.name		= "mixer",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d12_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D12_MIXER,
	}, {
		.name		= "hdmi",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d12_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D12_HDMI,
	}, {
		.name		= "mfc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d12_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D12_MFC,
	},

	/* System (D1_3) devices */
	{
		.name		= "chipid",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d13_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D13_CHIPID,
	}, {
		.name		= "gpio",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d13_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D13_GPIO,
	}, {
		.name		= "apc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d13_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D13_APC,
	}, {
		.name		= "iec",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d13_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D13_IEC,
	}, {
		.name		= "timers",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d13_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D13_PWM,
	}, {
		.name		= "systimer",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d13_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D13_SYSTIMER,
	}, {
		.name		= "watchdog",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d13_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D13_WDT,
	}, {
		.name		= "rtc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d13_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D13_RTC,
	},

	/* Connectivity (D1_4) devices */
	{
		.name		= "uart",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_UART0,
	}, {
		.name		= "uart",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_UART1,
	}, {
		.name		= "uart",
		.id		= 2,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_UART2,
	}, {
		.name		= "uart",
		.id		= 3,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_UART3,
	}, {
		.name		= "i2c",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_IIC,
	}, {
		.name		= "hdmi-i2c",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_HDMI_IIC,
	}, {
		.name		= "spi",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_SPI0,
	}, {
		.name		= "spi",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_SPI1,
	}, {
		.name		= "spi",
		.id		= 2,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_SPI2,
	}, {
		.name		= "irda",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_IRDA,
	}, {
		.name		= "hsitx",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_HSITX,
	}, {
		.name		= "hsirx",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d14_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D14_HSIRX,
	},

	/* Audio (D1_5) devices */
	{
		.name		= "iis",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_IIS0,
	}, {
		.name		= "iis",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_IIS1,
	}, {
		.name		= "iis",
		.id		= 2,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_IIS2,
	}, {
		.name		= "ac97",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_AC97,
	}, {
		.name		= "pcm",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_PCM0,
	}, {
		.name		= "pcm",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_PCM1,
	}, {
		.name		= "spdif",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_SPDIF,
	}, {
		.name		= "adc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_TSADC,
	}, {
		.name		= "cg",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s5pc100_clk_d15_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_D15_CG,
	},

	/* Audio (D2_0) devices: all disabled */

	/* Special Clocks 0 */
	{
		.name		= "sclk_hpm",
		.id		= -1,
		.parent		= NULL,
		.enable		= s5pc100_sclk0_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_SCLK0_HPM,
	}, {
		.name		= "sclk_onenand",
		.id		= -1,
		.parent		= NULL,
		.enable		= s5pc100_sclk0_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_SCLK0_ONENAND,
	}, {
		.name		= "spi_48",
		.id		= 0,
		.parent		= &clk_48m,
		.enable		= s5pc100_sclk0_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_SCLK0_SPI0_48,
	}, {
		.name		= "spi_48",
		.id		= 1,
		.parent		= &clk_48m,
		.enable		= s5pc100_sclk0_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_SCLK0_SPI1_48,
	}, {
		.name		= "spi_48",
		.id		= 2,
		.parent		= &clk_48m,
		.enable		= s5pc100_sclk0_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_SCLK0_SPI2_48,
	}, {
		.name		= "mmc_48",
		.id		= 0,
		.parent		= &clk_48m,
		.enable		= s5pc100_sclk0_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_SCLK0_MMC0_48,
	}, {
		.name		= "mmc_48",
		.id		= 1,
		.parent		= &clk_48m,
		.enable		= s5pc100_sclk0_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_SCLK0_MMC1_48,
	}, {
		.name		= "mmc_48",
		.id		= 2,
		.parent		= &clk_48m,
		.enable		= s5pc100_sclk0_ctrl,
		.ctrlbit	= S5PC100_CLKGATE_SCLK0_MMC2_48,
	},
	/* Special Clocks 1 */
};

static struct clk *clks[] __initdata = {
	&clk_ext,
	&clk_epll,
	&clk_27m,
	&clk_48m,
	&clk_54m,
};

void __init s5pc1xx_register_clocks(void)
{
	struct clk *clkp;
	int ret;
	int ptr;
	int size;

	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));

	s3c_register_clocks(s5pc100_init_clocks,
			    ARRAY_SIZE(s5pc100_init_clocks));

	clkp = s5pc100_init_clocks_disable;
	size = ARRAY_SIZE(s5pc100_init_clocks_disable);

	for (ptr = 0; ptr < size; ptr++, clkp++) {
		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}

		(clkp->enable)(clkp, 0);
	}

	s3c_pwmclk_init();
}
Commit	Line	Data
ff916f25 KP	1	/* linux/arch/arm/plat-s5pc1xx/clock.c
	2	*
	3	* Copyright 2009 Samsung Electronics Co.
	4	*
	5	* S5PC1XX Base clock support
	6	*
	7	* Based on plat-s3c64xx/clock.c
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/module.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/ioport.h>
	18	#include <linux/clk.h>
	19	#include <linux/io.h>
	20
	21	#include <mach/hardware.h>
	22	#include <mach/map.h>
	23
	24	#include <plat/regs-clock.h>
	25	#include <plat/devs.h>
	26	#include <plat/clock.h>
	27
	28	struct clk clk_27m = {
	29	.name = "clk_27m",
	30	.id = -1,
	31	.rate = 27000000,
	32	};
	33
	34	static int clk_48m_ctrl(struct clk *clk, int enable)
	35	{
	36	unsigned long flags;
	37	u32 val;
	38
	39	/* can't rely on clock lock, this register has other usages */
	40	local_irq_save(flags);
	41
	42	val = __raw_readl(S5PC100_CLKSRC1);
	43	if (enable)
	44	val \|= S5PC100_CLKSRC1_CLK48M_MASK;
	45	else
	46	val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
	47
	48	__raw_writel(val, S5PC100_CLKSRC1);
	49	local_irq_restore(flags);
	50
	51	return 0;
	52	}
	53
	54	struct clk clk_48m = {
	55	.name = "clk_48m",
	56	.id = -1,
	57	.rate = 48000000,
	58	.enable = clk_48m_ctrl,
	59	};
	60
	61	struct clk clk_54m = {
	62	.name = "clk_54m",
	63	.id = -1,
	64	.rate = 54000000,
65	};
66
ff916f25 KP	67	static int clk_dummy_enable(struct clk *clk, int enable)
	68	{
	69	return 0;
	70	}
	71
	72	struct clk clk_hd0 = {
	73	.name = "hclkd0",
	74	.id = -1,
	75	.rate = 0,
	76	.parent = NULL,
	77	.ctrlbit = 0,
ff916f25	78	.enable = clk_dummy_enable,
ed276849	79	.ops = &clk_ops_def_setrate,
ff916f25 KP	80	};
	81
	82	struct clk clk_pd0 = {
	83	.name = "pclkd0",
	84	.id = -1,
	85	.rate = 0,
	86	.parent = NULL,
	87	.ctrlbit = 0,
ed276849	88	.ops = &clk_ops_def_setrate,
ff916f25 KP	89	.enable = clk_dummy_enable,
	90	};
	91
	92	static int s5pc1xx_clk_gate(void __iomem reg, struct clk clk, int enable)
	93	{
	94	unsigned int ctrlbit = clk->ctrlbit;
	95	u32 con;
	96
	97	con = __raw_readl(reg);
	98	if (enable)
	99	con \|= ctrlbit;
	100	else
	101	con &= ~ctrlbit;
	102	__raw_writel(con, reg);
	103
	104	return 0;
	105	}
	106
	107	static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
	108	{
	109	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
	110	}
	111
	112	static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
	113	{
	114	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
	115	}
	116
	117	static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
	118	{
	119	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
	120	}
	121
	122	static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
	123	{
	124	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
	125	}
	126
	127	static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
	128	{
	129	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
	130	}
	131
	132	static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
	133	{
	134	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
	135	}
	136
	137	static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
	138	{
	139	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
	140	}
	141
	142	static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
	143	{
	144	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
	145	}
	146
	147	static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
	148	{
	149	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
	150	}
	151
	152	static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
153	{
154	return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
155	}
156
157	int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
158	{
159	return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
160	}
161
162	int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
163	{
164	return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
165	}
166
167	static struct clk s5pc100_init_clocks_disable[] = {
168	{
169	.name = "dsi",
170	.id = -1,
171	.parent = &clk_p,
172	.enable = s5pc100_clk_d11_ctrl,
173	.ctrlbit = S5PC100_CLKGATE_D11_DSI,
174	}, {
175	.name = "csi",
176	.id = -1,
177	.parent = &clk_h,
178	.enable = s5pc100_clk_d11_ctrl,
179	.ctrlbit = S5PC100_CLKGATE_D11_CSI,
180	}, {
181	.name = "ccan",
182	.id = 0,
183	.parent = &clk_p,
184	.enable = s5pc100_clk_d14_ctrl,
185	.ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
186	}, {
187	.name = "ccan",
188	.id = 1,
189	.parent = &clk_p,
190	.enable = s5pc100_clk_d14_ctrl,
191	.ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
192	}, {
193	.name = "keypad",
194	.id = -1,
195	.parent = &clk_p,
196	.enable = s5pc100_clk_d15_ctrl,
197	.ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
198	}, {
199	.name = "hclkd2",
200	.id = -1,
201	.parent = NULL,
202	.enable = s5pc100_clk_d20_ctrl,
203	.ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
204	}, {
205	.name = "iis-d2",
206	.id = -1,
207	.parent = NULL,
208	.enable = s5pc100_clk_d20_ctrl,
209	.ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
210	},
211	};
212
213	static struct clk s5pc100_init_clocks[] = {
214	/* System1 (D0_0) devices */
215	{
216	.name = "intc",
217	.id = -1,
218	.parent = &clk_hd0,
219	.enable = s5pc100_clk_d00_ctrl,
220	.ctrlbit = S5PC100_CLKGATE_D00_INTC,
221	}, {
222	.name = "tzic",
223	.id = -1,
224	.parent = &clk_hd0,
225	.enable = s5pc100_clk_d00_ctrl,
226	.ctrlbit = S5PC100_CLKGATE_D00_TZIC,
227	}, {
228	.name = "cf-ata",
229	.id = -1,
230	.parent = &clk_hd0,
231	.enable = s5pc100_clk_d00_ctrl,
232	.ctrlbit = S5PC100_CLKGATE_D00_CFCON,
233	}, {
234	.name = "mdma",
235	.id = -1,
236	.parent = &clk_hd0,
237	.enable = s5pc100_clk_d00_ctrl,
238	.ctrlbit = S5PC100_CLKGATE_D00_MDMA,
239	}, {
240	.name = "g2d",
241	.id = -1,
242	.parent = &clk_hd0,
243	.enable = s5pc100_clk_d00_ctrl,
244	.ctrlbit = S5PC100_CLKGATE_D00_G2D,
245	}, {
246	.name = "secss",
247	.id = -1,
248	.parent = &clk_hd0,
249	.enable = s5pc100_clk_d00_ctrl,
250	.ctrlbit = S5PC100_CLKGATE_D00_SECSS,
251	}, {
252	.name = "cssys",
253	.id = -1,
254	.parent = &clk_hd0,
255	.enable = s5pc100_clk_d00_ctrl,
256	.ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
257	},
258
259	/* Memory (D0_1) devices */
260	{
261	.name = "dmc",
262	.id = -1,
263	.parent = &clk_hd0,
264	.enable = s5pc100_clk_d01_ctrl,
265	.ctrlbit = S5PC100_CLKGATE_D01_DMC,
266	}, {
267	.name = "sromc",
268	.id = -1,
269	.parent = &clk_hd0,
270	.enable = s5pc100_clk_d01_ctrl,
271	.ctrlbit = S5PC100_CLKGATE_D01_SROMC,
272	}, {
273	.name = "onenand",
274	.id = -1,
275	.parent = &clk_hd0,
276	.enable = s5pc100_clk_d01_ctrl,
277	.ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
278	}, {
279	.name = "nand",
280	.id = -1,
281	.parent = &clk_hd0,
282	.enable = s5pc100_clk_d01_ctrl,
283	.ctrlbit = S5PC100_CLKGATE_D01_NFCON,
284	}, {
285	.name = "intmem",
286	.id = -1,
287	.parent = &clk_hd0,
288	.enable = s5pc100_clk_d01_ctrl,
289	.ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
290	}, {
291	.name = "ebi",
292	.id = -1,
293	.parent = &clk_hd0,
294	.enable = s5pc100_clk_d01_ctrl,
295	.ctrlbit = S5PC100_CLKGATE_D01_EBI,
296	},
297
298	/* System2 (D0_2) devices */
299	{
300	.name = "seckey",
301	.id = -1,
302	.parent = &clk_pd0,
303	.enable = s5pc100_clk_d02_ctrl,
304	.ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
305	}, {
306	.name = "sdm",
307	.id = -1,
308	.parent = &clk_hd0,
309	.enable = s5pc100_clk_d02_ctrl,
310	.ctrlbit = S5PC100_CLKGATE_D02_SDM,
311	},
312
313	/* File (D1_0) devices */
314	{
315	.name = "pdma",
316	.id = 0,
317	.parent = &clk_h,
318	.enable = s5pc100_clk_d10_ctrl,
319	.ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
320	}, {
321	.name = "pdma",
322	.id = 1,
323	.parent = &clk_h,
324	.enable = s5pc100_clk_d10_ctrl,
325	.ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
326	}, {
327	.name = "usb-host",
328	.id = -1,
329	.parent = &clk_h,
330	.enable = s5pc100_clk_d10_ctrl,
331	.ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
332	}, {
333	.name = "otg",
334	.id = -1,
335	.parent = &clk_h,
336	.enable = s5pc100_clk_d10_ctrl,
337	.ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
338	}, {
339	.name = "modem",
340	.id = -1,
341	.parent = &clk_h,
342	.enable = s5pc100_clk_d10_ctrl,
343	.ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
344	}, {
345	.name = "hsmmc",
346	.id = 0,
347	.parent = &clk_48m,
348	.enable = s5pc100_clk_d10_ctrl,
349	.ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
350	}, {
351	.name = "hsmmc",
352	.id = 1,
353	.parent = &clk_48m,
354	.enable = s5pc100_clk_d10_ctrl,
355	.ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
356	}, {
357	.name = "hsmmc",
358	.id = 2,
359	.parent = &clk_48m,
360	.enable = s5pc100_clk_d10_ctrl,
361	.ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
362	},
363
364	/* Multimedia1 (D1_1) devices */
365	{
366	.name = "lcd",
367	.id = -1,
368	.parent = &clk_p,
369	.enable = s5pc100_clk_d11_ctrl,
370	.ctrlbit = S5PC100_CLKGATE_D11_LCD,
371	}, {
372	.name = "rotator",
373	.id = -1,
374	.parent = &clk_p,
375	.enable = s5pc100_clk_d11_ctrl,
376	.ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
377	}, {
378	.name = "fimc",
379	.id = -1,
380	.parent = &clk_p,
381	.enable = s5pc100_clk_d11_ctrl,
382	.ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
383	}, {
384	.name = "fimc",
385	.id = -1,
386	.parent = &clk_p,
387	.enable = s5pc100_clk_d11_ctrl,
388	.ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
389	}, {
390	.name = "fimc",
391	.id = -1,
392	.parent = &clk_p,
393	.enable = s5pc100_clk_d11_ctrl,
394	.ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
395	}, {
396	.name = "jpeg",
397	.id = -1,
398	.parent = &clk_p,
399	.enable = s5pc100_clk_d11_ctrl,
400	.ctrlbit = S5PC100_CLKGATE_D11_JPEG,
401	}, {
402	.name = "g3d",
403	.id = -1,
404	.parent = &clk_p,
405	.enable = s5pc100_clk_d11_ctrl,
406	.ctrlbit = S5PC100_CLKGATE_D11_G3D,
407	},
408
409	/* Multimedia2 (D1_2) devices */
410	{
411	.name = "tv",
412	.id = -1,
413	.parent = &clk_p,
414	.enable = s5pc100_clk_d12_ctrl,
415	.ctrlbit = S5PC100_CLKGATE_D12_TV,
416	}, {
417	.name = "vp",
418	.id = -1,
419	.parent = &clk_p,
420	.enable = s5pc100_clk_d12_ctrl,
421	.ctrlbit = S5PC100_CLKGATE_D12_VP,
422	}, {
423	.name = "mixer",
424	.id = -1,
425	.parent = &clk_p,
426	.enable = s5pc100_clk_d12_ctrl,
427	.ctrlbit = S5PC100_CLKGATE_D12_MIXER,
428	}, {
429	.name = "hdmi",
430	.id = -1,
431	.parent = &clk_p,
432	.enable = s5pc100_clk_d12_ctrl,
433	.ctrlbit = S5PC100_CLKGATE_D12_HDMI,
434	}, {
435	.name = "mfc",
436	.id = -1,
437	.parent = &clk_p,
438	.enable = s5pc100_clk_d12_ctrl,
439	.ctrlbit = S5PC100_CLKGATE_D12_MFC,
440	},
441
442	/* System (D1_3) devices */
443	{
444	.name = "chipid",
445	.id = -1,
446	.parent = &clk_p,
447	.enable = s5pc100_clk_d13_ctrl,
448	.ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
449	}, {
450	.name = "gpio",
451	.id = -1,
452	.parent = &clk_p,
453	.enable = s5pc100_clk_d13_ctrl,
454	.ctrlbit = S5PC100_CLKGATE_D13_GPIO,
455	}, {
456	.name = "apc",
457	.id = -1,
458	.parent = &clk_p,
459	.enable = s5pc100_clk_d13_ctrl,
460	.ctrlbit = S5PC100_CLKGATE_D13_APC,
461	}, {
462	.name = "iec",
463	.id = -1,
464	.parent = &clk_p,
465	.enable = s5pc100_clk_d13_ctrl,
466	.ctrlbit = S5PC100_CLKGATE_D13_IEC,
467	}, {
468	.name = "timers",
469	.id = -1,
470	.parent = &clk_p,
471	.enable = s5pc100_clk_d13_ctrl,
472	.ctrlbit = S5PC100_CLKGATE_D13_PWM,
473	}, {
474	.name = "systimer",
475	.id = -1,
476	.parent = &clk_p,
477	.enable = s5pc100_clk_d13_ctrl,
478	.ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
479	}, {
480	.name = "watchdog",
481	.id = -1,
482	.parent = &clk_p,
483	.enable = s5pc100_clk_d13_ctrl,
484	.ctrlbit = S5PC100_CLKGATE_D13_WDT,
485	}, {
486	.name = "rtc",
487	.id = -1,
488	.parent = &clk_p,
489	.enable = s5pc100_clk_d13_ctrl,
490	.ctrlbit = S5PC100_CLKGATE_D13_RTC,
491	},
492
493	/* Connectivity (D1_4) devices */
494	{
495	.name = "uart",
496	.id = 0,
497	.parent = &clk_p,
498	.enable = s5pc100_clk_d14_ctrl,
499	.ctrlbit = S5PC100_CLKGATE_D14_UART0,
500	}, {
501	.name = "uart",
502	.id = 1,
503	.parent = &clk_p,
504	.enable = s5pc100_clk_d14_ctrl,
505	.ctrlbit = S5PC100_CLKGATE_D14_UART1,
506	}, {
507	.name = "uart",
508	.id = 2,
509	.parent = &clk_p,
510	.enable = s5pc100_clk_d14_ctrl,
511	.ctrlbit = S5PC100_CLKGATE_D14_UART2,
512	}, {
513	.name = "uart",
514	.id = 3,
515	.parent = &clk_p,
516	.enable = s5pc100_clk_d14_ctrl,
517	.ctrlbit = S5PC100_CLKGATE_D14_UART3,
518	}, {
519	.name = "i2c",
520	.id = -1,
521	.parent = &clk_p,
522	.enable = s5pc100_clk_d14_ctrl,
523	.ctrlbit = S5PC100_CLKGATE_D14_IIC,
524	}, {
525	.name = "hdmi-i2c",
526	.id = -1,
527	.parent = &clk_p,
528	.enable = s5pc100_clk_d14_ctrl,
529	.ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
530	}, {
531	.name = "spi",
532	.id = 0,
533	.parent = &clk_p,
534	.enable = s5pc100_clk_d14_ctrl,
535	.ctrlbit = S5PC100_CLKGATE_D14_SPI0,
536	}, {
537	.name = "spi",
538	.id = 1,
539	.parent = &clk_p,
540	.enable = s5pc100_clk_d14_ctrl,
541	.ctrlbit = S5PC100_CLKGATE_D14_SPI1,
542	}, {
543	.name = "spi",
544	.id = 2,
545	.parent = &clk_p,
546	.enable = s5pc100_clk_d14_ctrl,
547	.ctrlbit = S5PC100_CLKGATE_D14_SPI2,
548	}, {
549	.name = "irda",
550	.id = -1,
551	.parent = &clk_p,
552	.enable = s5pc100_clk_d14_ctrl,
553	.ctrlbit = S5PC100_CLKGATE_D14_IRDA,
554	}, {
555	.name = "hsitx",
556	.id = -1,
557	.parent = &clk_p,
558	.enable = s5pc100_clk_d14_ctrl,
559	.ctrlbit = S5PC100_CLKGATE_D14_HSITX,
560	}, {
561	.name = "hsirx",
562	.id = -1,
563	.parent = &clk_p,
564	.enable = s5pc100_clk_d14_ctrl,
565	.ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
566	},
567
568	/* Audio (D1_5) devices */
569	{
570	.name = "iis",
571	.id = 0,
572	.parent = &clk_p,
573	.enable = s5pc100_clk_d15_ctrl,
574	.ctrlbit = S5PC100_CLKGATE_D15_IIS0,
575	}, {
576	.name = "iis",
577	.id = 1,
578	.parent = &clk_p,
579	.enable = s5pc100_clk_d15_ctrl,
580	.ctrlbit = S5PC100_CLKGATE_D15_IIS1,
581	}, {
582	.name = "iis",
583	.id = 2,
584	.parent = &clk_p,
585	.enable = s5pc100_clk_d15_ctrl,
586	.ctrlbit = S5PC100_CLKGATE_D15_IIS2,
587	}, {
588	.name = "ac97",
589	.id = -1,
590	.parent = &clk_p,
591	.enable = s5pc100_clk_d15_ctrl,
592	.ctrlbit = S5PC100_CLKGATE_D15_AC97,
593	}, {
594	.name = "pcm",
595	.id = 0,
596	.parent = &clk_p,
597	.enable = s5pc100_clk_d15_ctrl,
598	.ctrlbit = S5PC100_CLKGATE_D15_PCM0,
599	}, {
600	.name = "pcm",
601	.id = 1,
602	.parent = &clk_p,
603	.enable = s5pc100_clk_d15_ctrl,
604	.ctrlbit = S5PC100_CLKGATE_D15_PCM1,
605	}, {
606	.name = "spdif",
607	.id = -1,
608	.parent = &clk_p,
609	.enable = s5pc100_clk_d15_ctrl,
610	.ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
611	}, {
612	.name = "adc",
613	.id = -1,
614	.parent = &clk_p,
615	.enable = s5pc100_clk_d15_ctrl,
616	.ctrlbit = S5PC100_CLKGATE_D15_TSADC,
617	}, {
618	.name = "cg",
619	.id = -1,
620	.parent = &clk_p,
621	.enable = s5pc100_clk_d15_ctrl,
622	.ctrlbit = S5PC100_CLKGATE_D15_CG,
623	},
624
625	/* Audio (D2_0) devices: all disabled */
626
627	/* Special Clocks 0 */
628	{
629	.name = "sclk_hpm",
630	.id = -1,
631	.parent = NULL,
632	.enable = s5pc100_sclk0_ctrl,
633	.ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
634	}, {
635	.name = "sclk_onenand",
636	.id = -1,
637	.parent = NULL,
638	.enable = s5pc100_sclk0_ctrl,
639	.ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
640	}, {
641	.name = "spi_48",
642	.id = 0,
643	.parent = &clk_48m,
644	.enable = s5pc100_sclk0_ctrl,
645	.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
646	}, {
647	.name = "spi_48",
648	.id = 1,
649	.parent = &clk_48m,
650	.enable = s5pc100_sclk0_ctrl,
651	.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
652	}, {
653	.name = "spi_48",
654	.id = 2,
655	.parent = &clk_48m,
656	.enable = s5pc100_sclk0_ctrl,
657	.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
658	}, {
659	.name = "mmc_48",
660	.id = 0,
661	.parent = &clk_48m,
662	.enable = s5pc100_sclk0_ctrl,
663	.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
664	}, {
665	.name = "mmc_48",
666	.id = 1,
667	.parent = &clk_48m,
668	.enable = s5pc100_sclk0_ctrl,
669	.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
670	}, {
671	.name = "mmc_48",
672	.id = 2,
673	.parent = &clk_48m,
674	.enable = s5pc100_sclk0_ctrl,
675	.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
676	},
677	/* Special Clocks 1 */
678	};
679
680	static struct clk *clks[] __initdata = {
681	&clk_ext,
682	&clk_epll,
683	&clk_27m,
684	&clk_48m,
685	&clk_54m,
686	};
687
688	void __init s5pc1xx_register_clocks(void)
689	{
690	struct clk *clkp;
691	int ret;
692	int ptr;
693	int size;
694
695	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
696
1d9f13c4 BD	697	s3c_register_clocks(s5pc100_init_clocks,
1d9f13c4 BD	698	ARRAY_SIZE(s5pc100_init_clocks));
ff916f25 KP	699
	700	clkp = s5pc100_init_clocks_disable;
	701	size = ARRAY_SIZE(s5pc100_init_clocks_disable);
	702
	703	for (ptr = 0; ptr < size; ptr++, clkp++) {
	704	ret = s3c24xx_register_clock(clkp);
	705	if (ret < 0) {
	706	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	707	clkp->name, ret);
	708	}
	709
	710	(clkp->enable)(clkp, 0);
	711	}
	712
	713	s3c_pwmclk_init();
	714	}