[net-next-2.6.git] / arch / arm / plat-s3c24xx / gpiolib.c

/* linux/arch/arm/plat-s3c24xx/gpiolib.c
 *
 * Copyright (c) 2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX GPIOlib support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/sysdev.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/pm.h>

#include <mach/regs-gpio.h>

static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
{
	return -EINVAL;
}

static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
	void __iomem *base = ourchip->base;
	unsigned long flags;
	unsigned long dat;
	unsigned long con;

	local_irq_save(flags);

	con = __raw_readl(base + 0x00);
	dat = __raw_readl(base + 0x04);

	dat &= ~(1 << offset);
	if (value)
		dat |= 1 << offset;

	__raw_writel(dat, base + 0x04);

	con &= ~(1 << offset);

	__raw_writel(con, base + 0x00);
	__raw_writel(dat, base + 0x04);

	local_irq_restore(flags);
	return 0;
}

static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
{
	if (offset < 4)
		return IRQ_EINT0 + offset;
	
	if (offset < 8)
		return IRQ_EINT4 + offset - 4;
	
	return -EINVAL;
}

static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
{
	return IRQ_EINT8 + offset;
}

static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
	.set_config	= s3c_gpio_setcfg_s3c24xx_a,
};

struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
	.set_config	= s3c_gpio_setcfg_s3c24xx,
};

struct s3c_gpio_chip s3c24xx_gpios[] = {
	[0] = {
		.base	= S3C2410_GPACON,
		.pm	= __gpio_pm(&s3c_gpio_pm_1bit),
		.config	= &s3c24xx_gpiocfg_banka,
		.chip	= {
			.base			= S3C2410_GPA(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOA",
			.ngpio			= 24,
			.direction_input	= s3c24xx_gpiolib_banka_input,
			.direction_output	= s3c24xx_gpiolib_banka_output,
		},
	},
	[1] = {
		.base	= S3C2410_GPBCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPB(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOB",
			.ngpio			= 16,
		},
	},
	[2] = {
		.base	= S3C2410_GPCCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPC(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOC",
			.ngpio			= 16,
		},
	},
	[3] = {
		.base	= S3C2410_GPDCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPD(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOD",
			.ngpio			= 16,
		},
	},
	[4] = {
		.base	= S3C2410_GPECON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPE(0),
			.label			= "GPIOE",
			.owner			= THIS_MODULE,
			.ngpio			= 16,
		},
	},
	[5] = {
		.base	= S3C2410_GPFCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPF(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOF",
			.ngpio			= 8,
			.to_irq			= s3c24xx_gpiolib_bankf_toirq,
		},
	},
	[6] = {
		.base	= S3C2410_GPGCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPG(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOG",
			.ngpio			= 16,
			.to_irq			= s3c24xx_gpiolib_bankg_toirq,
		},
	}, {
		.base	= S3C2410_GPHCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPH(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOH",
			.ngpio			= 11,
		},
	},
};

static __init int s3c24xx_gpiolib_init(void)
{
	struct s3c_gpio_chip *chip = s3c24xx_gpios;
	int gpn;

	for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
		if (!chip->config)
			chip->config = &s3c24xx_gpiocfg_default;

		s3c_gpiolib_add(chip);
	}

	return 0;
}

core_initcall(s3c24xx_gpiolib_init);
Commit	Line	Data
f348a2a2 BD	1	/* linux/arch/arm/plat-s3c24xx/gpiolib.c
	2	*
	3	* Copyright (c) 2008 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C24XX GPIOlib support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/interrupt.h>
86c03c52	18	#include <linux/sysdev.h>
f348a2a2 BD	19	#include <linux/ioport.h>
	20	#include <linux/io.h>
	21	#include <linux/gpio.h>
	22
e856bb1f	23	#include <plat/gpio-core.h>
9bbb851c BD	24	#include <plat/gpio-cfg.h>
9bbb851c BD	25	#include <plat/gpio-cfg-helpers.h>
a09e64fb	26	#include <mach/hardware.h>
f348a2a2	27	#include <asm/irq.h>
d87964c4	28	#include <plat/pm.h>
f348a2a2	29
a09e64fb	30	#include <mach/regs-gpio.h>
f348a2a2	31
f348a2a2 BD	32	static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
	33	{
	34	return -EINVAL;
	35	}
	36
	37	static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
	38	unsigned offset, int value)
	39	{
7db6c82a	40	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
f348a2a2 BD	41	void __iomem *base = ourchip->base;
	42	unsigned long flags;
	43	unsigned long dat;
	44	unsigned long con;
	45
	46	local_irq_save(flags);
	47
	48	con = __raw_readl(base + 0x00);
	49	dat = __raw_readl(base + 0x04);
	50
	51	dat &= ~(1 << offset);
	52	if (value)
	53	dat \|= 1 << offset;
	54
	55	__raw_writel(dat, base + 0x04);
	56
	57	con &= ~(1 << offset);
	58
	59	__raw_writel(con, base + 0x00);
	60	__raw_writel(dat, base + 0x04);
	61
	62	local_irq_restore(flags);
	63	return 0;
	64	}
	65
43ae6599 BD	66	static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
	67	{
	68	if (offset < 4)
	69	return IRQ_EINT0 + offset;
	70
	71	if (offset < 8)
	72	return IRQ_EINT4 + offset - 4;
	73
	74	return -EINVAL;
	75	}
	76
	77	static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
	78	{
	79	return IRQ_EINT8 + offset;
	80	}
	81
9bbb851c BD	82	static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
	83	.set_config = s3c_gpio_setcfg_s3c24xx_a,
	84	};
	85
	86	struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
	87	.set_config = s3c_gpio_setcfg_s3c24xx,
	88	};
	89
21b23664	90	struct s3c_gpio_chip s3c24xx_gpios[] = {
f348a2a2	91	[0] = {
fda7b2b0	92	.base = S3C2410_GPACON,
d87964c4	93	.pm = __gpio_pm(&s3c_gpio_pm_1bit),
9bbb851c	94	.config = &s3c24xx_gpiocfg_banka,
f348a2a2	95	.chip = {
070276d5	96	.base = S3C2410_GPA(0),
f348a2a2 BD	97	.owner = THIS_MODULE,
	98	.label = "GPIOA",
	99	.ngpio = 24,
	100	.direction_input = s3c24xx_gpiolib_banka_input,
	101	.direction_output = s3c24xx_gpiolib_banka_output,
f348a2a2 BD	102	},
	103	},
	104	[1] = {
fda7b2b0	105	.base = S3C2410_GPBCON,
d87964c4	106	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	107	.chip = {
070276d5	108	.base = S3C2410_GPB(0),
f348a2a2 BD	109	.owner = THIS_MODULE,
	110	.label = "GPIOB",
	111	.ngpio = 16,
f348a2a2 BD	112	},
	113	},
	114	[2] = {
fda7b2b0	115	.base = S3C2410_GPCCON,
d87964c4	116	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	117	.chip = {
070276d5	118	.base = S3C2410_GPC(0),
f348a2a2 BD	119	.owner = THIS_MODULE,
	120	.label = "GPIOC",
	121	.ngpio = 16,
f348a2a2 BD	122	},
	123	},
	124	[3] = {
fda7b2b0	125	.base = S3C2410_GPDCON,
d87964c4	126	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	127	.chip = {
070276d5	128	.base = S3C2410_GPD(0),
f348a2a2 BD	129	.owner = THIS_MODULE,
	130	.label = "GPIOD",
	131	.ngpio = 16,
f348a2a2 BD	132	},
	133	},
	134	[4] = {
fda7b2b0	135	.base = S3C2410_GPECON,
d87964c4	136	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	137	.chip = {
070276d5	138	.base = S3C2410_GPE(0),
f348a2a2 BD	139	.label = "GPIOE",
	140	.owner = THIS_MODULE,
	141	.ngpio = 16,
f348a2a2 BD	142	},
	143	},
	144	[5] = {
fda7b2b0	145	.base = S3C2410_GPFCON,
d87964c4	146	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	147	.chip = {
070276d5	148	.base = S3C2410_GPF(0),
f348a2a2 BD	149	.owner = THIS_MODULE,
	150	.label = "GPIOF",
	151	.ngpio = 8,
43ae6599	152	.to_irq = s3c24xx_gpiolib_bankf_toirq,
f348a2a2 BD	153	},
	154	},
	155	[6] = {
fda7b2b0	156	.base = S3C2410_GPGCON,
d87964c4	157	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	158	.chip = {
070276d5	159	.base = S3C2410_GPG(0),
f348a2a2 BD	160	.owner = THIS_MODULE,
f348a2a2 BD	161	.label = "GPIOG",
5233c178	162	.ngpio = 16,
43ae6599	163	.to_irq = s3c24xx_gpiolib_bankg_toirq,
f348a2a2	164	},
5233c178 BD	165	}, {
	166	.base = S3C2410_GPHCON,
	167	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	168	.chip = {
	169	.base = S3C2410_GPH(0),
	170	.owner = THIS_MODULE,
	171	.label = "GPIOH",
	172	.ngpio = 11,
	173	},
f348a2a2 BD	174	},
	175	};
	176
	177	static __init int s3c24xx_gpiolib_init(void)
	178	{
21b23664	179	struct s3c_gpio_chip *chip = s3c24xx_gpios;
f348a2a2 BD	180	int gpn;
f348a2a2 BD	181
9bbb851c BD	182	for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
	183	if (!chip->config)
	184	chip->config = &s3c24xx_gpiocfg_default;
	185
7db6c82a	186	s3c_gpiolib_add(chip);
9bbb851c	187	}
f348a2a2 BD	188
	189	return 0;
	190	}
	191
9c0ec957	192	core_initcall(s3c24xx_gpiolib_init);