[net-next-2.6.git] / arch / arm / plat-s3c24xx / gpiolib.c

/* linux/arch/arm/plat-s3c24xx/gpiolib.c
 *
 * Copyright (c) 2008-2010 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX GPIOlib support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/sysdev.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/pm.h>

#include <mach/regs-gpio.h>

static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
{
	return -EINVAL;
}

static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
	void __iomem *base = ourchip->base;
	unsigned long flags;
	unsigned long dat;
	unsigned long con;

	local_irq_save(flags);

	con = __raw_readl(base + 0x00);
	dat = __raw_readl(base + 0x04);

	dat &= ~(1 << offset);
	if (value)
		dat |= 1 << offset;

	__raw_writel(dat, base + 0x04);

	con &= ~(1 << offset);

	__raw_writel(con, base + 0x00);
	__raw_writel(dat, base + 0x04);

	local_irq_restore(flags);
	return 0;
}

static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
{
	if (offset < 4)
		return IRQ_EINT0 + offset;
	
	if (offset < 8)
		return IRQ_EINT4 + offset - 4;
	
	return -EINVAL;
}

static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
	.set_config	= s3c_gpio_setcfg_s3c24xx_a,
	.get_config	= s3c_gpio_getcfg_s3c24xx_a,
};

struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
	.set_config	= s3c_gpio_setcfg_s3c24xx,
	.get_config	= s3c_gpio_getcfg_s3c24xx,
	.set_pull	= s3c_gpio_setpull_1up,
	.get_pull	= s3c_gpio_getpull_1up,
};

struct s3c_gpio_chip s3c24xx_gpios[] = {
	[0] = {
		.base	= S3C2410_GPACON,
		.pm	= __gpio_pm(&s3c_gpio_pm_1bit),
		.config	= &s3c24xx_gpiocfg_banka,
		.chip	= {
			.base			= S3C2410_GPA(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOA",
			.ngpio			= 24,
			.direction_input	= s3c24xx_gpiolib_banka_input,
			.direction_output	= s3c24xx_gpiolib_banka_output,
		},
	},
	[1] = {
		.base	= S3C2410_GPBCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPB(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOB",
			.ngpio			= 16,
		},
	},
	[2] = {
		.base	= S3C2410_GPCCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPC(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOC",
			.ngpio			= 16,
		},
	},
	[3] = {
		.base	= S3C2410_GPDCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPD(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOD",
			.ngpio			= 16,
		},
	},
	[4] = {
		.base	= S3C2410_GPECON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPE(0),
			.label			= "GPIOE",
			.owner			= THIS_MODULE,
			.ngpio			= 16,
		},
	},
	[5] = {
		.base	= S3C2410_GPFCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPF(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOF",
			.ngpio			= 8,
			.to_irq			= s3c24xx_gpiolib_bankf_toirq,
		},
	},
	[6] = {
		.base	= S3C2410_GPGCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.irq_base = IRQ_EINT8,
		.chip	= {
			.base			= S3C2410_GPG(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOG",
			.ngpio			= 16,
			.to_irq			= samsung_gpiolib_to_irq,
		},
	}, {
		.base	= S3C2410_GPHCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPH(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOH",
			.ngpio			= 11,
		},
	},
		/* GPIOS for the S3C2443 and later devices. */
	{
		.base	= S3C2440_GPJCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPJ(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOJ",
			.ngpio			= 16,
		},
	}, {
		.base	= S3C2443_GPKCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPK(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOK",
			.ngpio			= 16,
		},
	}, {
		.base	= S3C2443_GPLCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPL(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOL",
			.ngpio			= 15,
		},
	}, {
		.base	= S3C2443_GPMCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPM(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOM",
			.ngpio			= 2,
		},
	},
};


static __init int s3c24xx_gpiolib_init(void)
{
	struct s3c_gpio_chip *chip = s3c24xx_gpios;
	int gpn;

	for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
		if (!chip->config)
			chip->config = &s3c24xx_gpiocfg_default;

		s3c_gpiolib_add(chip);
	}

	return 0;
}

core_initcall(s3c24xx_gpiolib_init);
Commit	Line	Data
f348a2a2 BD	1	/* linux/arch/arm/plat-s3c24xx/gpiolib.c
f348a2a2 BD	2	*
7ced5eab	3	* Copyright (c) 2008-2010 Simtec Electronics
f348a2a2 BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C24XX GPIOlib support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/interrupt.h>
86c03c52	18	#include <linux/sysdev.h>
f348a2a2 BD	19	#include <linux/ioport.h>
	20	#include <linux/io.h>
	21	#include <linux/gpio.h>
	22
e856bb1f	23	#include <plat/gpio-core.h>
9bbb851c BD	24	#include <plat/gpio-cfg.h>
9bbb851c BD	25	#include <plat/gpio-cfg-helpers.h>
a09e64fb	26	#include <mach/hardware.h>
f348a2a2	27	#include <asm/irq.h>
d87964c4	28	#include <plat/pm.h>
f348a2a2	29
a09e64fb	30	#include <mach/regs-gpio.h>
f348a2a2	31
f348a2a2 BD	32	static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
	33	{
	34	return -EINVAL;
	35	}
	36
	37	static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
	38	unsigned offset, int value)
	39	{
7db6c82a	40	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
f348a2a2 BD	41	void __iomem *base = ourchip->base;
	42	unsigned long flags;
	43	unsigned long dat;
	44	unsigned long con;
	45
	46	local_irq_save(flags);
	47
	48	con = __raw_readl(base + 0x00);
	49	dat = __raw_readl(base + 0x04);
	50
	51	dat &= ~(1 << offset);
	52	if (value)
	53	dat \|= 1 << offset;
	54
	55	__raw_writel(dat, base + 0x04);
	56
	57	con &= ~(1 << offset);
	58
	59	__raw_writel(con, base + 0x00);
	60	__raw_writel(dat, base + 0x04);
	61
	62	local_irq_restore(flags);
	63	return 0;
	64	}
	65
43ae6599 BD	66	static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
	67	{
	68	if (offset < 4)
	69	return IRQ_EINT0 + offset;
	70
	71	if (offset < 8)
	72	return IRQ_EINT4 + offset - 4;
	73
	74	return -EINVAL;
	75	}
	76
9bbb851c BD	77	static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
9bbb851c BD	78	.set_config = s3c_gpio_setcfg_s3c24xx_a,
97a33999	79	.get_config = s3c_gpio_getcfg_s3c24xx_a,
9bbb851c BD	80	};
	81
	82	struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
	83	.set_config = s3c_gpio_setcfg_s3c24xx,
97a33999	84	.get_config = s3c_gpio_getcfg_s3c24xx,
bdf5005b AWG	85	.set_pull = s3c_gpio_setpull_1up,
bdf5005b AWG	86	.get_pull = s3c_gpio_getpull_1up,
9bbb851c BD	87	};
9bbb851c BD	88
21b23664	89	struct s3c_gpio_chip s3c24xx_gpios[] = {
f348a2a2	90	[0] = {
fda7b2b0	91	.base = S3C2410_GPACON,
d87964c4	92	.pm = __gpio_pm(&s3c_gpio_pm_1bit),
9bbb851c	93	.config = &s3c24xx_gpiocfg_banka,
f348a2a2	94	.chip = {
070276d5	95	.base = S3C2410_GPA(0),
f348a2a2 BD	96	.owner = THIS_MODULE,
	97	.label = "GPIOA",
	98	.ngpio = 24,
	99	.direction_input = s3c24xx_gpiolib_banka_input,
	100	.direction_output = s3c24xx_gpiolib_banka_output,
f348a2a2 BD	101	},
	102	},
	103	[1] = {
fda7b2b0	104	.base = S3C2410_GPBCON,
d87964c4	105	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	106	.chip = {
070276d5	107	.base = S3C2410_GPB(0),
f348a2a2 BD	108	.owner = THIS_MODULE,
	109	.label = "GPIOB",
	110	.ngpio = 16,
f348a2a2 BD	111	},
	112	},
	113	[2] = {
fda7b2b0	114	.base = S3C2410_GPCCON,
d87964c4	115	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	116	.chip = {
070276d5	117	.base = S3C2410_GPC(0),
f348a2a2 BD	118	.owner = THIS_MODULE,
	119	.label = "GPIOC",
	120	.ngpio = 16,
f348a2a2 BD	121	},
	122	},
	123	[3] = {
fda7b2b0	124	.base = S3C2410_GPDCON,
d87964c4	125	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	126	.chip = {
070276d5	127	.base = S3C2410_GPD(0),
f348a2a2 BD	128	.owner = THIS_MODULE,
	129	.label = "GPIOD",
	130	.ngpio = 16,
f348a2a2 BD	131	},
	132	},
	133	[4] = {
fda7b2b0	134	.base = S3C2410_GPECON,
d87964c4	135	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	136	.chip = {
070276d5	137	.base = S3C2410_GPE(0),
f348a2a2 BD	138	.label = "GPIOE",
	139	.owner = THIS_MODULE,
	140	.ngpio = 16,
f348a2a2 BD	141	},
	142	},
	143	[5] = {
fda7b2b0	144	.base = S3C2410_GPFCON,
d87964c4	145	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	146	.chip = {
070276d5	147	.base = S3C2410_GPF(0),
f348a2a2 BD	148	.owner = THIS_MODULE,
	149	.label = "GPIOF",
	150	.ngpio = 8,
43ae6599	151	.to_irq = s3c24xx_gpiolib_bankf_toirq,
f348a2a2 BD	152	},
	153	},
	154	[6] = {
fda7b2b0	155	.base = S3C2410_GPGCON,
d87964c4	156	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
8ce14a22	157	.irq_base = IRQ_EINT8,
f348a2a2	158	.chip = {
070276d5	159	.base = S3C2410_GPG(0),
f348a2a2 BD	160	.owner = THIS_MODULE,
f348a2a2 BD	161	.label = "GPIOG",
5233c178	162	.ngpio = 16,
8ce14a22	163	.to_irq = samsung_gpiolib_to_irq,
f348a2a2	164	},
5233c178 BD	165	}, {
	166	.base = S3C2410_GPHCON,
	167	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	168	.chip = {
	169	.base = S3C2410_GPH(0),
	170	.owner = THIS_MODULE,
	171	.label = "GPIOH",
	172	.ngpio = 11,
	173	},
f348a2a2	174	},
7ced5eab BD	175	/* GPIOS for the S3C2443 and later devices. */
	176	{
	177	.base = S3C2440_GPJCON,
	178	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	179	.chip = {
	180	.base = S3C2410_GPJ(0),
	181	.owner = THIS_MODULE,
	182	.label = "GPIOJ",
	183	.ngpio = 16,
	184	},
	185	}, {
	186	.base = S3C2443_GPKCON,
	187	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	188	.chip = {
	189	.base = S3C2410_GPK(0),
	190	.owner = THIS_MODULE,
	191	.label = "GPIOK",
	192	.ngpio = 16,
	193	},
	194	}, {
	195	.base = S3C2443_GPLCON,
	196	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	197	.chip = {
	198	.base = S3C2410_GPL(0),
	199	.owner = THIS_MODULE,
	200	.label = "GPIOL",
	201	.ngpio = 15,
	202	},
	203	}, {
	204	.base = S3C2443_GPMCON,
	205	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	206	.chip = {
	207	.base = S3C2410_GPM(0),
	208	.owner = THIS_MODULE,
	209	.label = "GPIOM",
	210	.ngpio = 2,
	211	},
	212	},
f348a2a2 BD	213	};
f348a2a2 BD	214
7ced5eab	215
f348a2a2 BD	216	static __init int s3c24xx_gpiolib_init(void)
f348a2a2 BD	217	{
21b23664	218	struct s3c_gpio_chip *chip = s3c24xx_gpios;
f348a2a2 BD	219	int gpn;
f348a2a2 BD	220
9bbb851c BD	221	for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
	222	if (!chip->config)
	223	chip->config = &s3c24xx_gpiocfg_default;
	224
7db6c82a	225	s3c_gpiolib_add(chip);
9bbb851c	226	}
f348a2a2 BD	227
	228	return 0;
	229	}
	230
9c0ec957	231	core_initcall(s3c24xx_gpiolib_init);