[net-next-2.6.git] / arch / arm / plat-s3c24xx / cpu.c

/* linux/arch/arm/plat-s3c24xx/cpu.c
 *
 * Copyright (c) 2004-2005 Simtec Electronics
 *	http://www.simtec.co.uk/products/SWLINUX/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX CPU Support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/


#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/delay.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/cacheflush.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include <mach/system-reset.h>

#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>

#include <plat/cpu.h>
#include <plat/devs.h>
#include <asm/plat-s3c24xx/clock.h>
#include <plat/s3c2400.h>
#include <plat/s3c2410.h>
#include <asm/plat-s3c24xx/s3c2412.h>
#include "s3c244x.h"
#include <plat/s3c2440.h>
#include <plat/s3c2442.h>
#include <plat/s3c2443.h>

struct cpu_table {
	unsigned long	idcode;
	unsigned long	idmask;
	void		(*map_io)(struct map_desc *mach_desc, int size);
	void		(*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
	void		(*init_clocks)(int xtal);
	int		(*init)(void);
	const char	*name;
};

/* table of supported CPUs */

static const char name_s3c2400[]  = "S3C2400";
static const char name_s3c2410[]  = "S3C2410";
static const char name_s3c2412[]  = "S3C2412";
static const char name_s3c2440[]  = "S3C2440";
static const char name_s3c2442[]  = "S3C2442";
static const char name_s3c2443[]  = "S3C2443";
static const char name_s3c2410a[] = "S3C2410A";
static const char name_s3c2440a[] = "S3C2440A";

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= 0x32410000,
		.idmask		= 0xffffffff,
		.map_io		= s3c2410_map_io,
		.init_clocks	= s3c2410_init_clocks,
		.init_uarts	= s3c2410_init_uarts,
		.init		= s3c2410_init,
		.name		= name_s3c2410
	},
	{
		.idcode		= 0x32410002,
		.idmask		= 0xffffffff,
		.map_io		= s3c2410_map_io,
		.init_clocks	= s3c2410_init_clocks,
		.init_uarts	= s3c2410_init_uarts,
		.init		= s3c2410_init,
		.name		= name_s3c2410a
	},
	{
		.idcode		= 0x32440000,
		.idmask		= 0xffffffff,
		.map_io		= s3c244x_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2440_init,
		.name		= name_s3c2440
	},
	{
		.idcode		= 0x32440001,
		.idmask		= 0xffffffff,
		.map_io		= s3c244x_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2440_init,
		.name		= name_s3c2440a
	},
	{
		.idcode		= 0x32440aaa,
		.idmask		= 0xffffffff,
		.map_io		= s3c244x_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2442_init,
		.name		= name_s3c2442
	},
	{
		.idcode		= 0x32412001,
		.idmask		= 0xffffffff,
		.map_io		= s3c2412_map_io,
		.init_clocks	= s3c2412_init_clocks,
		.init_uarts	= s3c2412_init_uarts,
		.init		= s3c2412_init,
		.name		= name_s3c2412,
	},
	{			/* a newer version of the s3c2412 */
		.idcode		= 0x32412003,
		.idmask		= 0xffffffff,
		.map_io		= s3c2412_map_io,
		.init_clocks	= s3c2412_init_clocks,
		.init_uarts	= s3c2412_init_uarts,
		.init		= s3c2412_init,
		.name		= name_s3c2412,
	},
	{
		.idcode		= 0x32443001,
		.idmask		= 0xffffffff,
		.map_io		= s3c2443_map_io,
		.init_clocks	= s3c2443_init_clocks,
		.init_uarts	= s3c2443_init_uarts,
		.init		= s3c2443_init,
		.name		= name_s3c2443,
	},
	{
		.idcode		= 0x0,   /* S3C2400 doesn't have an idcode */
		.idmask		= 0xffffffff,
		.map_io		= s3c2400_map_io,
		.init_clocks	= s3c2400_init_clocks,
		.init_uarts	= s3c2400_init_uarts,
		.init		= s3c2400_init,
		.name		= name_s3c2400
	},
};

/* minimal IO mapping */

static struct map_desc s3c_iodesc[] __initdata = {
	IODESC_ENT(GPIO),
	IODESC_ENT(IRQ),
	IODESC_ENT(MEMCTRL),
	IODESC_ENT(UART)
};

static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode)
{
	struct cpu_table *tab;
	int count;

	tab = cpu_ids;
	for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
		if ((idcode & tab->idmask) == tab->idcode)
			return tab;
	}

	return NULL;
}

/* cpu information */

static struct cpu_table *cpu;

static unsigned long s3c24xx_read_idcode_v5(void)
{
#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
	return __raw_readl(S3C2412_GSTATUS1);
#else
	return 1UL;	/* don't look like an 2400 */
#endif
}

static unsigned long s3c24xx_read_idcode_v4(void)
{
#ifndef CONFIG_CPU_S3C2400
	return __raw_readl(S3C2410_GSTATUS1);
#else
	return 0UL;
#endif
}

/* Hook for arm_pm_restart to ensure we execute the reset code
 * with the caches enabled. It seems at least the S3C2440 has a problem
 * resetting if there is bus activity interrupted by the reset.
 */
static void s3c24xx_pm_restart(char mode)
{
	if (mode != 's') {
		unsigned long flags;

		local_irq_save(flags);
		__cpuc_flush_kern_all();
		__cpuc_flush_user_all();

		arch_reset(mode);
		local_irq_restore(flags);
	}

	/* fallback, or unhandled */
	arm_machine_restart(mode);
}

void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
{
	unsigned long idcode = 0x0;

	/* initialise the io descriptors we need for initialisation */
	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));

	if (cpu_architecture() >= CPU_ARCH_ARMv5) {
		idcode = s3c24xx_read_idcode_v5();
	} else {
		idcode = s3c24xx_read_idcode_v4();
	}

	cpu = s3c_lookup_cpu(idcode);

	if (cpu == NULL) {
		printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
		panic("Unknown S3C24XX CPU");
	}

	printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);

	if (cpu->map_io == NULL || cpu->init == NULL) {
		printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
		panic("Unsupported S3C24XX CPU");
	}

	arm_pm_restart = s3c24xx_pm_restart;

	(cpu->map_io)(mach_desc, size);
}

/* s3c24xx_init_clocks
 *
 * Initialise the clock subsystem and associated information from the
 * given master crystal value.
 *
 * xtal  = 0 -> use default PLL crystal value (normally 12MHz)
 *      != 0 -> PLL crystal value in Hz
*/

void __init s3c24xx_init_clocks(int xtal)
{
	if (xtal == 0)
		xtal = 12*1000*1000;

	if (cpu == NULL)
		panic("s3c24xx_init_clocks: no cpu setup?\n");

	if (cpu->init_clocks == NULL)
		panic("s3c24xx_init_clocks: cpu has no clock init\n");
	else
		(cpu->init_clocks)(xtal);
}

/* uart management */

static int nr_uarts __initdata = 0;

static struct s3c2410_uartcfg uart_cfgs[3];

/* s3c24xx_init_uartdevs
 *
 * copy the specified platform data and configuration into our central
 * set of devices, before the data is thrown away after the init process.
 *
 * This also fills in the array passed to the serial driver for the
 * early initialisation of the console.
*/

void __init s3c24xx_init_uartdevs(char *name,
				  struct s3c24xx_uart_resources *res,
				  struct s3c2410_uartcfg *cfg, int no)
{
	struct platform_device *platdev;
	struct s3c2410_uartcfg *cfgptr = uart_cfgs;
	struct s3c24xx_uart_resources *resp;
	int uart;

	memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);

	for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
		platdev = s3c24xx_uart_src[cfgptr->hwport];

		resp = res + cfgptr->hwport;

		s3c24xx_uart_devs[uart] = platdev;

		platdev->name = name;
		platdev->resource = resp->resources;
		platdev->num_resources = resp->nr_resources;

		platdev->dev.platform_data = cfgptr;
	}

	nr_uarts = no;
}

void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	if (cpu == NULL)
		return;

	if (cpu->init_uarts == NULL) {
		printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
	} else
		(cpu->init_uarts)(cfg, no);
}

static int __init s3c_arch_init(void)
{
	int ret;

	// do the correct init for cpu

	if (cpu == NULL)
		panic("s3c_arch_init: NULL cpu\n");

	ret = (cpu->init)();
	if (ret != 0)
		return ret;

	ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
	return ret;
}

arch_initcall(s3c_arch_init);
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/plat-s3c24xx/cpu.c
1da177e4 LT	2	*
	3	* Copyright (c) 2004-2005 Simtec Electronics
	4	* http://www.simtec.co.uk/products/SWLINUX/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C24XX CPU Support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24
	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/ioport.h>
b6d1f542	29	#include <linux/serial_core.h>
d052d1be	30	#include <linux/platform_device.h>
3c7d9c81	31	#include <linux/delay.h>
1da177e4	32
a09e64fb	33	#include <mach/hardware.h>
1da177e4 LT	34	#include <asm/irq.h>
	35	#include <asm/io.h>
	36	#include <asm/delay.h>
3c7d9c81	37	#include <asm/cacheflush.h>
1da177e4 LT	38
	39	#include <asm/mach/arch.h>
	40	#include <asm/mach/map.h>
	41
a09e64fb	42	#include <mach/system-reset.h>
3c7d9c81	43
a09e64fb	44	#include <mach/regs-gpio.h>
a2b7ba9c	45	#include <plat/regs-serial.h>
1da177e4	46
a2b7ba9c BD	47	#include <plat/cpu.h>
a2b7ba9c BD	48	#include <plat/devs.h>
a21765a7	49	#include <asm/plat-s3c24xx/clock.h>
a2b7ba9c BD	50	#include <plat/s3c2400.h>
a2b7ba9c BD	51	#include <plat/s3c2410.h>
a21765a7	52	#include <asm/plat-s3c24xx/s3c2412.h>
96ce2385	53	#include "s3c244x.h"
a2b7ba9c BD	54	#include <plat/s3c2440.h>
	55	#include <plat/s3c2442.h>
	56	#include <plat/s3c2443.h>
1da177e4 LT	57
	58	struct cpu_table {
	59	unsigned long idcode;
	60	unsigned long idmask;
	61	void (map_io)(struct map_desc mach_desc, int size);
	62	void (init_uarts)(struct s3c2410_uartcfg cfg, int no);
	63	void (*init_clocks)(int xtal);
	64	int (*init)(void);
	65	const char *name;
	66	};
	67
	68	/* table of supported CPUs */
	69
83f755f5	70	static const char name_s3c2400[] = "S3C2400";
1da177e4	71	static const char name_s3c2410[] = "S3C2410";
68d9ab39	72	static const char name_s3c2412[] = "S3C2412";
1da177e4	73	static const char name_s3c2440[] = "S3C2440";
96ce2385	74	static const char name_s3c2442[] = "S3C2442";
e4d06e39	75	static const char name_s3c2443[] = "S3C2443";
1da177e4 LT	76	static const char name_s3c2410a[] = "S3C2410A";
	77	static const char name_s3c2440a[] = "S3C2440A";
	78
	79	static struct cpu_table cpu_ids[] __initdata = {
	80	{
	81	.idcode = 0x32410000,
	82	.idmask = 0xffffffff,
	83	.map_io = s3c2410_map_io,
	84	.init_clocks = s3c2410_init_clocks,
	85	.init_uarts = s3c2410_init_uarts,
	86	.init = s3c2410_init,
	87	.name = name_s3c2410
	88	},
	89	{
	90	.idcode = 0x32410002,
	91	.idmask = 0xffffffff,
	92	.map_io = s3c2410_map_io,
	93	.init_clocks = s3c2410_init_clocks,
	94	.init_uarts = s3c2410_init_uarts,
	95	.init = s3c2410_init,
	96	.name = name_s3c2410a
	97	},
	98	{
	99	.idcode = 0x32440000,
	100	.idmask = 0xffffffff,
96ce2385 BD	101	.map_io = s3c244x_map_io,
	102	.init_clocks = s3c244x_init_clocks,
	103	.init_uarts = s3c244x_init_uarts,
1da177e4 LT	104	.init = s3c2440_init,
	105	.name = name_s3c2440
	106	},
	107	{
	108	.idcode = 0x32440001,
	109	.idmask = 0xffffffff,
96ce2385 BD	110	.map_io = s3c244x_map_io,
	111	.init_clocks = s3c244x_init_clocks,
	112	.init_uarts = s3c244x_init_uarts,
1da177e4 LT	113	.init = s3c2440_init,
1da177e4 LT	114	.name = name_s3c2440a
83f755f5	115	},
96ce2385 BD	116	{
	117	.idcode = 0x32440aaa,
	118	.idmask = 0xffffffff,
	119	.map_io = s3c244x_map_io,
	120	.init_clocks = s3c244x_init_clocks,
	121	.init_uarts = s3c244x_init_uarts,
	122	.init = s3c2442_init,
	123	.name = name_s3c2442
	124	},
68d9ab39 BD	125	{
	126	.idcode = 0x32412001,
	127	.idmask = 0xffffffff,
	128	.map_io = s3c2412_map_io,
	129	.init_clocks = s3c2412_init_clocks,
	130	.init_uarts = s3c2412_init_uarts,
	131	.init = s3c2412_init,
	132	.name = name_s3c2412,
	133	},
d9bc55fa BD	134	{ /* a newer version of the s3c2412 */
	135	.idcode = 0x32412003,
	136	.idmask = 0xffffffff,
	137	.map_io = s3c2412_map_io,
	138	.init_clocks = s3c2412_init_clocks,
	139	.init_uarts = s3c2412_init_uarts,
	140	.init = s3c2412_init,
	141	.name = name_s3c2412,
	142	},
e4d06e39 BD	143	{
	144	.idcode = 0x32443001,
	145	.idmask = 0xffffffff,
	146	.map_io = s3c2443_map_io,
	147	.init_clocks = s3c2443_init_clocks,
	148	.init_uarts = s3c2443_init_uarts,
	149	.init = s3c2443_init,
	150	.name = name_s3c2443,
	151	},
83f755f5 LCVR	152	{
	153	.idcode = 0x0, /* S3C2400 doesn't have an idcode */
	154	.idmask = 0xffffffff,
	155	.map_io = s3c2400_map_io,
	156	.init_clocks = s3c2400_init_clocks,
	157	.init_uarts = s3c2400_init_uarts,
	158	.init = s3c2400_init,
	159	.name = name_s3c2400
	160	},
1da177e4 LT	161	};
	162
	163	/* minimal IO mapping */
	164
	165	static struct map_desc s3c_iodesc[] __initdata = {
	166	IODESC_ENT(GPIO),
	167	IODESC_ENT(IRQ),
	168	IODESC_ENT(MEMCTRL),
	169	IODESC_ENT(UART)
	170	};
	171
ed414fb7	172	static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode)
1da177e4 LT	173	{
	174	struct cpu_table *tab;
	175	int count;
	176
	177	tab = cpu_ids;
	178	for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
	179	if ((idcode & tab->idmask) == tab->idcode)
	180	return tab;
	181	}
	182
	183	return NULL;
	184	}
	185
1da177e4 LT	186	/* cpu information */
	187
	188	static struct cpu_table *cpu;
	189
68d9ab39 BD	190	static unsigned long s3c24xx_read_idcode_v5(void)
	191	{
	192	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
	193	return __raw_readl(S3C2412_GSTATUS1);
	194	#else
	195	return 1UL; /* don't look like an 2400 */
	196	#endif
	197	}
	198
	199	static unsigned long s3c24xx_read_idcode_v4(void)
	200	{
	201	#ifndef CONFIG_CPU_S3C2400
	202	return __raw_readl(S3C2410_GSTATUS1);
	203	#else
	204	return 0UL;
	205	#endif
	206	}
	207
3c7d9c81 BD	208	/* Hook for arm_pm_restart to ensure we execute the reset code
	209	* with the caches enabled. It seems at least the S3C2440 has a problem
	210	* resetting if there is bus activity interrupted by the reset.
	211	*/
	212	static void s3c24xx_pm_restart(char mode)
	213	{
	214	if (mode != 's') {
	215	unsigned long flags;
	216
	217	local_irq_save(flags);
	218	__cpuc_flush_kern_all();
	219	__cpuc_flush_user_all();
	220
	221	arch_reset(mode);
	222	local_irq_restore(flags);
	223	}
	224
	225	/* fallback, or unhandled */
	226	arm_machine_restart(mode);
	227	}
	228
1da177e4 LT	229	void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
1da177e4 LT	230	{
83f755f5	231	unsigned long idcode = 0x0;
1da177e4 LT	232
	233	/* initialise the io descriptors we need for initialisation */
	234	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
	235
68d9ab39 BD	236	if (cpu_architecture() >= CPU_ARCH_ARMv5) {
	237	idcode = s3c24xx_read_idcode_v5();
	238	} else {
	239	idcode = s3c24xx_read_idcode_v4();
	240	}
83f755f5	241
1da177e4 LT	242	cpu = s3c_lookup_cpu(idcode);
	243
	244	if (cpu == NULL) {
	245	printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
	246	panic("Unknown S3C24XX CPU");
	247	}
	248
36fe6a83 BD	249	printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
36fe6a83 BD	250
1da177e4 LT	251	if (cpu->map_io == NULL \|\| cpu->init == NULL) {
	252	printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
	253	panic("Unsupported S3C24XX CPU");
	254	}
	255
3c7d9c81 BD	256	arm_pm_restart = s3c24xx_pm_restart;
3c7d9c81 BD	257
1da177e4 LT	258	(cpu->map_io)(mach_desc, size);
	259	}
	260
	261	/* s3c24xx_init_clocks
	262	*
	263	* Initialise the clock subsystem and associated information from the
	264	* given master crystal value.
	265	*
	266	* xtal = 0 -> use default PLL crystal value (normally 12MHz)
	267	* != 0 -> PLL crystal value in Hz
	268	*/
	269
	270	void __init s3c24xx_init_clocks(int xtal)
	271	{
	272	if (xtal == 0)
	273	xtal = 1210001000;
	274
	275	if (cpu == NULL)
	276	panic("s3c24xx_init_clocks: no cpu setup?\n");
	277
	278	if (cpu->init_clocks == NULL)
	279	panic("s3c24xx_init_clocks: cpu has no clock init\n");
	280	else
	281	(cpu->init_clocks)(xtal);
	282	}
	283
66a9b49a BD	284	/* uart management */
	285
	286	static int nr_uarts __initdata = 0;
	287
	288	static struct s3c2410_uartcfg uart_cfgs[3];
	289
	290	/* s3c24xx_init_uartdevs
	291	*
	292	* copy the specified platform data and configuration into our central
	293	* set of devices, before the data is thrown away after the init process.
	294	*
	295	* This also fills in the array passed to the serial driver for the
	296	* early initialisation of the console.
	297	*/
	298
	299	void __init s3c24xx_init_uartdevs(char *name,
	300	struct s3c24xx_uart_resources *res,
	301	struct s3c2410_uartcfg *cfg, int no)
	302	{
	303	struct platform_device *platdev;
	304	struct s3c2410_uartcfg *cfgptr = uart_cfgs;
	305	struct s3c24xx_uart_resources *resp;
	306	int uart;
	307
	308	memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
	309
	310	for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
	311	platdev = s3c24xx_uart_src[cfgptr->hwport];
	312
	313	resp = res + cfgptr->hwport;
	314
	315	s3c24xx_uart_devs[uart] = platdev;
	316
	317	platdev->name = name;
	318	platdev->resource = resp->resources;
	319	platdev->num_resources = resp->nr_resources;
	320
	321	platdev->dev.platform_data = cfgptr;
	322	}
	323
	324	nr_uarts = no;
	325	}
	326
1da177e4 LT	327	void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
	328	{
	329	if (cpu == NULL)
	330	return;
	331
	332	if (cpu->init_uarts == NULL) {
	333	printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
	334	} else
	335	(cpu->init_uarts)(cfg, no);
	336	}
	337
	338	static int __init s3c_arch_init(void)
	339	{
	340	int ret;
	341
	342	// do the correct init for cpu
	343
	344	if (cpu == NULL)
	345	panic("s3c_arch_init: NULL cpu\n");
	346
	347	ret = (cpu->init)();
	348	if (ret != 0)
	349	return ret;
	350
66a9b49a	351	ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
1da177e4 LT	352	return ret;
	353	}
	354
	355	arch_initcall(s3c_arch_init);