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OMAP: McBSP: Use appropriate value for startup delay
[net-next-2.6.git] / arch / arm / plat-omap / mcbsp.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
bc5d0c89 18#include <linux/platform_device.h>
5e1c5ff4
TL		 19#include <linux/wait.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
04fbf6a2 24#include <linux/delay.h>
fb78d808 25#include <linux/io.h>
5e1c5ff4 26
a09e64fb
RK		 27#include <mach/dma.h>
28#include <mach/mcbsp.h>
5e1c5ff4 29
b4b58f58
CS		 30struct omap_mcbsp **mcbsp_ptr;
31int omap_mcbsp_count;
bc5d0c89 32
b4b58f58
CS		 33void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
34{
35 if (cpu_class_is_omap1() || cpu_is_omap2420())
36 __raw_writew((u16)val, io_base + reg);
37 else
38 __raw_writel(val, io_base + reg);
39}
40
41int omap_mcbsp_read(void __iomem *io_base, u16 reg)
42{
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base + reg);
45 else
46 return __raw_readl(io_base + reg);
47}
48
49#define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51#define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
53
54#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
5e1c5ff4
TL		 56
57static void omap_mcbsp_dump_reg(u8 id)
58{
b4b58f58
CS		 59 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
60
61 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
62 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
64 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
66 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
67 OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
68 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
69 OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
70 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
71 OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
72 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
73 OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
74 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
75 OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
76 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
77 OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
78 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
79 OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
80 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
81 OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
82 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
83 OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
84 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
85 OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
86 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
88 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 89}
90
0cd61b68 91static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 92{
e8f2af17 93 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 94 u16 irqst_spcr2;
5e1c5ff4 95
d6d834b0
EN		 96 irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
97 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 98
d6d834b0
EN		 99 if (irqst_spcr2 & XSYNC_ERR) {
100 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
101 irqst_spcr2);
102 /* Writing zero to XSYNC_ERR clears the IRQ */
103 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
104 irqst_spcr2 & ~(XSYNC_ERR));
105 } else {
106 complete(&mcbsp_tx->tx_irq_completion);
107 }
fb78d808 108
5e1c5ff4
TL		 109 return IRQ_HANDLED;
110}
111
0cd61b68 112static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 113{
e8f2af17 114 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 115 u16 irqst_spcr1;
116
117 irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
118 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
119
120 if (irqst_spcr1 & RSYNC_ERR) {
121 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
122 irqst_spcr1);
123 /* Writing zero to RSYNC_ERR clears the IRQ */
124 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
125 irqst_spcr1 & ~(RSYNC_ERR));
126 } else {
127 complete(&mcbsp_rx->tx_irq_completion);
128 }
fb78d808 129
5e1c5ff4
TL		 130 return IRQ_HANDLED;
131}
132
5e1c5ff4
TL		 133static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
134{
e8f2af17 135 struct omap_mcbsp *mcbsp_dma_tx = data;
5e1c5ff4 136
bc5d0c89
EV		 137 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
138 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
5e1c5ff4
TL		 139
140 /* We can free the channels */
141 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
142 mcbsp_dma_tx->dma_tx_lch = -1;
143
144 complete(&mcbsp_dma_tx->tx_dma_completion);
145}
146
147static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
148{
e8f2af17 149 struct omap_mcbsp *mcbsp_dma_rx = data;
5e1c5ff4 150
bc5d0c89
EV		 151 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
152 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
5e1c5ff4
TL		 153
154 /* We can free the channels */
155 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
156 mcbsp_dma_rx->dma_rx_lch = -1;
157
158 complete(&mcbsp_dma_rx->rx_dma_completion);
159}
160
5e1c5ff4
TL		 161/*
162 * omap_mcbsp_config simply write a config to the
163 * appropriate McBSP.
164 * You either call this function or set the McBSP registers
165 * by yourself before calling omap_mcbsp_start().
166 */
fb78d808 167void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 168{
b4b58f58 169 struct omap_mcbsp *mcbsp;
d592dd1a 170 void __iomem *io_base;
5e1c5ff4 171
bc5d0c89
EV		 172 if (!omap_mcbsp_check_valid_id(id)) {
173 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
174 return;
175 }
b4b58f58 176 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 177
b4b58f58
CS		 178 io_base = mcbsp->io_base;
179 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
180 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 181
182 /* We write the given config */
183 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
184 OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
185 OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
186 OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
187 OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
188 OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
189 OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
190 OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
3127f8f8
TL		 194 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
197 }
5e1c5ff4 198}
fb78d808 199EXPORT_SYMBOL(omap_mcbsp_config);
5e1c5ff4 200
120db2cb
TL		 201/*
202 * We can choose between IRQ based or polled IO.
203 * This needs to be called before omap_mcbsp_request().
204 */
205int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
206{
b4b58f58
CS		 207 struct omap_mcbsp *mcbsp;
208
bc5d0c89
EV		 209 if (!omap_mcbsp_check_valid_id(id)) {
210 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
211 return -ENODEV;
212 }
b4b58f58 213 mcbsp = id_to_mcbsp_ptr(id);
120db2cb 214
b4b58f58 215 spin_lock(&mcbsp->lock);
120db2cb 216
b4b58f58
CS		 217 if (!mcbsp->free) {
218 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
219 mcbsp->id);
220 spin_unlock(&mcbsp->lock);
120db2cb
TL		 221 return -EINVAL;
222 }
223
b4b58f58 224 mcbsp->io_type = io_type;
120db2cb 225
b4b58f58 226 spin_unlock(&mcbsp->lock);
120db2cb
TL		 227
228 return 0;
229}
fb78d808 230EXPORT_SYMBOL(omap_mcbsp_set_io_type);
5e1c5ff4 231
5e1c5ff4
TL		 232int omap_mcbsp_request(unsigned int id)
233{
b4b58f58 234 struct omap_mcbsp *mcbsp;
5e1c5ff4
TL		 235 int err;
236
bc5d0c89
EV		 237 if (!omap_mcbsp_check_valid_id(id)) {
238 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
239 return -ENODEV;
120db2cb 240 }
b4b58f58 241 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 242
b4b58f58
CS		 243 spin_lock(&mcbsp->lock);
244 if (!mcbsp->free) {
245 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
246 mcbsp->id);
247 spin_unlock(&mcbsp->lock);
b820ce4e 248 return -EBUSY;
5e1c5ff4
TL		 249 }
250
b4b58f58
CS		 251 mcbsp->free = 0;
252 spin_unlock(&mcbsp->lock);
5e1c5ff4 253
b820ce4e
RK		 254 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
255 mcbsp->pdata->ops->request(id);
256
257 clk_enable(mcbsp->iclk);
258 clk_enable(mcbsp->fclk);
259
5a07055a
JN		 260 /*
261 * Make sure that transmitter, receiver and sample-rate generator are
262 * not running before activating IRQs.
263 */
264 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
265 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
266
b4b58f58 267 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
120db2cb 268 /* We need to get IRQs here */
5a07055a 269 init_completion(&mcbsp->tx_irq_completion);
b4b58f58
CS		 270 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
271 0, "McBSP", (void *)mcbsp);
120db2cb 272 if (err != 0) {
b4b58f58
CS		 273 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
274 "for McBSP%d\n", mcbsp->tx_irq,
275 mcbsp->id);
120db2cb
TL		 276 return err;
277 }
5e1c5ff4 278
5a07055a 279 init_completion(&mcbsp->rx_irq_completion);
b4b58f58
CS		 280 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
281 0, "McBSP", (void *)mcbsp);
120db2cb 282 if (err != 0) {
b4b58f58
CS		 283 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
284 "for McBSP%d\n", mcbsp->rx_irq,
285 mcbsp->id);
286 free_irq(mcbsp->tx_irq, (void *)mcbsp);
120db2cb
TL		 287 return err;
288 }
5e1c5ff4
TL		 289 }
290
5e1c5ff4 291 return 0;
5e1c5ff4 292}
fb78d808 293EXPORT_SYMBOL(omap_mcbsp_request);
5e1c5ff4
TL		 294
295void omap_mcbsp_free(unsigned int id)
296{
b4b58f58
CS		 297 struct omap_mcbsp *mcbsp;
298
bc5d0c89
EV		 299 if (!omap_mcbsp_check_valid_id(id)) {
300 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 301 return;
120db2cb 302 }
b4b58f58 303 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 304
b4b58f58
CS		 305 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
306 mcbsp->pdata->ops->free(id);
bc5d0c89 307
b820ce4e
RK		 308 clk_disable(mcbsp->fclk);
309 clk_disable(mcbsp->iclk);
310
311 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
312 /* Free IRQs */
313 free_irq(mcbsp->rx_irq, (void *)mcbsp);
314 free_irq(mcbsp->tx_irq, (void *)mcbsp);
315 }
5e1c5ff4 316
b4b58f58
CS		 317 spin_lock(&mcbsp->lock);
318 if (mcbsp->free) {
319 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
320 mcbsp->id);
321 spin_unlock(&mcbsp->lock);
5e1c5ff4
TL		 322 return;
323 }
324
b4b58f58
CS		 325 mcbsp->free = 1;
326 spin_unlock(&mcbsp->lock);
5e1c5ff4 327}
fb78d808 328EXPORT_SYMBOL(omap_mcbsp_free);
5e1c5ff4
TL		 329
330/*
c12abc01
JN		 331 * Here we start the McBSP, by enabling transmitter, receiver or both.
332 * If no transmitter or receiver is active prior calling, then sample-rate
333 * generator and frame sync are started.
5e1c5ff4 334 */
c12abc01 335void omap_mcbsp_start(unsigned int id, int tx, int rx)
5e1c5ff4 336{
b4b58f58 337 struct omap_mcbsp *mcbsp;
d592dd1a 338 void __iomem *io_base;
c12abc01 339 int idle;
5e1c5ff4
TL		 340 u16 w;
341
bc5d0c89
EV		 342 if (!omap_mcbsp_check_valid_id(id)) {
343 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 344 return;
bc5d0c89 345 }
b4b58f58
CS		 346 mcbsp = id_to_mcbsp_ptr(id);
347 io_base = mcbsp->io_base;
5e1c5ff4 348
b4b58f58
CS		 349 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
350 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
5e1c5ff4 351
c12abc01
JN		 352 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
353 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
354
355 if (idle) {
356 /* Start the sample generator */
357 w = OMAP_MCBSP_READ(io_base, SPCR2);
358 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
359 }
5e1c5ff4
TL		 360
361 /* Enable transmitter and receiver */
362 w = OMAP_MCBSP_READ(io_base, SPCR2);
c12abc01 363 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (tx & 1));
5e1c5ff4
TL		 364
365 w = OMAP_MCBSP_READ(io_base, SPCR1);
c12abc01 366 OMAP_MCBSP_WRITE(io_base, SPCR1, w | (rx & 1));
5e1c5ff4 367
44a6311c
EV		 368 /*
369 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
370 * REVISIT: 100us may give enough time for two CLKSRG, however
371 * due to some unknown PM related, clock gating etc. reason it
372 * is now at 500us.
373 */
374 udelay(500);
5e1c5ff4 375
c12abc01
JN		 376 if (idle) {
377 /* Start frame sync */
378 w = OMAP_MCBSP_READ(io_base, SPCR2);
379 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
380 }
5e1c5ff4
TL		 381
382 /* Dump McBSP Regs */
383 omap_mcbsp_dump_reg(id);
5e1c5ff4 384}
fb78d808 385EXPORT_SYMBOL(omap_mcbsp_start);
5e1c5ff4 386
c12abc01 387void omap_mcbsp_stop(unsigned int id, int tx, int rx)
5e1c5ff4 388{
b4b58f58 389 struct omap_mcbsp *mcbsp;
d592dd1a 390 void __iomem *io_base;
c12abc01 391 int idle;
5e1c5ff4
TL		 392 u16 w;
393
bc5d0c89
EV		 394 if (!omap_mcbsp_check_valid_id(id)) {
395 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 396 return;
bc5d0c89 397 }
5e1c5ff4 398
b4b58f58
CS		 399 mcbsp = id_to_mcbsp_ptr(id);
400 io_base = mcbsp->io_base;
5e1c5ff4 401
fb78d808 402 /* Reset transmitter */
5e1c5ff4 403 w = OMAP_MCBSP_READ(io_base, SPCR2);
c12abc01 404 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(tx & 1));
5e1c5ff4
TL		 405
406 /* Reset receiver */
407 w = OMAP_MCBSP_READ(io_base, SPCR1);
c12abc01 408 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(rx & 1));
5e1c5ff4 409
c12abc01
JN		 410 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
411 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
412
413 if (idle) {
414 /* Reset the sample rate generator */
415 w = OMAP_MCBSP_READ(io_base, SPCR2);
416 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
417 }
5e1c5ff4 418}
fb78d808 419EXPORT_SYMBOL(omap_mcbsp_stop);
5e1c5ff4 420
9abea08e
EN		 421void omap_mcbsp_xmit_enable(unsigned int id, u8 enable)
422{
423 struct omap_mcbsp *mcbsp;
424 void __iomem *io_base;
425 u16 w;
426
427 if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
428 return;
429
430 if (!omap_mcbsp_check_valid_id(id)) {
431 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
432 return;
433 }
434
435 mcbsp = id_to_mcbsp_ptr(id);
436 io_base = mcbsp->io_base;
437
438 w = OMAP_MCBSP_READ(io_base, XCCR);
439
440 if (enable)
441 OMAP_MCBSP_WRITE(io_base, XCCR, w & ~(XDISABLE));
442 else
443 OMAP_MCBSP_WRITE(io_base, XCCR, w | XDISABLE);
444}
445EXPORT_SYMBOL(omap_mcbsp_xmit_enable);
446
447void omap_mcbsp_recv_enable(unsigned int id, u8 enable)
448{
449 struct omap_mcbsp *mcbsp;
450 void __iomem *io_base;
451 u16 w;
452
453 if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
454 return;
455
456 if (!omap_mcbsp_check_valid_id(id)) {
457 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
458 return;
459 }
460
461 mcbsp = id_to_mcbsp_ptr(id);
462 io_base = mcbsp->io_base;
463
464 w = OMAP_MCBSP_READ(io_base, RCCR);
465
466 if (enable)
467 OMAP_MCBSP_WRITE(io_base, RCCR, w & ~(RDISABLE));
468 else
469 OMAP_MCBSP_WRITE(io_base, RCCR, w | RDISABLE);
470}
471EXPORT_SYMBOL(omap_mcbsp_recv_enable);
472
bb13b5fd
TL		 473/* polled mcbsp i/o operations */
474int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
475{
b4b58f58 476 struct omap_mcbsp *mcbsp;
d592dd1a 477 void __iomem *base;
bc5d0c89
EV		 478
479 if (!omap_mcbsp_check_valid_id(id)) {
480 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
481 return -ENODEV;
482 }
483
b4b58f58
CS		 484 mcbsp = id_to_mcbsp_ptr(id);
485 base = mcbsp->io_base;
486
bb13b5fd
TL		 487 writew(buf, base + OMAP_MCBSP_REG_DXR1);
488 /* if frame sync error - clear the error */
489 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
490 /* clear error */
491 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
492 base + OMAP_MCBSP_REG_SPCR2);
493 /* resend */
494 return -1;
495 } else {
496 /* wait for transmit confirmation */
497 int attemps = 0;
498 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
499 if (attemps++ > 1000) {
500 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
501 (~XRST),
502 base + OMAP_MCBSP_REG_SPCR2);
503 udelay(10);
504 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
505 (XRST),
506 base + OMAP_MCBSP_REG_SPCR2);
507 udelay(10);
b4b58f58
CS		 508 dev_err(mcbsp->dev, "Could not write to"
509 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 510 return -2;
511 }
512 }
513 }
fb78d808 514
bb13b5fd
TL		 515 return 0;
516}
fb78d808 517EXPORT_SYMBOL(omap_mcbsp_pollwrite);
bb13b5fd 518
fb78d808 519int omap_mcbsp_pollread(unsigned int id, u16 *buf)
bb13b5fd 520{
b4b58f58 521 struct omap_mcbsp *mcbsp;
d592dd1a 522 void __iomem *base;
bc5d0c89
EV		 523
524 if (!omap_mcbsp_check_valid_id(id)) {
525 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
526 return -ENODEV;
527 }
b4b58f58 528 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 529
b4b58f58 530 base = mcbsp->io_base;
bb13b5fd
TL		 531 /* if frame sync error - clear the error */
532 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
533 /* clear error */
534 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
535 base + OMAP_MCBSP_REG_SPCR1);
536 /* resend */
537 return -1;
538 } else {
539 /* wait for recieve confirmation */
540 int attemps = 0;
541 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
542 if (attemps++ > 1000) {
543 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
544 (~RRST),
545 base + OMAP_MCBSP_REG_SPCR1);
546 udelay(10);
547 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
548 (RRST),
549 base + OMAP_MCBSP_REG_SPCR1);
550 udelay(10);
b4b58f58
CS		 551 dev_err(mcbsp->dev, "Could not read from"
552 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 553 return -2;
554 }
555 }
556 }
557 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
fb78d808 558
bb13b5fd
TL		 559 return 0;
560}
fb78d808 561EXPORT_SYMBOL(omap_mcbsp_pollread);
bb13b5fd 562
5e1c5ff4
TL		 563/*
564 * IRQ based word transmission.
565 */
566void omap_mcbsp_xmit_word(unsigned int id, u32 word)
567{
b4b58f58 568 struct omap_mcbsp *mcbsp;
d592dd1a 569 void __iomem *io_base;
bc5d0c89 570 omap_mcbsp_word_length word_length;
5e1c5ff4 571
bc5d0c89
EV		 572 if (!omap_mcbsp_check_valid_id(id)) {
573 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 574 return;
bc5d0c89 575 }
5e1c5ff4 576
b4b58f58
CS		 577 mcbsp = id_to_mcbsp_ptr(id);
578 io_base = mcbsp->io_base;
579 word_length = mcbsp->tx_word_length;
5e1c5ff4 580
b4b58f58 581 wait_for_completion(&mcbsp->tx_irq_completion);
5e1c5ff4
TL		 582
583 if (word_length > OMAP_MCBSP_WORD_16)
584 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
585 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
586}
fb78d808 587EXPORT_SYMBOL(omap_mcbsp_xmit_word);
5e1c5ff4
TL		 588
589u32 omap_mcbsp_recv_word(unsigned int id)
590{
b4b58f58 591 struct omap_mcbsp *mcbsp;
d592dd1a 592 void __iomem *io_base;
5e1c5ff4 593 u16 word_lsb, word_msb = 0;
bc5d0c89 594 omap_mcbsp_word_length word_length;
5e1c5ff4 595
bc5d0c89
EV		 596 if (!omap_mcbsp_check_valid_id(id)) {
597 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
598 return -ENODEV;
599 }
b4b58f58 600 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 601
b4b58f58
CS		 602 word_length = mcbsp->rx_word_length;
603 io_base = mcbsp->io_base;
5e1c5ff4 604
b4b58f58 605 wait_for_completion(&mcbsp->rx_irq_completion);
5e1c5ff4
TL		 606
607 if (word_length > OMAP_MCBSP_WORD_16)
608 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
609 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
610
611 return (word_lsb | (word_msb << 16));
612}
fb78d808 613EXPORT_SYMBOL(omap_mcbsp_recv_word);
5e1c5ff4 614
120db2cb
TL		 615int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
616{
b4b58f58 617 struct omap_mcbsp *mcbsp;
d592dd1a 618 void __iomem *io_base;
bc5d0c89
EV		 619 omap_mcbsp_word_length tx_word_length;
620 omap_mcbsp_word_length rx_word_length;
120db2cb
TL		 621 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
622
bc5d0c89
EV		 623 if (!omap_mcbsp_check_valid_id(id)) {
624 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
625 return -ENODEV;
626 }
b4b58f58
CS		 627 mcbsp = id_to_mcbsp_ptr(id);
628 io_base = mcbsp->io_base;
629 tx_word_length = mcbsp->tx_word_length;
630 rx_word_length = mcbsp->rx_word_length;
bc5d0c89 631
120db2cb
TL		 632 if (tx_word_length != rx_word_length)
633 return -EINVAL;
634
635 /* First we wait for the transmitter to be ready */
636 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
637 while (!(spcr2 & XRDY)) {
638 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
639 if (attempts++ > 1000) {
640 /* We must reset the transmitter */
641 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
642 udelay(10);
643 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
644 udelay(10);
b4b58f58
CS		 645 dev_err(mcbsp->dev, "McBSP%d transmitter not "
646 "ready\n", mcbsp->id);
120db2cb
TL		 647 return -EAGAIN;
648 }
649 }
650
651 /* Now we can push the data */
652 if (tx_word_length > OMAP_MCBSP_WORD_16)
653 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
654 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
655
656 /* We wait for the receiver to be ready */
657 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
658 while (!(spcr1 & RRDY)) {
659 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
660 if (attempts++ > 1000) {
661 /* We must reset the receiver */
662 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
663 udelay(10);
664 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
665 udelay(10);
b4b58f58
CS		 666 dev_err(mcbsp->dev, "McBSP%d receiver not "
667 "ready\n", mcbsp->id);
120db2cb
TL		 668 return -EAGAIN;
669 }
670 }
671
672 /* Receiver is ready, let's read the dummy data */
673 if (rx_word_length > OMAP_MCBSP_WORD_16)
674 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
675 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
676
677 return 0;
678}
fb78d808 679EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
120db2cb 680
fb78d808 681int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
120db2cb 682{
b4b58f58 683 struct omap_mcbsp *mcbsp;
d592dd1a
RK		 684 u32 clock_word = 0;
685 void __iomem *io_base;
bc5d0c89
EV		 686 omap_mcbsp_word_length tx_word_length;
687 omap_mcbsp_word_length rx_word_length;
120db2cb
TL		 688 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
689
bc5d0c89
EV		 690 if (!omap_mcbsp_check_valid_id(id)) {
691 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
692 return -ENODEV;
693 }
694
b4b58f58
CS		 695 mcbsp = id_to_mcbsp_ptr(id);
696 io_base = mcbsp->io_base;
697
698 tx_word_length = mcbsp->tx_word_length;
699 rx_word_length = mcbsp->rx_word_length;
bc5d0c89 700
120db2cb
TL		 701 if (tx_word_length != rx_word_length)
702 return -EINVAL;
703
704 /* First we wait for the transmitter to be ready */
705 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
706 while (!(spcr2 & XRDY)) {
707 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
708 if (attempts++ > 1000) {
709 /* We must reset the transmitter */
710 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
711 udelay(10);
712 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
713 udelay(10);
b4b58f58
CS		 714 dev_err(mcbsp->dev, "McBSP%d transmitter not "
715 "ready\n", mcbsp->id);
120db2cb
TL		 716 return -EAGAIN;
717 }
718 }
719
720 /* We first need to enable the bus clock */
721 if (tx_word_length > OMAP_MCBSP_WORD_16)
722 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
723 OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
724
725 /* We wait for the receiver to be ready */
726 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
727 while (!(spcr1 & RRDY)) {
728 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
729 if (attempts++ > 1000) {
730 /* We must reset the receiver */
731 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
732 udelay(10);
733 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
734 udelay(10);
b4b58f58
CS		 735 dev_err(mcbsp->dev, "McBSP%d receiver not "
736 "ready\n", mcbsp->id);
120db2cb
TL		 737 return -EAGAIN;
738 }
739 }
740
741 /* Receiver is ready, there is something for us */
742 if (rx_word_length > OMAP_MCBSP_WORD_16)
743 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
744 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
745
746 word[0] = (word_lsb | (word_msb << 16));
747
748 return 0;
749}
fb78d808 750EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
120db2cb 751
5e1c5ff4
TL		 752/*
753 * Simple DMA based buffer rx/tx routines.
754 * Nothing fancy, just a single buffer tx/rx through DMA.
755 * The DMA resources are released once the transfer is done.
756 * For anything fancier, you should use your own customized DMA
757 * routines and callbacks.
758 */
fb78d808
EV		 759int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
760 unsigned int length)
5e1c5ff4 761{
b4b58f58 762 struct omap_mcbsp *mcbsp;
5e1c5ff4 763 int dma_tx_ch;
120db2cb
TL		 764 int src_port = 0;
765 int dest_port = 0;
766 int sync_dev = 0;
5e1c5ff4 767
bc5d0c89
EV		 768 if (!omap_mcbsp_check_valid_id(id)) {
769 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
770 return -ENODEV;
771 }
b4b58f58 772 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 773
b4b58f58 774 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
fb78d808 775 omap_mcbsp_tx_dma_callback,
b4b58f58 776 mcbsp,
fb78d808 777 &dma_tx_ch)) {
b4b58f58 778 dev_err(mcbsp->dev, " Unable to request DMA channel for "
bc5d0c89 779 "McBSP%d TX. Trying IRQ based TX\n",
b4b58f58 780 mcbsp->id);
5e1c5ff4
TL		 781 return -EAGAIN;
782 }
b4b58f58 783 mcbsp->dma_tx_lch = dma_tx_ch;
5e1c5ff4 784
b4b58f58 785 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
bc5d0c89 786 dma_tx_ch);
5e1c5ff4 787
b4b58f58 788 init_completion(&mcbsp->tx_dma_completion);
5e1c5ff4 789
120db2cb
TL		 790 if (cpu_class_is_omap1()) {
791 src_port = OMAP_DMA_PORT_TIPB;
792 dest_port = OMAP_DMA_PORT_EMIFF;
793 }
bc5d0c89 794 if (cpu_class_is_omap2())
b4b58f58 795 sync_dev = mcbsp->dma_tx_sync;
120db2cb 796
b4b58f58 797 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
5e1c5ff4
TL		 798 OMAP_DMA_DATA_TYPE_S16,
799 length >> 1, 1,
1a8bfa1e 800 OMAP_DMA_SYNC_ELEMENT,
120db2cb 801 sync_dev, 0);
5e1c5ff4 802
b4b58f58 803 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
120db2cb 804 src_port,
5e1c5ff4 805 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 806 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1a8bfa1e 807 0, 0);
5e1c5ff4 808
b4b58f58 809 omap_set_dma_src_params(mcbsp->dma_tx_lch,
120db2cb 810 dest_port,
5e1c5ff4 811 OMAP_DMA_AMODE_POST_INC,
1a8bfa1e
TL		 812 buffer,
813 0, 0);
5e1c5ff4 814
b4b58f58
CS		 815 omap_start_dma(mcbsp->dma_tx_lch);
816 wait_for_completion(&mcbsp->tx_dma_completion);
fb78d808 817
5e1c5ff4
TL		 818 return 0;
819}
fb78d808 820EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
5e1c5ff4 821
fb78d808
EV		 822int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
823 unsigned int length)
5e1c5ff4 824{
b4b58f58 825 struct omap_mcbsp *mcbsp;
5e1c5ff4 826 int dma_rx_ch;
120db2cb
TL		 827 int src_port = 0;
828 int dest_port = 0;
829 int sync_dev = 0;
5e1c5ff4 830
bc5d0c89
EV		 831 if (!omap_mcbsp_check_valid_id(id)) {
832 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
833 return -ENODEV;
834 }
b4b58f58 835 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 836
b4b58f58 837 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
fb78d808 838 omap_mcbsp_rx_dma_callback,
b4b58f58 839 mcbsp,
fb78d808 840 &dma_rx_ch)) {
b4b58f58 841 dev_err(mcbsp->dev, "Unable to request DMA channel for "
bc5d0c89 842 "McBSP%d RX. Trying IRQ based RX\n",
b4b58f58 843 mcbsp->id);
5e1c5ff4
TL		 844 return -EAGAIN;
845 }
b4b58f58 846 mcbsp->dma_rx_lch = dma_rx_ch;
5e1c5ff4 847
b4b58f58 848 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
bc5d0c89 849 dma_rx_ch);
5e1c5ff4 850
b4b58f58 851 init_completion(&mcbsp->rx_dma_completion);
5e1c5ff4 852
120db2cb
TL		 853 if (cpu_class_is_omap1()) {
854 src_port = OMAP_DMA_PORT_TIPB;
855 dest_port = OMAP_DMA_PORT_EMIFF;
856 }
bc5d0c89 857 if (cpu_class_is_omap2())
b4b58f58 858 sync_dev = mcbsp->dma_rx_sync;
120db2cb 859
b4b58f58 860 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
fb78d808
EV		 861 OMAP_DMA_DATA_TYPE_S16,
862 length >> 1, 1,
863 OMAP_DMA_SYNC_ELEMENT,
864 sync_dev, 0);
5e1c5ff4 865
b4b58f58 866 omap_set_dma_src_params(mcbsp->dma_rx_lch,
120db2cb 867 src_port,
5e1c5ff4 868 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 869 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1a8bfa1e 870 0, 0);
5e1c5ff4 871
b4b58f58 872 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
fb78d808
EV		 873 dest_port,
874 OMAP_DMA_AMODE_POST_INC,
875 buffer,
876 0, 0);
5e1c5ff4 877
b4b58f58
CS		 878 omap_start_dma(mcbsp->dma_rx_lch);
879 wait_for_completion(&mcbsp->rx_dma_completion);
fb78d808 880
5e1c5ff4
TL		 881 return 0;
882}
fb78d808 883EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
5e1c5ff4
TL		 884
885/*
886 * SPI wrapper.
887 * Since SPI setup is much simpler than the generic McBSP one,
888 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
889 * Once this is done, you can call omap_mcbsp_start().
890 */
fb78d808
EV		 891void omap_mcbsp_set_spi_mode(unsigned int id,
892 const struct omap_mcbsp_spi_cfg *spi_cfg)
5e1c5ff4 893{
b4b58f58 894 struct omap_mcbsp *mcbsp;
5e1c5ff4
TL		 895 struct omap_mcbsp_reg_cfg mcbsp_cfg;
896
bc5d0c89
EV		 897 if (!omap_mcbsp_check_valid_id(id)) {
898 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 899 return;
bc5d0c89 900 }
b4b58f58 901 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4
TL		 902
903 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
904
905 /* SPI has only one frame */
906 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
907 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
908
fb78d808 909 /* Clock stop mode */
5e1c5ff4
TL		 910 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
911 mcbsp_cfg.spcr1 |= (1 << 12);
912 else
913 mcbsp_cfg.spcr1 |= (3 << 11);
914
915 /* Set clock parities */
916 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
917 mcbsp_cfg.pcr0 |= CLKRP;
918 else
919 mcbsp_cfg.pcr0 &= ~CLKRP;
920
921 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
922 mcbsp_cfg.pcr0 &= ~CLKXP;
923 else
924 mcbsp_cfg.pcr0 |= CLKXP;
925
926 /* Set SCLKME to 0 and CLKSM to 1 */
927 mcbsp_cfg.pcr0 &= ~SCLKME;
928 mcbsp_cfg.srgr2 |= CLKSM;
929
930 /* Set FSXP */
931 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
932 mcbsp_cfg.pcr0 &= ~FSXP;
933 else
934 mcbsp_cfg.pcr0 |= FSXP;
935
936 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
937 mcbsp_cfg.pcr0 |= CLKXM;
fb78d808 938 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
5e1c5ff4
TL		 939 mcbsp_cfg.pcr0 |= FSXM;
940 mcbsp_cfg.srgr2 &= ~FSGM;
941 mcbsp_cfg.xcr2 |= XDATDLY(1);
942 mcbsp_cfg.rcr2 |= RDATDLY(1);
fb78d808 943 } else {
5e1c5ff4
TL		 944 mcbsp_cfg.pcr0 &= ~CLKXM;
945 mcbsp_cfg.srgr1 |= CLKGDV(1);
946 mcbsp_cfg.pcr0 &= ~FSXM;
947 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
948 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
949 }
950
951 mcbsp_cfg.xcr2 &= ~XPHASE;
952 mcbsp_cfg.rcr2 &= ~RPHASE;
953
954 omap_mcbsp_config(id, &mcbsp_cfg);
955}
fb78d808 956EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
5e1c5ff4
TL		 957
958/*
959 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
960 * 730 has only 2 McBSP, and both of them are MPU peripherals.
961 */
25cef225 962static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
bc5d0c89
EV		 963{
964 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
b4b58f58 965 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 966 int id = pdev->id - 1;
967 int ret = 0;
5e1c5ff4 968
bc5d0c89
EV		 969 if (!pdata) {
970 dev_err(&pdev->dev, "McBSP device initialized without"
971 "platform data\n");
972 ret = -EINVAL;
973 goto exit;
974 }
975
976 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
977
b4b58f58 978 if (id >= omap_mcbsp_count) {
bc5d0c89
EV		 979 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
980 ret = -EINVAL;
981 goto exit;
982 }
983
b4b58f58
CS		 984 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
985 if (!mcbsp) {
986 ret = -ENOMEM;
987 goto exit;
988 }
b4b58f58
CS		 989
990 spin_lock_init(&mcbsp->lock);
991 mcbsp->id = id + 1;
992 mcbsp->free = 1;
993 mcbsp->dma_tx_lch = -1;
994 mcbsp->dma_rx_lch = -1;
bc5d0c89 995
b4b58f58
CS		 996 mcbsp->phys_base = pdata->phys_base;
997 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
998 if (!mcbsp->io_base) {
d592dd1a
RK		 999 ret = -ENOMEM;
1000 goto err_ioremap;
1001 }
1002
bc5d0c89 1003 /* Default I/O is IRQ based */
b4b58f58
CS		 1004 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1005 mcbsp->tx_irq = pdata->tx_irq;
1006 mcbsp->rx_irq = pdata->rx_irq;
1007 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1008 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
bc5d0c89 1009
b820ce4e
RK		 1010 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1011 if (IS_ERR(mcbsp->iclk)) {
1012 ret = PTR_ERR(mcbsp->iclk);
1013 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1014 goto err_iclk;
1015 }
06151158 1016
b820ce4e
RK		 1017 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1018 if (IS_ERR(mcbsp->fclk)) {
1019 ret = PTR_ERR(mcbsp->fclk);
1020 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1021 goto err_fclk;
bc5d0c89
EV		 1022 }
1023
b4b58f58
CS		 1024 mcbsp->pdata = pdata;
1025 mcbsp->dev = &pdev->dev;
b820ce4e 1026 mcbsp_ptr[id] = mcbsp;
b4b58f58 1027 platform_set_drvdata(pdev, mcbsp);
d592dd1a 1028 return 0;
bc5d0c89 1029
b820ce4e
RK		 1030err_fclk:
1031 clk_put(mcbsp->iclk);
1032err_iclk:
b4b58f58 1033 iounmap(mcbsp->io_base);
d592dd1a 1034err_ioremap:
b820ce4e 1035 kfree(mcbsp);
bc5d0c89
EV		 1036exit:
1037 return ret;
1038}
120db2cb 1039
25cef225 1040static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
5e1c5ff4 1041{
bc5d0c89 1042 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
5e1c5ff4 1043
bc5d0c89
EV		 1044 platform_set_drvdata(pdev, NULL);
1045 if (mcbsp) {
5e1c5ff4 1046
bc5d0c89
EV		 1047 if (mcbsp->pdata && mcbsp->pdata->ops &&
1048 mcbsp->pdata->ops->free)
1049 mcbsp->pdata->ops->free(mcbsp->id);
5e1c5ff4 1050
b820ce4e
RK		 1051 clk_disable(mcbsp->fclk);
1052 clk_disable(mcbsp->iclk);
1053 clk_put(mcbsp->fclk);
1054 clk_put(mcbsp->iclk);
bc5d0c89 1055
d592dd1a
RK		 1056 iounmap(mcbsp->io_base);
1057
b820ce4e
RK		 1058 mcbsp->fclk = NULL;
1059 mcbsp->iclk = NULL;
bc5d0c89
EV		 1060 mcbsp->free = 0;
1061 mcbsp->dev = NULL;
5e1c5ff4
TL		 1062 }
1063
1064 return 0;
1065}
1066
bc5d0c89
EV		 1067static struct platform_driver omap_mcbsp_driver = {
1068 .probe = omap_mcbsp_probe,
25cef225 1069 .remove = __devexit_p(omap_mcbsp_remove),
bc5d0c89
EV		 1070 .driver = {
1071 .name = "omap-mcbsp",
1072 },
1073};
1074
1075int __init omap_mcbsp_init(void)
1076{
1077 /* Register the McBSP driver */
1078 return platform_driver_register(&omap_mcbsp_driver);
1079}
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