[net-next-2.6.git] / arch / arm / plat-omap / include / plat / clock.h

/*
 * OMAP clock: data structure definitions, function prototypes, shared macros
 *
 * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_OMAP_CLOCK_H
#define __ARCH_ARM_OMAP_CLOCK_H

#include <linux/list.h>

struct module;
struct clk;
struct clockdomain;

struct clkops {
	int			(*enable)(struct clk *);
	void			(*disable)(struct clk *);
	void			(*find_idlest)(struct clk *, void __iomem **,
					       u8 *, u8 *);
	void			(*find_companion)(struct clk *, void __iomem **,
						  u8 *);
};

#ifdef CONFIG_ARCH_OMAP2PLUS

struct clksel_rate {
	u32			val;
	u8			div;
	u8			flags;
};

struct clksel {
	struct clk		 *parent;
	const struct clksel_rate *rates;
};

/**
 * struct dpll_data - DPLL registers and integration data
 * @mult_div1_reg: register containing the DPLL M and N bitfields
 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
 * @clk_bypass: struct clk pointer to the clock's bypass clock input
 * @clk_ref: struct clk pointer to the clock's reference clock input
 * @control_reg: register containing the DPLL mode bitfield
 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
 * @rate_tolerance: maximum variance allowed from target rate (in Hz)
 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
 * @min_divider: minimum valid non-bypass divider value (actual)
 * @max_divider: maximum valid non-bypass divider value (actual)
 * @modes: possible values of @enable_mask
 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
 * @idlest_reg: register containing the DPLL idle status bitfield
 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
 * @flags: DPLL type/features (see below)
 *
 * Possible values for @flags:
 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
 * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs)

 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
 *
 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
 * correct to only have one @clk_bypass pointer.
 *
 * XXX @rate_tolerance should probably be deprecated - currently there
 * don't seem to be any usecases for DPLL rounding that is not exact.
 *
 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
 * @last_rounded_n) should be separated from the runtime-fixed fields
 * and placed into a differenct structure, so that the runtime-fixed data
 * can be placed into read-only space.
 */
struct dpll_data {
	void __iomem		*mult_div1_reg;
	u32			mult_mask;
	u32			div1_mask;
	struct clk		*clk_bypass;
	struct clk		*clk_ref;
	void __iomem		*control_reg;
	u32			enable_mask;
	unsigned int		rate_tolerance;
	unsigned long		last_rounded_rate;
	u16			last_rounded_m;
	u16			max_multiplier;
	u8			last_rounded_n;
	u8			min_divider;
	u8			max_divider;
	u8			modes;
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
	void __iomem		*autoidle_reg;
	void __iomem		*idlest_reg;
	u32			autoidle_mask;
	u32			freqsel_mask;
	u32			idlest_mask;
	u8			auto_recal_bit;
	u8			recal_en_bit;
	u8			recal_st_bit;
	u8			flags;
#  endif
};

#endif

struct clk {
	struct list_head	node;
	const struct clkops	*ops;
	const char		*name;
	struct clk		*parent;
	struct list_head	children;
	struct list_head	sibling;	/* node for children */
	unsigned long		rate;
	void __iomem		*enable_reg;
	unsigned long		(*recalc)(struct clk *);
	int			(*set_rate)(struct clk *, unsigned long);
	long			(*round_rate)(struct clk *, unsigned long);
	void			(*init)(struct clk *);
	__u8			enable_bit;
	__s8			usecount;
	u8			fixed_div;
	u8			flags;
#ifdef CONFIG_ARCH_OMAP2PLUS
	void __iomem		*clksel_reg;
	u32			clksel_mask;
	const struct clksel	*clksel;
	struct dpll_data	*dpll_data;
	const char		*clkdm_name;
	struct clockdomain	*clkdm;
#else
	__u8			rate_offset;
	__u8			src_offset;
#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
	struct dentry		*dent;	/* For visible tree hierarchy */
#endif
};

struct cpufreq_frequency_table;

struct clk_functions {
	int		(*clk_enable)(struct clk *clk);
	void		(*clk_disable)(struct clk *clk);
	long		(*clk_round_rate)(struct clk *clk, unsigned long rate);
	int		(*clk_set_rate)(struct clk *clk, unsigned long rate);
	int		(*clk_set_parent)(struct clk *clk, struct clk *parent);
	void		(*clk_allow_idle)(struct clk *clk);
	void		(*clk_deny_idle)(struct clk *clk);
	void		(*clk_disable_unused)(struct clk *clk);
#ifdef CONFIG_CPU_FREQ
	void		(*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
	void		(*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
#endif
};

extern int mpurate;

extern int clk_init(struct clk_functions *custom_clocks);
extern void clk_preinit(struct clk *clk);
extern int clk_register(struct clk *clk);
extern void clk_reparent(struct clk *child, struct clk *parent);
extern void clk_unregister(struct clk *clk);
extern void propagate_rate(struct clk *clk);
extern void recalculate_root_clocks(void);
extern unsigned long followparent_recalc(struct clk *clk);
extern void clk_enable_init_clocks(void);
unsigned long omap_fixed_divisor_recalc(struct clk *clk);
#ifdef CONFIG_CPU_FREQ
extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
#endif
extern struct clk *omap_clk_get_by_name(const char *name);

extern const struct clkops clkops_null;

extern struct clk dummy_ck;

/* Clock flags */
#define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
#define CLOCK_IDLE_CONTROL	(1 << 1)
#define CLOCK_NO_IDLE_PARENT	(1 << 2)
#define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
#define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */

/* Clksel_rate flags */
#define DEFAULT_RATE		(1 << 0)
#define RATE_IN_242X		(1 << 1)
#define RATE_IN_243X		(1 << 2)
#define RATE_IN_343X		(1 << 3)	/* rates common to all 343X */
#define RATE_IN_3430ES2		(1 << 4)	/* 3430ES2 rates only */
#define RATE_IN_36XX		(1 << 5)
#define RATE_IN_4430		(1 << 6)

#define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)


#endif
Commit	Line	Data
9ad5897c	1	/*
93340a22	2	* OMAP clock: data structure definitions, function prototypes, shared macros
9ad5897c	3	*
93340a22 PW	4	* Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
	5	* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
	6	* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
9ad5897c TL	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __ARCH_ARM_OMAP_CLOCK_H
	14	#define __ARCH_ARM_OMAP_CLOCK_H
	15
d8a94458 PW	16	#include <linux/list.h>
d8a94458 PW	17
9ad5897c	18	struct module;
6b8858a9	19	struct clk;
d1b03f61	20	struct clockdomain;
6b8858a9	21
548d8495 RK	22	struct clkops {
	23	int (enable)(struct clk );
	24	void (disable)(struct clk );
419cc97d RL	25	void (find_idlest)(struct clk , void __iomem **,
	26	u8 , u8 );
	27	void (find_companion)(struct clk , void __iomem **,
	28	u8 *);
548d8495 RK	29	};
548d8495 RK	30
140455fa	31	#ifdef CONFIG_ARCH_OMAP2PLUS
6b8858a9 PW	32
6b8858a9 PW	33	struct clksel_rate {
6b8858a9	34	u32 val;
ebb8dca2	35	u8 div;
6b8858a9 PW	36	u8 flags;
	37	};
	38
	39	struct clksel {
	40	struct clk *parent;
	41	const struct clksel_rate *rates;
	42	};
	43
93340a22 PW	44	/**
	45	* struct dpll_data - DPLL registers and integration data
	46	* @mult_div1_reg: register containing the DPLL M and N bitfields
	47	* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
	48	* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
	49	* @clk_bypass: struct clk pointer to the clock's bypass clock input
	50	* @clk_ref: struct clk pointer to the clock's reference clock input
	51	* @control_reg: register containing the DPLL mode bitfield
	52	* @enable_mask: mask of the DPLL mode bitfield in @control_reg
	53	* @rate_tolerance: maximum variance allowed from target rate (in Hz)
	54	* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
	55	* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
	56	* @max_multiplier: maximum valid non-bypass multiplier value (actual)
	57	* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
	58	* @min_divider: minimum valid non-bypass divider value (actual)
	59	* @max_divider: maximum valid non-bypass divider value (actual)
	60	* @modes: possible values of @enable_mask
	61	* @autoidle_reg: register containing the DPLL autoidle mode bitfield
	62	* @idlest_reg: register containing the DPLL idle status bitfield
	63	* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
	64	* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
	65	* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
	66	* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
	67	* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
	68	* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
	69	* @flags: DPLL type/features (see below)
	70	*
	71	* Possible values for @flags:
	72	* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
	73	* NO_DCO_SEL: don't program DCO (only for some J-type DPLLs)
	74
	75	* @freqsel_mask is only used on the OMAP34xx family and AM35xx.
	76	*
	77	* XXX Some DPLLs have multiple bypass inputs, so it's not technically
	78	* correct to only have one @clk_bypass pointer.
	79	*
	80	* XXX @rate_tolerance should probably be deprecated - currently there
	81	* don't seem to be any usecases for DPLL rounding that is not exact.
	82	*
	83	* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
	84	* @last_rounded_n) should be separated from the runtime-fixed fields
	85	* and placed into a differenct structure, so that the runtime-fixed data
	86	* can be placed into read-only space.
358965d7	87	*/
6b8858a9 PW	88	struct dpll_data {
	89	void __iomem *mult_div1_reg;
	90	u32 mult_mask;
	91	u32 div1_mask;
c0bf3132 RK	92	struct clk *clk_bypass;
	93	struct clk *clk_ref;
	94	void __iomem *control_reg;
	95	u32 enable_mask;
ebb8dca2 RK	96	unsigned int rate_tolerance;
ebb8dca2 RK	97	unsigned long last_rounded_rate;
88b8ba90	98	u16 last_rounded_m;
93340a22	99	u16 max_multiplier;
88b8ba90	100	u8 last_rounded_n;
95f538ac	101	u8 min_divider;
88b8ba90	102	u8 max_divider;
542313cc	103	u8 modes;
93340a22	104	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP4)
ebb8dca2 RK	105	void __iomem *autoidle_reg;
ebb8dca2 RK	106	void __iomem *idlest_reg;
ebb8dca2	107	u32 autoidle_mask;
16c90f02	108	u32 freqsel_mask;
c1bd7aaf	109	u32 idlest_mask;
b045d080 PW	110	u8 auto_recal_bit;
	111	u8 recal_en_bit;
	112	u8 recal_st_bit;
358965d7	113	u8 flags;
b045d080	114	# endif
6b8858a9 PW	115	};
	116
	117	#endif
9ad5897c TL	118
	119	struct clk {
	120	struct list_head node;
548d8495	121	const struct clkops *ops;
9ad5897c TL	122	const char *name;
9ad5897c TL	123	struct clk *parent;
3f0a820c RK	124	struct list_head children;
3f0a820c RK	125	struct list_head sibling; /* node for children */
9ad5897c	126	unsigned long rate;
9ad5897c	127	void __iomem *enable_reg;
8b9dbc16	128	unsigned long (recalc)(struct clk );
9ad5897c TL	129	int (set_rate)(struct clk , unsigned long);
	130	long (round_rate)(struct clk , unsigned long);
	131	void (init)(struct clk );
ebb8dca2 RK	132	__u8 enable_bit;
ebb8dca2 RK	133	__s8 usecount;
e9b98f60	134	u8 fixed_div;
f71eddb1	135	u8 flags;
140455fa	136	#ifdef CONFIG_ARCH_OMAP2PLUS
6b8858a9 PW	137	void __iomem *clksel_reg;
	138	u32 clksel_mask;
	139	const struct clksel *clksel;
88b8ba90	140	struct dpll_data *dpll_data;
d1b03f61 PW	141	const char *clkdm_name;
d1b03f61 PW	142	struct clockdomain *clkdm;
6b8858a9 PW	143	#else
	144	__u8 rate_offset;
	145	__u8 src_offset;
	146	#endif
137b3ee2 HD	147	#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
	148	struct dentry dent; / For visible tree hierarchy */
	149	#endif
9ad5897c TL	150	};
9ad5897c TL	151
b851cb28 RK	152	struct cpufreq_frequency_table;
b851cb28 RK	153
9ad5897c TL	154	struct clk_functions {
	155	int (clk_enable)(struct clk clk);
	156	void (clk_disable)(struct clk clk);
9ad5897c TL	157	long (clk_round_rate)(struct clk clk, unsigned long rate);
	158	int (clk_set_rate)(struct clk clk, unsigned long rate);
	159	int (clk_set_parent)(struct clk clk, struct clk *parent);
9ad5897c TL	160	void (clk_allow_idle)(struct clk clk);
9ad5897c TL	161	void (clk_deny_idle)(struct clk clk);
90afd5cb	162	void (clk_disable_unused)(struct clk clk);
b851cb28 RK	163	#ifdef CONFIG_CPU_FREQ
b851cb28 RK	164	void (clk_init_cpufreq_table)(struct cpufreq_frequency_table *);
4e37c10d	165	void (clk_exit_cpufreq_table)(struct cpufreq_frequency_table *);
b851cb28	166	#endif
9ad5897c TL	167	};
9ad5897c TL	168
d3730192	169	extern int mpurate;
9ad5897c	170
fecb494b	171	extern int clk_init(struct clk_functions *custom_clocks);
79716870	172	extern void clk_preinit(struct clk *clk);
9ad5897c	173	extern int clk_register(struct clk *clk);
3f0a820c	174	extern void clk_reparent(struct clk child, struct clk parent);
9ad5897c TL	175	extern void clk_unregister(struct clk *clk);
9ad5897c TL	176	extern void propagate_rate(struct clk *clk);
6b8858a9	177	extern void recalculate_root_clocks(void);
8b9dbc16	178	extern unsigned long followparent_recalc(struct clk *clk);
6b8858a9	179	extern void clk_enable_init_clocks(void);
e9b98f60	180	unsigned long omap_fixed_divisor_recalc(struct clk *clk);
aeec2990 KH	181	#ifdef CONFIG_CPU_FREQ
aeec2990 KH	182	extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
4e37c10d	183	extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
aeec2990	184	#endif
74be8427	185	extern struct clk omap_clk_get_by_name(const char name);
9ad5897c	186
897dcded RK	187	extern const struct clkops clkops_null;
897dcded RK	188
7c43d547 SS	189	extern struct clk dummy_ck;
7c43d547 SS	190
9ad5897c	191	/* Clock flags */
51c19541 PW	192	#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
	193	#define CLOCK_IDLE_CONTROL (1 << 1)
	194	#define CLOCK_NO_IDLE_PARENT (1 << 2)
	195	#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
	196	#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
6b8858a9 PW	197
	198	/* Clksel_rate flags */
	199	#define DEFAULT_RATE (1 << 0)
	200	#define RATE_IN_242X (1 << 1)
	201	#define RATE_IN_243X (1 << 2)
	202	#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
93340a22	203	#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
678bc9a2 VB	204	#define RATE_IN_36XX (1 << 5)
678bc9a2 VB	205	#define RATE_IN_4430 (1 << 6)
6b8858a9 PW	206
	207	#define RATE_IN_24XX (RATE_IN_242X \| RATE_IN_243X)
	208
9ad5897c TL	209
9ad5897c TL	210	#endif