[net-next-2.6.git] / arch / arm / plat-omap / i2c.c

/*
 * linux/arch/arm/plat-omap/i2c.c
 *
 * Helper module for board specific I2C bus registration
 *
 * Copyright (C) 2007 Nokia Corporation.
 *
 * Contact: Jarkko Nikula <jhnikula@gmail.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c-omap.h>

#include <mach/irqs.h>
#include <plat/mux.h>
#include <plat/i2c.h>
#include <plat/omap-pm.h>

#define OMAP_I2C_SIZE		0x3f
#define OMAP1_I2C_BASE		0xfffb3800
#define OMAP2_I2C_BASE1		0x48070000
#define OMAP2_I2C_BASE2		0x48072000
#define OMAP2_I2C_BASE3		0x48060000

static const char name[] = "i2c_omap";

#define I2C_RESOURCE_BUILDER(base, irq)			\
	{						\
		.start	= (base),			\
		.end	= (base) + OMAP_I2C_SIZE,	\
		.flags	= IORESOURCE_MEM,		\
	},						\
	{						\
		.start	= (irq),			\
		.flags	= IORESOURCE_IRQ,		\
	},

static struct resource i2c_resources[][2] = {
	{ I2C_RESOURCE_BUILDER(0, 0) },
#if	defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) },
#endif
#if	defined(CONFIG_ARCH_OMAP3)
	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) },
#endif
};

#define I2C_DEV_BUILDER(bus_id, res, data)		\
	{						\
		.id	= (bus_id),			\
		.name	= name,				\
		.num_resources	= ARRAY_SIZE(res),	\
		.resource	= (res),		\
		.dev		= {			\
			.platform_data	= (data),	\
		},					\
	}

static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
static struct platform_device omap_i2c_devices[] = {
	I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
#if	defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
	I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
#endif
#if	defined(CONFIG_ARCH_OMAP3)
	I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
#endif
};

#define OMAP_I2C_CMDLINE_SETUP	(BIT(31))

static int __init omap_i2c_nr_ports(void)
{
	int ports = 0;

	if (cpu_class_is_omap1())
		ports = 1;
	else if (cpu_is_omap24xx())
		ports = 2;
	else if (cpu_is_omap34xx())
		ports = 3;

	return ports;
}

/* Shared between omap2 and 3 */
static resource_size_t omap2_i2c_irq[3] __initdata = {
	INT_24XX_I2C1_IRQ,
	INT_24XX_I2C2_IRQ,
	INT_34XX_I2C3_IRQ,
};

static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
{
	struct omap_i2c_bus_platform_data *pd;
	struct resource *res;

	pd = pdev->dev.platform_data;
	res = pdev->resource;
	res[0].start = OMAP1_I2C_BASE;
	res[0].end = res[0].start + OMAP_I2C_SIZE;
	res[1].start = INT_I2C;
	omap1_i2c_mux_pins(bus_id);

	return platform_device_register(pdev);
}

static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
{
	struct resource *res;
	resource_size_t *irq;

	res = pdev->resource;

	irq = omap2_i2c_irq;

	if (bus_id == 1) {
		res[0].start = OMAP2_I2C_BASE1;
		res[0].end = res[0].start + OMAP_I2C_SIZE;
	}

	res[1].start = irq[bus_id - 1];
	omap2_i2c_mux_pins(bus_id);

	/*
	 * When waiting for completion of a i2c transfer, we need to
	 * set a wake up latency constraint for the MPU. This is to
	 * ensure quick enough wakeup from idle, when transfer
	 * completes.
	 */
	if (cpu_is_omap34xx()) {
		struct omap_i2c_bus_platform_data *pd;

		pd = pdev->dev.platform_data;
		pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat;
	}

	return platform_device_register(pdev);
}

static int __init omap_i2c_add_bus(int bus_id)
{
	struct platform_device *pdev;

	pdev = &omap_i2c_devices[bus_id - 1];

	if (cpu_class_is_omap1())
		return omap1_i2c_add_bus(pdev, bus_id);
	else
		return omap2_i2c_add_bus(pdev, bus_id);
}

/**
 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
 * @str: String of options
 *
 * This function allow to override the default I2C bus speed for given I2C
 * bus with a command line option.
 *
 * Format: i2c_bus=bus_id,clkrate (in kHz)
 *
 * Returns 1 on success, 0 otherwise.
 */
static int __init omap_i2c_bus_setup(char *str)
{
	int ports;
	int ints[3];

	ports = omap_i2c_nr_ports();
	get_options(str, 3, ints);
	if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports)
		return 0;
	i2c_pdata[ints[1] - 1].clkrate = ints[2];
	i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;

	return 1;
}
__setup("i2c_bus=", omap_i2c_bus_setup);

/*
 * Register busses defined in command line but that are not registered with
 * omap_register_i2c_bus from board initialization code.
 */
static int __init omap_register_i2c_bus_cmdline(void)
{
	int i, err = 0;

	for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
		if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
			i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
			err = omap_i2c_add_bus(i + 1);
			if (err)
				goto out;
		}

out:
	return err;
}
subsys_initcall(omap_register_i2c_bus_cmdline);

/**
 * omap_register_i2c_bus - register I2C bus with device descriptors
 * @bus_id: bus id counting from number 1
 * @clkrate: clock rate of the bus in kHz
 * @info: pointer into I2C device descriptor table or NULL
 * @len: number of descriptors in the table
 *
 * Returns 0 on success or an error code.
 */
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
			  struct i2c_board_info const *info,
			  unsigned len)
{
	int err;

	BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports());

	if (info) {
		err = i2c_register_board_info(bus_id, info, len);
		if (err)
			return err;
	}

	if (!i2c_pdata[bus_id - 1].clkrate)
		i2c_pdata[bus_id - 1].clkrate = clkrate;

	i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;

	return omap_i2c_add_bus(bus_id);
}
Commit	Line	Data
85d05fb3 JN	1	/*
	2	* linux/arch/arm/plat-omap/i2c.c
	3	*
	4	* Helper module for board specific I2C bus registration
	5	*
	6	* Copyright (C) 2007 Nokia Corporation.
	7	*
ddf25dfe	8	* Contact: Jarkko Nikula <jhnikula@gmail.com>
85d05fb3 JN	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License
	12	* version 2 as published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	22	* 02110-1301 USA
	23	*
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/i2c.h>
20c9d2c4 KJ	29	#include <linux/i2c-omap.h>
20c9d2c4 KJ	30
80b02c17	31	#include <mach/irqs.h>
ce491cf8	32	#include <plat/mux.h>
9833eff3	33	#include <plat/i2c.h>
20c9d2c4	34	#include <plat/omap-pm.h>
85d05fb3 JN	35
	36	#define OMAP_I2C_SIZE 0x3f
	37	#define OMAP1_I2C_BASE 0xfffb3800
	38	#define OMAP2_I2C_BASE1 0x48070000
	39	#define OMAP2_I2C_BASE2 0x48072000
	40	#define OMAP2_I2C_BASE3 0x48060000
	41
	42	static const char name[] = "i2c_omap";
	43
	44	#define I2C_RESOURCE_BUILDER(base, irq) \
	45	{ \
	46	.start = (base), \
	47	.end = (base) + OMAP_I2C_SIZE, \
	48	.flags = IORESOURCE_MEM, \
	49	}, \
	50	{ \
	51	.start = (irq), \
	52	.flags = IORESOURCE_IRQ, \
	53	},
	54
	55	static struct resource i2c_resources[][2] = {
	56	{ I2C_RESOURCE_BUILDER(0, 0) },
a8eb7ca0	57	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
85d05fb3 JN	58	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) },
85d05fb3 JN	59	#endif
a8eb7ca0	60	#if defined(CONFIG_ARCH_OMAP3)
85d05fb3 JN	61	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) },
	62	#endif
	63	};
	64
	65	#define I2C_DEV_BUILDER(bus_id, res, data) \
	66	{ \
	67	.id = (bus_id), \
	68	.name = name, \
	69	.num_resources = ARRAY_SIZE(res), \
	70	.resource = (res), \
	71	.dev = { \
	72	.platform_data = (data), \
	73	}, \
	74	}
	75
20c9d2c4	76	static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
85d05fb3	77	static struct platform_device omap_i2c_devices[] = {
20c9d2c4	78	I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
a8eb7ca0	79	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
20c9d2c4	80	I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
85d05fb3	81	#endif
a8eb7ca0	82	#if defined(CONFIG_ARCH_OMAP3)
20c9d2c4	83	I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
85d05fb3 JN	84	#endif
	85	};
	86
7954763b JN	87	#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
7954763b JN	88
3a853fb9 JN	89	static int __init omap_i2c_nr_ports(void)
	90	{
	91	int ports = 0;
	92
	93	if (cpu_class_is_omap1())
	94	ports = 1;
	95	else if (cpu_is_omap24xx())
	96	ports = 2;
	97	else if (cpu_is_omap34xx())
	98	ports = 3;
	99
	100	return ports;
	101	}
	102
b32dd41e TL	103	/* Shared between omap2 and 3 */
	104	static resource_size_t omap2_i2c_irq[3] __initdata = {
	105	INT_24XX_I2C1_IRQ,
	106	INT_24XX_I2C2_IRQ,
	107	INT_34XX_I2C3_IRQ,
	108	};
	109
	110	static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
7954763b	111	{
20c9d2c4	112	struct omap_i2c_bus_platform_data *pd;
7954763b	113	struct resource *res;
7954763b	114
20c9d2c4	115	pd = pdev->dev.platform_data;
b32dd41e TL	116	res = pdev->resource;
	117	res[0].start = OMAP1_I2C_BASE;
	118	res[0].end = res[0].start + OMAP_I2C_SIZE;
	119	res[1].start = INT_I2C;
	120	omap1_i2c_mux_pins(bus_id);
	121
	122	return platform_device_register(pdev);
	123	}
	124
	125	static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
	126	{
	127	struct resource *res;
	128	resource_size_t *irq;
	129
	130	res = pdev->resource;
	131
	132	irq = omap2_i2c_irq;
	133
7954763b	134	if (bus_id == 1) {
b32dd41e TL	135	res[0].start = OMAP2_I2C_BASE1;
b32dd41e TL	136	res[0].end = res[0].start + OMAP_I2C_SIZE;
7954763b JN	137	}
7954763b JN	138
b32dd41e TL	139	res[1].start = irq[bus_id - 1];
b32dd41e TL	140	omap2_i2c_mux_pins(bus_id);
9833eff3	141
20c9d2c4 KJ	142	/*
	143	* When waiting for completion of a i2c transfer, we need to
	144	* set a wake up latency constraint for the MPU. This is to
	145	* ensure quick enough wakeup from idle, when transfer
	146	* completes.
	147	*/
b32dd41e TL	148	if (cpu_is_omap34xx()) {
	149	struct omap_i2c_bus_platform_data *pd;
	150
	151	pd = pdev->dev.platform_data;
20c9d2c4	152	pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat;
b32dd41e	153	}
20c9d2c4	154
7954763b JN	155	return platform_device_register(pdev);
	156	}
	157
b32dd41e TL	158	static int __init omap_i2c_add_bus(int bus_id)
	159	{
	160	struct platform_device *pdev;
	161
	162	pdev = &omap_i2c_devices[bus_id - 1];
	163
	164	if (cpu_class_is_omap1())
	165	return omap1_i2c_add_bus(pdev, bus_id);
	166	else
	167	return omap2_i2c_add_bus(pdev, bus_id);
	168	}
	169
3a853fb9 JN	170	/**
	171	* omap_i2c_bus_setup - Process command line options for the I2C bus speed
	172	* @str: String of options
	173	*
	174	* This function allow to override the default I2C bus speed for given I2C
	175	* bus with a command line option.
	176	*
	177	* Format: i2c_bus=bus_id,clkrate (in kHz)
	178	*
	179	* Returns 1 on success, 0 otherwise.
	180	*/
	181	static int __init omap_i2c_bus_setup(char *str)
	182	{
	183	int ports;
	184	int ints[3];
	185
	186	ports = omap_i2c_nr_ports();
	187	get_options(str, 3, ints);
	188	if (ints[0] < 2 \|\| ints[1] < 1 \|\| ints[1] > ports)
	189	return 0;
20c9d2c4 KJ	190	i2c_pdata[ints[1] - 1].clkrate = ints[2];
20c9d2c4 KJ	191	i2c_pdata[ints[1] - 1].clkrate \|= OMAP_I2C_CMDLINE_SETUP;
3a853fb9 JN	192
	193	return 1;
	194	}
	195	__setup("i2c_bus=", omap_i2c_bus_setup);
	196
7954763b JN	197	/*
	198	* Register busses defined in command line but that are not registered with
	199	* omap_register_i2c_bus from board initialization code.
	200	*/
	201	static int __init omap_register_i2c_bus_cmdline(void)
	202	{
	203	int i, err = 0;
	204
20c9d2c4 KJ	205	for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
	206	if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
	207	i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
7954763b JN	208	err = omap_i2c_add_bus(i + 1);
	209	if (err)
	210	goto out;
	211	}
	212
	213	out:
	214	return err;
	215	}
	216	subsys_initcall(omap_register_i2c_bus_cmdline);
	217
d4c58bf4	218	/**
9833eff3	219	* omap_register_i2c_bus - register I2C bus with device descriptors
d4c58bf4 JN	220	* @bus_id: bus id counting from number 1
	221	* @clkrate: clock rate of the bus in kHz
	222	* @info: pointer into I2C device descriptor table or NULL
	223	* @len: number of descriptors in the table
	224	*
	225	* Returns 0 on success or an error code.
	226	*/
9833eff3	227	int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
85d05fb3 JN	228	struct i2c_board_info const *info,
	229	unsigned len)
	230	{
3a853fb9	231	int err;
85d05fb3	232
3a853fb9	233	BUG_ON(bus_id < 1 \|\| bus_id > omap_i2c_nr_ports());
85d05fb3 JN	234
	235	if (info) {
	236	err = i2c_register_board_info(bus_id, info, len);
	237	if (err)
	238	return err;
	239	}
	240
20c9d2c4 KJ	241	if (!i2c_pdata[bus_id - 1].clkrate)
	242	i2c_pdata[bus_id - 1].clkrate = clkrate;
	243
	244	i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
85d05fb3	245
7954763b	246	return omap_i2c_add_bus(bus_id);
85d05fb3	247	}