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OMAP3: PM: GPMC context save/restore
[net-next-2.6.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
5e1c5ff4
TL		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
5e1c5ff4
TL		 17#include <linux/init.h>
18#include <linux/module.h>
5e1c5ff4 19#include <linux/interrupt.h>
92105bb7
TL		 20#include <linux/sysdev.h>
21#include <linux/err.h>
f8ce2547 22#include <linux/clk.h>
fced80c7 23#include <linux/io.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4
TL		 31/*
32 * OMAP1510 GPIO registers
33 */
9f7065da 34#define OMAP1510_GPIO_BASE 0xfffce000
5e1c5ff4
TL		 35#define OMAP1510_GPIO_DATA_INPUT 0x00
36#define OMAP1510_GPIO_DATA_OUTPUT 0x04
37#define OMAP1510_GPIO_DIR_CONTROL 0x08
38#define OMAP1510_GPIO_INT_CONTROL 0x0c
39#define OMAP1510_GPIO_INT_MASK 0x10
40#define OMAP1510_GPIO_INT_STATUS 0x14
41#define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43#define OMAP1510_IH_GPIO_BASE 64
44
45/*
46 * OMAP1610 specific GPIO registers
47 */
9f7065da
TL		 48#define OMAP1610_GPIO1_BASE 0xfffbe400
49#define OMAP1610_GPIO2_BASE 0xfffbec00
50#define OMAP1610_GPIO3_BASE 0xfffbb400
51#define OMAP1610_GPIO4_BASE 0xfffbbc00
5e1c5ff4
TL		 52#define OMAP1610_GPIO_REVISION 0x0000
53#define OMAP1610_GPIO_SYSCONFIG 0x0010
54#define OMAP1610_GPIO_SYSSTATUS 0x0014
55#define OMAP1610_GPIO_IRQSTATUS1 0x0018
56#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 57#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 58#define OMAP1610_GPIO_DATAIN 0x002c
59#define OMAP1610_GPIO_DATAOUT 0x0030
60#define OMAP1610_GPIO_DIRECTION 0x0034
61#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 64#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 67#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70/*
7c006926 71 * OMAP7XX specific GPIO registers
5e1c5ff4 72 */
9f7065da
TL		 73#define OMAP7XX_GPIO1_BASE 0xfffbc000
74#define OMAP7XX_GPIO2_BASE 0xfffbc800
75#define OMAP7XX_GPIO3_BASE 0xfffbd000
76#define OMAP7XX_GPIO4_BASE 0xfffbd800
77#define OMAP7XX_GPIO5_BASE 0xfffbe000
78#define OMAP7XX_GPIO6_BASE 0xfffbe800
7c006926
AB		 79#define OMAP7XX_GPIO_DATA_INPUT 0x00
80#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81#define OMAP7XX_GPIO_DIR_CONTROL 0x08
82#define OMAP7XX_GPIO_INT_CONTROL 0x0c
83#define OMAP7XX_GPIO_INT_MASK 0x10
84#define OMAP7XX_GPIO_INT_STATUS 0x14
5e1c5ff4 85
9f7065da 86#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
94113260 87
92105bb7
TL		 88/*
89 * omap24xx specific GPIO registers
90 */
9f7065da
TL		 91#define OMAP242X_GPIO1_BASE 0x48018000
92#define OMAP242X_GPIO2_BASE 0x4801a000
93#define OMAP242X_GPIO3_BASE 0x4801c000
94#define OMAP242X_GPIO4_BASE 0x4801e000
56a25641 95
9f7065da
TL		 96#define OMAP243X_GPIO1_BASE 0x4900C000
97#define OMAP243X_GPIO2_BASE 0x4900E000
98#define OMAP243X_GPIO3_BASE 0x49010000
99#define OMAP243X_GPIO4_BASE 0x49012000
100#define OMAP243X_GPIO5_BASE 0x480B6000
56a25641 101
92105bb7
TL		 102#define OMAP24XX_GPIO_REVISION 0x0000
103#define OMAP24XX_GPIO_SYSCONFIG 0x0010
104#define OMAP24XX_GPIO_SYSSTATUS 0x0014
105#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 106#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 108#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 109#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 110#define OMAP24XX_GPIO_CTRL 0x0030
111#define OMAP24XX_GPIO_OE 0x0034
112#define OMAP24XX_GPIO_DATAIN 0x0038
113#define OMAP24XX_GPIO_DATAOUT 0x003c
114#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116#define OMAP24XX_GPIO_RISINGDETECT 0x0048
117#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 118#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 120#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123#define OMAP24XX_GPIO_SETWKUENA 0x0084
124#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125#define OMAP24XX_GPIO_SETDATAOUT 0x0094
126
78a1a6d3
SR		 127#define OMAP4_GPIO_REVISION 0x0000
128#define OMAP4_GPIO_SYSCONFIG 0x0010
129#define OMAP4_GPIO_EOI 0x0020
130#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132#define OMAP4_GPIO_IRQSTATUS0 0x002c
133#define OMAP4_GPIO_IRQSTATUS1 0x0030
134#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138#define OMAP4_GPIO_IRQWAKEN0 0x0044
139#define OMAP4_GPIO_IRQWAKEN1 0x0048
140#define OMAP4_GPIO_SYSSTATUS 0x0104
141#define OMAP4_GPIO_CTRL 0x0130
142#define OMAP4_GPIO_OE 0x0134
143#define OMAP4_GPIO_DATAIN 0x0138
144#define OMAP4_GPIO_DATAOUT 0x013c
145#define OMAP4_GPIO_LEVELDETECT0 0x0140
146#define OMAP4_GPIO_LEVELDETECT1 0x0144
147#define OMAP4_GPIO_RISINGDETECT 0x0148
148#define OMAP4_GPIO_FALLINGDETECT 0x014c
149#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151#define OMAP4_GPIO_CLEARDATAOUT 0x0190
152#define OMAP4_GPIO_SETDATAOUT 0x0194
5492fb1a
SMK		 153/*
154 * omap34xx specific GPIO registers
155 */
156
9f7065da
TL		 157#define OMAP34XX_GPIO1_BASE 0x48310000
158#define OMAP34XX_GPIO2_BASE 0x49050000
159#define OMAP34XX_GPIO3_BASE 0x49052000
160#define OMAP34XX_GPIO4_BASE 0x49054000
161#define OMAP34XX_GPIO5_BASE 0x49056000
162#define OMAP34XX_GPIO6_BASE 0x49058000
5492fb1a 163
44169075
SS		 164/*
165 * OMAP44XX specific GPIO registers
166 */
9f7065da
TL		 167#define OMAP44XX_GPIO1_BASE 0x4a310000
168#define OMAP44XX_GPIO2_BASE 0x48055000
169#define OMAP44XX_GPIO3_BASE 0x48057000
170#define OMAP44XX_GPIO4_BASE 0x48059000
171#define OMAP44XX_GPIO5_BASE 0x4805B000
172#define OMAP44XX_GPIO6_BASE 0x4805D000
5492fb1a 173
5e1c5ff4 174struct gpio_bank {
9f7065da 175 unsigned long pbase;
92105bb7 176 void __iomem *base;
5e1c5ff4
TL		 177 u16 irq;
178 u16 virtual_irq_start;
92105bb7 179 int method;
44169075
SS		 180#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
181 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 182 u32 suspend_wakeup;
183 u32 saved_wakeup;
3ac4fa99 184#endif
44169075
SS		 185#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
186 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 187 u32 non_wakeup_gpios;
188 u32 enabled_non_wakeup_gpios;
189
190 u32 saved_datain;
191 u32 saved_fallingdetect;
192 u32 saved_risingdetect;
193#endif
b144ff6f 194 u32 level_mask;
5e1c5ff4 195 spinlock_t lock;
52e31344 196 struct gpio_chip chip;
89db9482 197 struct clk *dbck;
5e1c5ff4
TL		 198};
199
200#define METHOD_MPUIO 0
201#define METHOD_GPIO_1510 1
202#define METHOD_GPIO_1610 2
7c006926 203#define METHOD_GPIO_7XX 3
56739a69 204#define METHOD_GPIO_24XX 5
5e1c5ff4 205
92105bb7 206#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 207static struct gpio_bank gpio_bank_1610[5] = {
9f7065da
TL		 208 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
209 METHOD_MPUIO },
210 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
211 METHOD_GPIO_1610 },
212 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
213 METHOD_GPIO_1610 },
214 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
215 METHOD_GPIO_1610 },
216 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
217 METHOD_GPIO_1610 },
5e1c5ff4
TL		 218};
219#endif
220
1a8bfa1e 221#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 222static struct gpio_bank gpio_bank_1510[2] = {
9f7065da
TL		 223 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
224 METHOD_MPUIO },
225 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
226 METHOD_GPIO_1510 }
5e1c5ff4
TL		 227};
228#endif
229
b718aa81 230#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926 231static struct gpio_bank gpio_bank_7xx[7] = {
9f7065da
TL		 232 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
233 METHOD_MPUIO },
234 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
235 METHOD_GPIO_7XX },
236 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
237 METHOD_GPIO_7XX },
238 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
239 METHOD_GPIO_7XX },
240 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
241 METHOD_GPIO_7XX },
242 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
243 METHOD_GPIO_7XX },
244 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
245 METHOD_GPIO_7XX },
5e1c5ff4
TL		 246};
247#endif
248
92105bb7 249#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 250
251static struct gpio_bank gpio_bank_242x[4] = {
9f7065da
TL		 252 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
253 METHOD_GPIO_24XX },
254 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
255 METHOD_GPIO_24XX },
256 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
257 METHOD_GPIO_24XX },
258 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
259 METHOD_GPIO_24XX },
92105bb7 260};
56a25641
SMK		 261
262static struct gpio_bank gpio_bank_243x[5] = {
9f7065da
TL		 263 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
264 METHOD_GPIO_24XX },
265 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
266 METHOD_GPIO_24XX },
267 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
268 METHOD_GPIO_24XX },
269 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
270 METHOD_GPIO_24XX },
271 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
272 METHOD_GPIO_24XX },
56a25641
SMK		 273};
274
92105bb7
TL		 275#endif
276
5492fb1a
SMK		 277#ifdef CONFIG_ARCH_OMAP34XX
278static struct gpio_bank gpio_bank_34xx[6] = {
9f7065da
TL		 279 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
280 METHOD_GPIO_24XX },
281 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
282 METHOD_GPIO_24XX },
283 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
284 METHOD_GPIO_24XX },
285 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
286 METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
288 METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
290 METHOD_GPIO_24XX },
5492fb1a
SMK		 291};
292
293#endif
294
44169075
SS		 295#ifdef CONFIG_ARCH_OMAP4
296static struct gpio_bank gpio_bank_44xx[6] = {
9f7065da 297 { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
44169075 298 METHOD_GPIO_24XX },
9f7065da 299 { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
44169075 300 METHOD_GPIO_24XX },
9f7065da 301 { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
44169075 302 METHOD_GPIO_24XX },
9f7065da 303 { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
44169075 304 METHOD_GPIO_24XX },
9f7065da 305 { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
44169075 306 METHOD_GPIO_24XX },
9f7065da 307 { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
44169075
SS		 308 METHOD_GPIO_24XX },
309};
310
311#endif
312
5e1c5ff4
TL		 313static struct gpio_bank *gpio_bank;
314static int gpio_bank_count;
315
316static inline struct gpio_bank *get_gpio_bank(int gpio)
317{
6e60e79a 318 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 319 if (OMAP_GPIO_IS_MPUIO(gpio))
320 return &gpio_bank[0];
321 return &gpio_bank[1];
322 }
5e1c5ff4
TL		 323 if (cpu_is_omap16xx()) {
324 if (OMAP_GPIO_IS_MPUIO(gpio))
325 return &gpio_bank[0];
326 return &gpio_bank[1 + (gpio >> 4)];
327 }
56739a69 328 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 329 if (OMAP_GPIO_IS_MPUIO(gpio))
330 return &gpio_bank[0];
331 return &gpio_bank[1 + (gpio >> 5)];
332 }
92105bb7
TL		 333 if (cpu_is_omap24xx())
334 return &gpio_bank[gpio >> 5];
44169075 335 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 336 return &gpio_bank[gpio >> 5];
e031ab23
DB		 337 BUG();
338 return NULL;
5e1c5ff4
TL		 339}
340
341static inline int get_gpio_index(int gpio)
342{
56739a69 343 if (cpu_is_omap7xx())
5e1c5ff4 344 return gpio & 0x1f;
92105bb7
TL		 345 if (cpu_is_omap24xx())
346 return gpio & 0x1f;
44169075 347 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 348 return gpio & 0x1f;
92105bb7 349 return gpio & 0x0f;
5e1c5ff4
TL		 350}
351
352static inline int gpio_valid(int gpio)
353{
354 if (gpio < 0)
355 return -1;
d11ac979 356 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 357 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 358 return -1;
359 return 0;
360 }
6e60e79a 361 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 362 return 0;
5e1c5ff4
TL		 363 if ((cpu_is_omap16xx()) && gpio < 64)
364 return 0;
56739a69 365 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 366 return 0;
92105bb7
TL		 367 if (cpu_is_omap24xx() && gpio < 128)
368 return 0;
44169075 369 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 370 return 0;
5e1c5ff4
TL		 371 return -1;
372}
373
374static int check_gpio(int gpio)
375{
376 if (unlikely(gpio_valid(gpio)) < 0) {
377 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
378 dump_stack();
379 return -1;
380 }
381 return 0;
382}
383
384static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
385{
92105bb7 386 void __iomem *reg = bank->base;
5e1c5ff4
TL		 387 u32 l;
388
389 switch (bank->method) {
e5c56ed3 390#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 391 case METHOD_MPUIO:
392 reg += OMAP_MPUIO_IO_CNTL;
393 break;
e5c56ed3
DB		 394#endif
395#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 396 case METHOD_GPIO_1510:
397 reg += OMAP1510_GPIO_DIR_CONTROL;
398 break;
e5c56ed3
DB		 399#endif
400#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 401 case METHOD_GPIO_1610:
402 reg += OMAP1610_GPIO_DIRECTION;
403 break;
e5c56ed3 404#endif
b718aa81 405#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 406 case METHOD_GPIO_7XX:
407 reg += OMAP7XX_GPIO_DIR_CONTROL;
5e1c5ff4 408 break;
e5c56ed3 409#endif
78a1a6d3 410#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 411 case METHOD_GPIO_24XX:
412 reg += OMAP24XX_GPIO_OE;
413 break;
78a1a6d3
SR		 414#endif
415#if defined(CONFIG_ARCH_OMAP4)
416 case METHOD_GPIO_24XX:
417 reg += OMAP4_GPIO_OE;
418 break;
e5c56ed3
DB		 419#endif
420 default:
421 WARN_ON(1);
422 return;
5e1c5ff4
TL		 423 }
424 l = __raw_readl(reg);
425 if (is_input)
426 l |= 1 << gpio;
427 else
428 l &= ~(1 << gpio);
429 __raw_writel(l, reg);
430}
431
5e1c5ff4
TL		 432static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
433{
92105bb7 434 void __iomem *reg = bank->base;
5e1c5ff4
TL		 435 u32 l = 0;
436
437 switch (bank->method) {
e5c56ed3 438#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 439 case METHOD_MPUIO:
440 reg += OMAP_MPUIO_OUTPUT;
441 l = __raw_readl(reg);
442 if (enable)
443 l |= 1 << gpio;
444 else
445 l &= ~(1 << gpio);
446 break;
e5c56ed3
DB		 447#endif
448#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 449 case METHOD_GPIO_1510:
450 reg += OMAP1510_GPIO_DATA_OUTPUT;
451 l = __raw_readl(reg);
452 if (enable)
453 l |= 1 << gpio;
454 else
455 l &= ~(1 << gpio);
456 break;
e5c56ed3
DB		 457#endif
458#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 459 case METHOD_GPIO_1610:
460 if (enable)
461 reg += OMAP1610_GPIO_SET_DATAOUT;
462 else
463 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
464 l = 1 << gpio;
465 break;
e5c56ed3 466#endif
b718aa81 467#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 468 case METHOD_GPIO_7XX:
469 reg += OMAP7XX_GPIO_DATA_OUTPUT;
5e1c5ff4
TL		 470 l = __raw_readl(reg);
471 if (enable)
472 l |= 1 << gpio;
473 else
474 l &= ~(1 << gpio);
475 break;
e5c56ed3 476#endif
78a1a6d3 477#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 478 case METHOD_GPIO_24XX:
479 if (enable)
480 reg += OMAP24XX_GPIO_SETDATAOUT;
481 else
482 reg += OMAP24XX_GPIO_CLEARDATAOUT;
483 l = 1 << gpio;
484 break;
78a1a6d3
SR		 485#endif
486#ifdef CONFIG_ARCH_OMAP4
487 case METHOD_GPIO_24XX:
488 if (enable)
489 reg += OMAP4_GPIO_SETDATAOUT;
490 else
491 reg += OMAP4_GPIO_CLEARDATAOUT;
492 l = 1 << gpio;
493 break;
e5c56ed3 494#endif
5e1c5ff4 495 default:
e5c56ed3 496 WARN_ON(1);
5e1c5ff4
TL		 497 return;
498 }
499 __raw_writel(l, reg);
500}
501
b37c45b8 502static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 503{
92105bb7 504 void __iomem *reg;
5e1c5ff4
TL		 505
506 if (check_gpio(gpio) < 0)
e5c56ed3 507 return -EINVAL;
5e1c5ff4
TL		 508 reg = bank->base;
509 switch (bank->method) {
e5c56ed3 510#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 511 case METHOD_MPUIO:
512 reg += OMAP_MPUIO_INPUT_LATCH;
513 break;
e5c56ed3
DB		 514#endif
515#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 516 case METHOD_GPIO_1510:
517 reg += OMAP1510_GPIO_DATA_INPUT;
518 break;
e5c56ed3
DB		 519#endif
520#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 521 case METHOD_GPIO_1610:
522 reg += OMAP1610_GPIO_DATAIN;
523 break;
e5c56ed3 524#endif
b718aa81 525#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 526 case METHOD_GPIO_7XX:
527 reg += OMAP7XX_GPIO_DATA_INPUT;
5e1c5ff4 528 break;
e5c56ed3 529#endif
78a1a6d3 530#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 531 case METHOD_GPIO_24XX:
532 reg += OMAP24XX_GPIO_DATAIN;
533 break;
78a1a6d3
SR		 534#endif
535#ifdef CONFIG_ARCH_OMAP4
536 case METHOD_GPIO_24XX:
537 reg += OMAP4_GPIO_DATAIN;
538 break;
e5c56ed3 539#endif
5e1c5ff4 540 default:
e5c56ed3 541 return -EINVAL;
5e1c5ff4 542 }
92105bb7
TL		 543 return (__raw_readl(reg)
544 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 545}
546
b37c45b8
RQ		 547static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
548{
549 void __iomem *reg;
550
551 if (check_gpio(gpio) < 0)
552 return -EINVAL;
553 reg = bank->base;
554
555 switch (bank->method) {
556#ifdef CONFIG_ARCH_OMAP1
557 case METHOD_MPUIO:
558 reg += OMAP_MPUIO_OUTPUT;
559 break;
560#endif
561#ifdef CONFIG_ARCH_OMAP15XX
562 case METHOD_GPIO_1510:
563 reg += OMAP1510_GPIO_DATA_OUTPUT;
564 break;
565#endif
566#ifdef CONFIG_ARCH_OMAP16XX
567 case METHOD_GPIO_1610:
568 reg += OMAP1610_GPIO_DATAOUT;
569 break;
570#endif
b718aa81 571#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 572 case METHOD_GPIO_7XX:
573 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 574 break;
575#endif
b37c45b8
RQ		 576#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
577 defined(CONFIG_ARCH_OMAP4)
578 case METHOD_GPIO_24XX:
579 reg += OMAP24XX_GPIO_DATAOUT;
580 break;
581#endif
582 default:
583 return -EINVAL;
584 }
585
586 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
587}
588
92105bb7
TL		 589#define MOD_REG_BIT(reg, bit_mask, set) \
590do { \
591 int l = __raw_readl(base + reg); \
592 if (set) l |= bit_mask; \
593 else l &= ~bit_mask; \
594 __raw_writel(l, base + reg); \
595} while(0)
596
5eb3bb9c
KH		 597void omap_set_gpio_debounce(int gpio, int enable)
598{
599 struct gpio_bank *bank;
600 void __iomem *reg;
e031ab23 601 unsigned long flags;
5eb3bb9c
KH		 602 u32 val, l = 1 << get_gpio_index(gpio);
603
604 if (cpu_class_is_omap1())
605 return;
606
607 bank = get_gpio_bank(gpio);
608 reg = bank->base;
78a1a6d3
SR		 609#ifdef CONFIG_ARCH_OMAP4
610 reg += OMAP4_GPIO_DEBOUNCENABLE;
611#else
5eb3bb9c 612 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
78a1a6d3 613#endif
e031ab23
DB		 614
615 spin_lock_irqsave(&bank->lock, flags);
5eb3bb9c
KH		 616 val = __raw_readl(reg);
617
89db9482 618 if (enable && !(val & l))
5eb3bb9c 619 val |= l;
e031ab23 620 else if (!enable && (val & l))
5eb3bb9c 621 val &= ~l;
89db9482 622 else
e031ab23 623 goto done;
89db9482 624
44169075 625 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
e031ab23
DB		 626 if (enable)
627 clk_enable(bank->dbck);
628 else
629 clk_disable(bank->dbck);
630 }
5eb3bb9c
KH		 631
632 __raw_writel(val, reg);
e031ab23
DB		 633done:
634 spin_unlock_irqrestore(&bank->lock, flags);
5eb3bb9c
KH		 635}
636EXPORT_SYMBOL(omap_set_gpio_debounce);
637
638void omap_set_gpio_debounce_time(int gpio, int enc_time)
639{
640 struct gpio_bank *bank;
641 void __iomem *reg;
642
643 if (cpu_class_is_omap1())
644 return;
645
646 bank = get_gpio_bank(gpio);
647 reg = bank->base;
648
649 enc_time &= 0xff;
78a1a6d3
SR		 650#ifdef CONFIG_ARCH_OMAP4
651 reg += OMAP4_GPIO_DEBOUNCINGTIME;
652#else
5eb3bb9c 653 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
78a1a6d3 654#endif
5eb3bb9c
KH		 655 __raw_writel(enc_time, reg);
656}
657EXPORT_SYMBOL(omap_set_gpio_debounce_time);
658
44169075
SS		 659#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
660 defined(CONFIG_ARCH_OMAP4)
5eb3bb9c
KH		 661static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
662 int trigger)
5e1c5ff4 663{
3ac4fa99 664 void __iomem *base = bank->base;
92105bb7 665 u32 gpio_bit = 1 << gpio;
78a1a6d3 666 u32 val;
92105bb7 667
78a1a6d3
SR		 668 if (cpu_is_omap44xx()) {
669 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
670 trigger & IRQ_TYPE_LEVEL_LOW);
671 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
672 trigger & IRQ_TYPE_LEVEL_HIGH);
673 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
674 trigger & IRQ_TYPE_EDGE_RISING);
675 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
676 trigger & IRQ_TYPE_EDGE_FALLING);
677 } else {
678 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
679 trigger & IRQ_TYPE_LEVEL_LOW);
680 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
681 trigger & IRQ_TYPE_LEVEL_HIGH);
682 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
683 trigger & IRQ_TYPE_EDGE_RISING);
684 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
685 trigger & IRQ_TYPE_EDGE_FALLING);
686 }
3ac4fa99 687 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3
SR		 688 if (cpu_is_omap44xx()) {
689 if (trigger != 0)
690 __raw_writel(1 << gpio, bank->base+
691 OMAP4_GPIO_IRQWAKEN0);
692 else {
693 val = __raw_readl(bank->base +
694 OMAP4_GPIO_IRQWAKEN0);
695 __raw_writel(val & (~(1 << gpio)), bank->base +
696 OMAP4_GPIO_IRQWAKEN0);
697 }
698 } else {
699 if (trigger != 0)
700 __raw_writel(1 << gpio, bank->base
5eb3bb9c 701 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 702 else
703 __raw_writel(1 << gpio, bank->base
5eb3bb9c 704 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 705 }
3ac4fa99
JY		 706 } else {
707 if (trigger != 0)
708 bank->enabled_non_wakeup_gpios |= gpio_bit;
709 else
710 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
711 }
5eb3bb9c 712
78a1a6d3
SR		 713 if (cpu_is_omap44xx()) {
714 bank->level_mask =
715 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
716 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
717 } else {
718 bank->level_mask =
719 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
720 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
721 }
92105bb7 722}
3ac4fa99 723#endif
92105bb7
TL		 724
725static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
726{
727 void __iomem *reg = bank->base;
728 u32 l = 0;
5e1c5ff4
TL		 729
730 switch (bank->method) {
e5c56ed3 731#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 732 case METHOD_MPUIO:
733 reg += OMAP_MPUIO_GPIO_INT_EDGE;
734 l = __raw_readl(reg);
6cab4860 735 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 736 l |= 1 << gpio;
6cab4860 737 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 738 l &= ~(1 << gpio);
92105bb7
TL		 739 else
740 goto bad;
5e1c5ff4 741 break;
e5c56ed3
DB		 742#endif
743#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 744 case METHOD_GPIO_1510:
745 reg += OMAP1510_GPIO_INT_CONTROL;
746 l = __raw_readl(reg);
6cab4860 747 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 748 l |= 1 << gpio;
6cab4860 749 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 750 l &= ~(1 << gpio);
92105bb7
TL		 751 else
752 goto bad;
5e1c5ff4 753 break;
e5c56ed3 754#endif
3ac4fa99 755#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 756 case METHOD_GPIO_1610:
5e1c5ff4
TL		 757 if (gpio & 0x08)
758 reg += OMAP1610_GPIO_EDGE_CTRL2;
759 else
760 reg += OMAP1610_GPIO_EDGE_CTRL1;
761 gpio &= 0x07;
762 l = __raw_readl(reg);
763 l &= ~(3 << (gpio << 1));
6cab4860 764 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 765 l |= 2 << (gpio << 1);
6cab4860 766 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 767 l |= 1 << (gpio << 1);
3ac4fa99
JY		 768 if (trigger)
769 /* Enable wake-up during idle for dynamic tick */
770 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
771 else
772 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 773 break;
3ac4fa99 774#endif
b718aa81 775#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 776 case METHOD_GPIO_7XX:
777 reg += OMAP7XX_GPIO_INT_CONTROL;
5e1c5ff4 778 l = __raw_readl(reg);
6cab4860 779 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 780 l |= 1 << gpio;
6cab4860 781 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 782 l &= ~(1 << gpio);
92105bb7
TL		 783 else
784 goto bad;
785 break;
3ac4fa99 786#endif
44169075
SS		 787#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
788 defined(CONFIG_ARCH_OMAP4)
92105bb7 789 case METHOD_GPIO_24XX:
3ac4fa99 790 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 791 break;
3ac4fa99 792#endif
5e1c5ff4 793 default:
92105bb7 794 goto bad;
5e1c5ff4 795 }
92105bb7
TL		 796 __raw_writel(l, reg);
797 return 0;
798bad:
799 return -EINVAL;
5e1c5ff4
TL		 800}
801
92105bb7 802static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 803{
804 struct gpio_bank *bank;
92105bb7
TL		 805 unsigned gpio;
806 int retval;
a6472533 807 unsigned long flags;
92105bb7 808
5492fb1a 809 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 810 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
811 else
812 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 813
814 if (check_gpio(gpio) < 0)
92105bb7
TL		 815 return -EINVAL;
816
e5c56ed3 817 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 818 return -EINVAL;
e5c56ed3
DB		 819
820 /* OMAP1 allows only only edge triggering */
5492fb1a 821 if (!cpu_class_is_omap2()
e5c56ed3 822 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 823 return -EINVAL;
824
58781016 825 bank = get_irq_chip_data(irq);
a6472533 826 spin_lock_irqsave(&bank->lock, flags);
92105bb7 827 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 828 if (retval == 0) {
829 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
830 irq_desc[irq].status |= type;
831 }
a6472533 832 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 833
834 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
835 __set_irq_handler_unlocked(irq, handle_level_irq);
836 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
837 __set_irq_handler_unlocked(irq, handle_edge_irq);
838
92105bb7 839 return retval;
5e1c5ff4
TL		 840}
841
842static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
843{
92105bb7 844 void __iomem *reg = bank->base;
5e1c5ff4
TL		 845
846 switch (bank->method) {
e5c56ed3 847#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 848 case METHOD_MPUIO:
849 /* MPUIO irqstatus is reset by reading the status register,
850 * so do nothing here */
851 return;
e5c56ed3
DB		 852#endif
853#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 854 case METHOD_GPIO_1510:
855 reg += OMAP1510_GPIO_INT_STATUS;
856 break;
e5c56ed3
DB		 857#endif
858#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 859 case METHOD_GPIO_1610:
860 reg += OMAP1610_GPIO_IRQSTATUS1;
861 break;
e5c56ed3 862#endif
b718aa81 863#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 864 case METHOD_GPIO_7XX:
865 reg += OMAP7XX_GPIO_INT_STATUS;
5e1c5ff4 866 break;
e5c56ed3 867#endif
78a1a6d3 868#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 869 case METHOD_GPIO_24XX:
870 reg += OMAP24XX_GPIO_IRQSTATUS1;
871 break;
78a1a6d3
SR		 872#endif
873#if defined(CONFIG_ARCH_OMAP4)
874 case METHOD_GPIO_24XX:
875 reg += OMAP4_GPIO_IRQSTATUS0;
876 break;
e5c56ed3 877#endif
5e1c5ff4 878 default:
e5c56ed3 879 WARN_ON(1);
5e1c5ff4
TL		 880 return;
881 }
882 __raw_writel(gpio_mask, reg);
bee7930f
HD		 883
884 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a 885#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
bedfd154 886 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
78a1a6d3
SR		 887#endif
888#if defined(CONFIG_ARCH_OMAP4)
889 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
890#endif
891 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
bedfd154
RQ		 892 __raw_writel(gpio_mask, reg);
893
894 /* Flush posted write for the irq status to avoid spurious interrupts */
895 __raw_readl(reg);
78a1a6d3 896 }
5e1c5ff4
TL		 897}
898
899static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
900{
901 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
902}
903
ea6dedd7
ID		 904static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
905{
906 void __iomem *reg = bank->base;
99c47707
ID		 907 int inv = 0;
908 u32 l;
909 u32 mask;
ea6dedd7
ID		 910
911 switch (bank->method) {
e5c56ed3 912#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 913 case METHOD_MPUIO:
914 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 915 mask = 0xffff;
916 inv = 1;
ea6dedd7 917 break;
e5c56ed3
DB		 918#endif
919#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 920 case METHOD_GPIO_1510:
921 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 922 mask = 0xffff;
923 inv = 1;
ea6dedd7 924 break;
e5c56ed3
DB		 925#endif
926#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 927 case METHOD_GPIO_1610:
928 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 929 mask = 0xffff;
ea6dedd7 930 break;
e5c56ed3 931#endif
b718aa81 932#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 933 case METHOD_GPIO_7XX:
934 reg += OMAP7XX_GPIO_INT_MASK;
99c47707
ID		 935 mask = 0xffffffff;
936 inv = 1;
ea6dedd7 937 break;
e5c56ed3 938#endif
78a1a6d3 939#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 940 case METHOD_GPIO_24XX:
941 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 942 mask = 0xffffffff;
ea6dedd7 943 break;
78a1a6d3
SR		 944#endif
945#if defined(CONFIG_ARCH_OMAP4)
946 case METHOD_GPIO_24XX:
947 reg += OMAP4_GPIO_IRQSTATUSSET0;
948 mask = 0xffffffff;
949 break;
e5c56ed3 950#endif
ea6dedd7 951 default:
e5c56ed3 952 WARN_ON(1);
ea6dedd7
ID		 953 return 0;
954 }
955
99c47707
ID		 956 l = __raw_readl(reg);
957 if (inv)
958 l = ~l;
959 l &= mask;
960 return l;
ea6dedd7
ID		 961}
962
5e1c5ff4
TL		 963static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
964{
92105bb7 965 void __iomem *reg = bank->base;
5e1c5ff4
TL		 966 u32 l;
967
968 switch (bank->method) {
e5c56ed3 969#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 970 case METHOD_MPUIO:
971 reg += OMAP_MPUIO_GPIO_MASKIT;
972 l = __raw_readl(reg);
973 if (enable)
974 l &= ~(gpio_mask);
975 else
976 l |= gpio_mask;
977 break;
e5c56ed3
DB		 978#endif
979#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 980 case METHOD_GPIO_1510:
981 reg += OMAP1510_GPIO_INT_MASK;
982 l = __raw_readl(reg);
983 if (enable)
984 l &= ~(gpio_mask);
985 else
986 l |= gpio_mask;
987 break;
e5c56ed3
DB		 988#endif
989#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 990 case METHOD_GPIO_1610:
991 if (enable)
992 reg += OMAP1610_GPIO_SET_IRQENABLE1;
993 else
994 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
995 l = gpio_mask;
996 break;
e5c56ed3 997#endif
b718aa81 998#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 999 case METHOD_GPIO_7XX:
1000 reg += OMAP7XX_GPIO_INT_MASK;
5e1c5ff4
TL		 1001 l = __raw_readl(reg);
1002 if (enable)
1003 l &= ~(gpio_mask);
1004 else
1005 l |= gpio_mask;
1006 break;
e5c56ed3 1007#endif
78a1a6d3 1008#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1009 case METHOD_GPIO_24XX:
1010 if (enable)
1011 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1012 else
1013 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1014 l = gpio_mask;
1015 break;
78a1a6d3
SR		 1016#endif
1017#ifdef CONFIG_ARCH_OMAP4
1018 case METHOD_GPIO_24XX:
1019 if (enable)
1020 reg += OMAP4_GPIO_IRQSTATUSSET0;
1021 else
1022 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1023 l = gpio_mask;
1024 break;
e5c56ed3 1025#endif
5e1c5ff4 1026 default:
e5c56ed3 1027 WARN_ON(1);
5e1c5ff4
TL		 1028 return;
1029 }
1030 __raw_writel(l, reg);
1031}
1032
1033static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1034{
1035 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1036}
1037
92105bb7
TL		 1038/*
1039 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1040 * 1510 does not seem to have a wake-up register. If JTAG is connected
1041 * to the target, system will wake up always on GPIO events. While
1042 * system is running all registered GPIO interrupts need to have wake-up
1043 * enabled. When system is suspended, only selected GPIO interrupts need
1044 * to have wake-up enabled.
1045 */
1046static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1047{
a6472533
DB		 1048 unsigned long flags;
1049
92105bb7 1050 switch (bank->method) {
3ac4fa99 1051#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 1052 case METHOD_MPUIO:
92105bb7 1053 case METHOD_GPIO_1610:
a6472533 1054 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1055 if (enable)
92105bb7 1056 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1057 else
92105bb7 1058 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1059 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1060 return 0;
3ac4fa99 1061#endif
44169075
SS		 1062#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1063 defined(CONFIG_ARCH_OMAP4)
3ac4fa99 1064 case METHOD_GPIO_24XX:
11a78b79
DB		 1065 if (bank->non_wakeup_gpios & (1 << gpio)) {
1066 printk(KERN_ERR "Unable to modify wakeup on "
1067 "non-wakeup GPIO%d\n",
1068 (bank - gpio_bank) * 32 + gpio);
1069 return -EINVAL;
1070 }
a6472533 1071 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1072 if (enable)
3ac4fa99 1073 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1074 else
3ac4fa99 1075 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1076 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 1077 return 0;
1078#endif
92105bb7
TL		 1079 default:
1080 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1081 bank->method);
1082 return -EINVAL;
1083 }
1084}
1085
4196dd6b
TL		 1086static void _reset_gpio(struct gpio_bank *bank, int gpio)
1087{
1088 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1089 _set_gpio_irqenable(bank, gpio, 0);
1090 _clear_gpio_irqstatus(bank, gpio);
6cab4860 1091 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 1092}
1093
92105bb7
TL		 1094/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1095static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1096{
1097 unsigned int gpio = irq - IH_GPIO_BASE;
1098 struct gpio_bank *bank;
1099 int retval;
1100
1101 if (check_gpio(gpio) < 0)
1102 return -ENODEV;
58781016 1103 bank = get_irq_chip_data(irq);
92105bb7 1104 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 1105
1106 return retval;
1107}
1108
3ff164e1 1109static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1110{
3ff164e1 1111 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1112 unsigned long flags;
52e31344 1113
a6472533 1114 spin_lock_irqsave(&bank->lock, flags);
92105bb7 1115
4196dd6b
TL		 1116 /* Set trigger to none. You need to enable the desired trigger with
1117 * request_irq() or set_irq_type().
1118 */
3ff164e1 1119 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 1120
1a8bfa1e 1121#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 1122 if (bank->method == METHOD_GPIO_1510) {
92105bb7 1123 void __iomem *reg;
5e1c5ff4 1124
92105bb7 1125 /* Claim the pin for MPU */
5e1c5ff4 1126 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 1127 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 1128 }
1129#endif
a6472533 1130 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1131
1132 return 0;
1133}
1134
3ff164e1 1135static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1136{
3ff164e1 1137 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1138 unsigned long flags;
5e1c5ff4 1139
a6472533 1140 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1141#ifdef CONFIG_ARCH_OMAP16XX
1142 if (bank->method == METHOD_GPIO_1610) {
1143 /* Disable wake-up during idle for dynamic tick */
1144 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 1145 __raw_writel(1 << offset, reg);
92105bb7
TL		 1146 }
1147#endif
44169075
SS		 1148#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1149 defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 1150 if (bank->method == METHOD_GPIO_24XX) {
1151 /* Disable wake-up during idle for dynamic tick */
1152 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 1153 __raw_writel(1 << offset, reg);
92105bb7
TL		 1154 }
1155#endif
3ff164e1 1156 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1157 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1158}
1159
1160/*
1161 * We need to unmask the GPIO bank interrupt as soon as possible to
1162 * avoid missing GPIO interrupts for other lines in the bank.
1163 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1164 * in the bank to avoid missing nested interrupts for a GPIO line.
1165 * If we wait to unmask individual GPIO lines in the bank after the
1166 * line's interrupt handler has been run, we may miss some nested
1167 * interrupts.
1168 */
10dd5ce2 1169static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1170{
92105bb7 1171 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 1172 u32 isr;
1173 unsigned int gpio_irq;
1174 struct gpio_bank *bank;
ea6dedd7
ID		 1175 u32 retrigger = 0;
1176 int unmasked = 0;
5e1c5ff4
TL		 1177
1178 desc->chip->ack(irq);
1179
418ca1f0 1180 bank = get_irq_data(irq);
e5c56ed3 1181#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 1182 if (bank->method == METHOD_MPUIO)
1183 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 1184#endif
1a8bfa1e 1185#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1186 if (bank->method == METHOD_GPIO_1510)
1187 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1188#endif
1189#if defined(CONFIG_ARCH_OMAP16XX)
1190 if (bank->method == METHOD_GPIO_1610)
1191 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1192#endif
b718aa81 1193#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1194 if (bank->method == METHOD_GPIO_7XX)
1195 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
5e1c5ff4 1196#endif
78a1a6d3 1197#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1198 if (bank->method == METHOD_GPIO_24XX)
1199 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1200#endif
1201#if defined(CONFIG_ARCH_OMAP4)
1202 if (bank->method == METHOD_GPIO_24XX)
1203 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1204#endif
92105bb7 1205 while(1) {
6e60e79a 1206 u32 isr_saved, level_mask = 0;
ea6dedd7 1207 u32 enabled;
6e60e79a 1208
ea6dedd7
ID		 1209 enabled = _get_gpio_irqbank_mask(bank);
1210 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1211
1212 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1213 isr &= 0x0000ffff;
1214
5492fb1a 1215 if (cpu_class_is_omap2()) {
b144ff6f 1216 level_mask = bank->level_mask & enabled;
ea6dedd7 1217 }
6e60e79a
TL		 1218
1219 /* clear edge sensitive interrupts before handler(s) are
1220 called so that we don't miss any interrupt occurred while
1221 executing them */
1222 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1223 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1224 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1225
1226 /* if there is only edge sensitive GPIO pin interrupts
1227 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1228 if (!level_mask && !unmasked) {
1229 unmasked = 1;
6e60e79a 1230 desc->chip->unmask(irq);
ea6dedd7 1231 }
92105bb7 1232
ea6dedd7
ID		 1233 isr |= retrigger;
1234 retrigger = 0;
92105bb7
TL		 1235 if (!isr)
1236 break;
1237
1238 gpio_irq = bank->virtual_irq_start;
1239 for (; isr != 0; isr >>= 1, gpio_irq++) {
92105bb7
TL		 1240 if (!(isr & 1))
1241 continue;
29454dde 1242
d8aa0251 1243 generic_handle_irq(gpio_irq);
92105bb7 1244 }
1a8bfa1e 1245 }
ea6dedd7
ID		 1246 /* if bank has any level sensitive GPIO pin interrupt
1247 configured, we must unmask the bank interrupt only after
1248 handler(s) are executed in order to avoid spurious bank
1249 interrupt */
1250 if (!unmasked)
1251 desc->chip->unmask(irq);
1252
5e1c5ff4
TL		 1253}
1254
4196dd6b
TL		 1255static void gpio_irq_shutdown(unsigned int irq)
1256{
1257 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1258 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1259
1260 _reset_gpio(bank, gpio);
1261}
1262
5e1c5ff4
TL		 1263static void gpio_ack_irq(unsigned int irq)
1264{
1265 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1266 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1267
1268 _clear_gpio_irqstatus(bank, gpio);
1269}
1270
1271static void gpio_mask_irq(unsigned int irq)
1272{
1273 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1274 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1275
1276 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1277 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
5e1c5ff4
TL		 1278}
1279
1280static void gpio_unmask_irq(unsigned int irq)
1281{
1282 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1283 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f 1284 unsigned int irq_mask = 1 << get_gpio_index(gpio);
55b6019a
KH		 1285 struct irq_desc *desc = irq_to_desc(irq);
1286 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1287
1288 if (trigger)
1289 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1290
1291 /* For level-triggered GPIOs, the clearing must be done after
1292 * the HW source is cleared, thus after the handler has run */
1293 if (bank->level_mask & irq_mask) {
1294 _set_gpio_irqenable(bank, gpio, 0);
1295 _clear_gpio_irqstatus(bank, gpio);
1296 }
5e1c5ff4 1297
4de8c75b 1298 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1299}
1300
e5c56ed3
DB		 1301static struct irq_chip gpio_irq_chip = {
1302 .name = "GPIO",
1303 .shutdown = gpio_irq_shutdown,
1304 .ack = gpio_ack_irq,
1305 .mask = gpio_mask_irq,
1306 .unmask = gpio_unmask_irq,
1307 .set_type = gpio_irq_type,
1308 .set_wake = gpio_wake_enable,
1309};
1310
1311/*---------------------------------------------------------------------*/
1312
1313#ifdef CONFIG_ARCH_OMAP1
1314
1315/* MPUIO uses the always-on 32k clock */
1316
5e1c5ff4
TL		 1317static void mpuio_ack_irq(unsigned int irq)
1318{
1319 /* The ISR is reset automatically, so do nothing here. */
1320}
1321
1322static void mpuio_mask_irq(unsigned int irq)
1323{
1324 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1325 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1326
1327 _set_gpio_irqenable(bank, gpio, 0);
1328}
1329
1330static void mpuio_unmask_irq(unsigned int irq)
1331{
1332 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1333 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1334
1335 _set_gpio_irqenable(bank, gpio, 1);
1336}
1337
e5c56ed3
DB		 1338static struct irq_chip mpuio_irq_chip = {
1339 .name = "MPUIO",
1340 .ack = mpuio_ack_irq,
1341 .mask = mpuio_mask_irq,
1342 .unmask = mpuio_unmask_irq,
92105bb7 1343 .set_type = gpio_irq_type,
11a78b79
DB		 1344#ifdef CONFIG_ARCH_OMAP16XX
1345 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1346 .set_wake = gpio_wake_enable,
1347#endif
5e1c5ff4
TL		 1348};
1349
e5c56ed3
DB		 1350
1351#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1352
11a78b79
DB		 1353
1354#ifdef CONFIG_ARCH_OMAP16XX
1355
1356#include <linux/platform_device.h>
1357
79ee031f 1358static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1359{
79ee031f 1360 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1361 struct gpio_bank *bank = platform_get_drvdata(pdev);
1362 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1363 unsigned long flags;
11a78b79 1364
a6472533 1365 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1366 bank->saved_wakeup = __raw_readl(mask_reg);
1367 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1368 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1369
1370 return 0;
1371}
1372
79ee031f 1373static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1374{
79ee031f 1375 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1376 struct gpio_bank *bank = platform_get_drvdata(pdev);
1377 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1378 unsigned long flags;
11a78b79 1379
a6472533 1380 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1381 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1382 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1383
1384 return 0;
1385}
1386
79ee031f
MD		 1387static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1388 .suspend_noirq = omap_mpuio_suspend_noirq,
1389 .resume_noirq = omap_mpuio_resume_noirq,
1390};
1391
11a78b79
DB		 1392/* use platform_driver for this, now that there's no longer any
1393 * point to sys_device (other than not disturbing old code).
1394 */
1395static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1396 .driver = {
1397 .name = "mpuio",
79ee031f 1398 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1399 },
1400};
1401
1402static struct platform_device omap_mpuio_device = {
1403 .name = "mpuio",
1404 .id = -1,
1405 .dev = {
1406 .driver = &omap_mpuio_driver.driver,
1407 }
1408 /* could list the /proc/iomem resources */
1409};
1410
1411static inline void mpuio_init(void)
1412{
fcf126d8
DB		 1413 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1414
11a78b79
DB		 1415 if (platform_driver_register(&omap_mpuio_driver) == 0)
1416 (void) platform_device_register(&omap_mpuio_device);
1417}
1418
1419#else
1420static inline void mpuio_init(void) {}
1421#endif /* 16xx */
1422
e5c56ed3
DB		 1423#else
1424
1425extern struct irq_chip mpuio_irq_chip;
1426
1427#define bank_is_mpuio(bank) 0
11a78b79 1428static inline void mpuio_init(void) {}
e5c56ed3
DB		 1429
1430#endif
1431
1432/*---------------------------------------------------------------------*/
5e1c5ff4 1433
52e31344
DB		 1434/* REVISIT these are stupid implementations! replace by ones that
1435 * don't switch on METHOD_* and which mostly avoid spinlocks
1436 */
1437
1438static int gpio_input(struct gpio_chip *chip, unsigned offset)
1439{
1440 struct gpio_bank *bank;
1441 unsigned long flags;
1442
1443 bank = container_of(chip, struct gpio_bank, chip);
1444 spin_lock_irqsave(&bank->lock, flags);
1445 _set_gpio_direction(bank, offset, 1);
1446 spin_unlock_irqrestore(&bank->lock, flags);
1447 return 0;
1448}
1449
b37c45b8
RQ		 1450static int gpio_is_input(struct gpio_bank *bank, int mask)
1451{
1452 void __iomem *reg = bank->base;
1453
1454 switch (bank->method) {
1455 case METHOD_MPUIO:
1456 reg += OMAP_MPUIO_IO_CNTL;
1457 break;
1458 case METHOD_GPIO_1510:
1459 reg += OMAP1510_GPIO_DIR_CONTROL;
1460 break;
1461 case METHOD_GPIO_1610:
1462 reg += OMAP1610_GPIO_DIRECTION;
1463 break;
7c006926
AB		 1464 case METHOD_GPIO_7XX:
1465 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8 1466 break;
b37c45b8
RQ		 1467 case METHOD_GPIO_24XX:
1468 reg += OMAP24XX_GPIO_OE;
1469 break;
1470 }
1471 return __raw_readl(reg) & mask;
1472}
1473
52e31344
DB		 1474static int gpio_get(struct gpio_chip *chip, unsigned offset)
1475{
b37c45b8
RQ		 1476 struct gpio_bank *bank;
1477 void __iomem *reg;
1478 int gpio;
1479 u32 mask;
1480
1481 gpio = chip->base + offset;
1482 bank = get_gpio_bank(gpio);
1483 reg = bank->base;
1484 mask = 1 << get_gpio_index(gpio);
1485
1486 if (gpio_is_input(bank, mask))
1487 return _get_gpio_datain(bank, gpio);
1488 else
1489 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1490}
1491
1492static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1493{
1494 struct gpio_bank *bank;
1495 unsigned long flags;
1496
1497 bank = container_of(chip, struct gpio_bank, chip);
1498 spin_lock_irqsave(&bank->lock, flags);
1499 _set_gpio_dataout(bank, offset, value);
1500 _set_gpio_direction(bank, offset, 0);
1501 spin_unlock_irqrestore(&bank->lock, flags);
1502 return 0;
1503}
1504
1505static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1506{
1507 struct gpio_bank *bank;
1508 unsigned long flags;
1509
1510 bank = container_of(chip, struct gpio_bank, chip);
1511 spin_lock_irqsave(&bank->lock, flags);
1512 _set_gpio_dataout(bank, offset, value);
1513 spin_unlock_irqrestore(&bank->lock, flags);
1514}
1515
a007b709
DB		 1516static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1517{
1518 struct gpio_bank *bank;
1519
1520 bank = container_of(chip, struct gpio_bank, chip);
1521 return bank->virtual_irq_start + offset;
1522}
1523
52e31344
DB		 1524/*---------------------------------------------------------------------*/
1525
1a8bfa1e 1526static int initialized;
44169075 1527#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1a8bfa1e 1528static struct clk * gpio_ick;
5492fb1a
SMK		 1529#endif
1530
1531#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1532static struct clk * gpio_fck;
5492fb1a 1533#endif
5e1c5ff4 1534
5492fb1a 1535#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1536static struct clk * gpio5_ick;
1537static struct clk * gpio5_fck;
1538#endif
1539
44169075 1540#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
5492fb1a
SMK		 1541static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1542#endif
1543
9f7065da
TL		 1544static void __init omap_gpio_show_rev(void)
1545{
1546 u32 rev;
1547
1548 if (cpu_is_omap16xx())
1549 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1550 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1551 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1552 else if (cpu_is_omap44xx())
1553 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1554 else
1555 return;
1556
1557 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1558 (rev >> 4) & 0x0f, rev & 0x0f);
1559}
1560
8ba55c5c
DB		 1561/* This lock class tells lockdep that GPIO irqs are in a different
1562 * category than their parents, so it won't report false recursion.
1563 */
1564static struct lock_class_key gpio_lock_class;
1565
5e1c5ff4
TL		 1566static int __init _omap_gpio_init(void)
1567{
1568 int i;
52e31344 1569 int gpio = 0;
5e1c5ff4 1570 struct gpio_bank *bank;
9f7065da 1571 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
5492fb1a 1572 char clk_name[11];
5e1c5ff4
TL		 1573
1574 initialized = 1;
1575
5492fb1a 1576#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1577 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1578 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1579 if (IS_ERR(gpio_ick))
92105bb7
TL		 1580 printk("Could not get arm_gpio_ck\n");
1581 else
30ff720b 1582 clk_enable(gpio_ick);
1a8bfa1e 1583 }
5492fb1a
SMK		 1584#endif
1585#if defined(CONFIG_ARCH_OMAP2)
1586 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1587 gpio_ick = clk_get(NULL, "gpios_ick");
1588 if (IS_ERR(gpio_ick))
1589 printk("Could not get gpios_ick\n");
1590 else
30ff720b 1591 clk_enable(gpio_ick);
1a8bfa1e 1592 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1593 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1594 printk("Could not get gpios_fck\n");
1595 else
30ff720b 1596 clk_enable(gpio_fck);
56a25641
SMK		 1597
1598 /*
5492fb1a 1599 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1600 */
5492fb1a 1601#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1602 if (cpu_is_omap2430()) {
1603 gpio5_ick = clk_get(NULL, "gpio5_ick");
1604 if (IS_ERR(gpio5_ick))
1605 printk("Could not get gpio5_ick\n");
1606 else
1607 clk_enable(gpio5_ick);
1608 gpio5_fck = clk_get(NULL, "gpio5_fck");
1609 if (IS_ERR(gpio5_fck))
1610 printk("Could not get gpio5_fck\n");
1611 else
1612 clk_enable(gpio5_fck);
1613 }
1614#endif
5492fb1a
SMK		 1615 }
1616#endif
1617
44169075
SS		 1618#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1619 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
5492fb1a
SMK		 1620 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1621 sprintf(clk_name, "gpio%d_ick", i + 1);
1622 gpio_iclks[i] = clk_get(NULL, clk_name);
1623 if (IS_ERR(gpio_iclks[i]))
1624 printk(KERN_ERR "Could not get %s\n", clk_name);
1625 else
1626 clk_enable(gpio_iclks[i]);
5492fb1a
SMK		 1627 }
1628 }
1629#endif
1630
92105bb7 1631
1a8bfa1e 1632#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1633 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1634 gpio_bank_count = 2;
1635 gpio_bank = gpio_bank_1510;
9f7065da 1636 bank_size = SZ_2K;
5e1c5ff4
TL		 1637 }
1638#endif
1639#if defined(CONFIG_ARCH_OMAP16XX)
1640 if (cpu_is_omap16xx()) {
5e1c5ff4
TL		 1641 gpio_bank_count = 5;
1642 gpio_bank = gpio_bank_1610;
9f7065da 1643 bank_size = SZ_2K;
5e1c5ff4
TL		 1644 }
1645#endif
b718aa81
AB		 1646#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1647 if (cpu_is_omap7xx()) {
5e1c5ff4 1648 gpio_bank_count = 7;
7c006926 1649 gpio_bank = gpio_bank_7xx;
9f7065da 1650 bank_size = SZ_2K;
5e1c5ff4 1651 }
92105bb7
TL		 1652#endif
1653#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1654 if (cpu_is_omap242x()) {
92105bb7 1655 gpio_bank_count = 4;
56a25641 1656 gpio_bank = gpio_bank_242x;
56a25641
SMK		 1657 }
1658 if (cpu_is_omap243x()) {
56a25641
SMK		 1659 gpio_bank_count = 5;
1660 gpio_bank = gpio_bank_243x;
92105bb7 1661 }
5492fb1a
SMK		 1662#endif
1663#ifdef CONFIG_ARCH_OMAP34XX
1664 if (cpu_is_omap34xx()) {
5492fb1a
SMK		 1665 gpio_bank_count = OMAP34XX_NR_GPIOS;
1666 gpio_bank = gpio_bank_34xx;
5492fb1a 1667 }
44169075
SS		 1668#endif
1669#ifdef CONFIG_ARCH_OMAP4
1670 if (cpu_is_omap44xx()) {
44169075
SS		 1671 gpio_bank_count = OMAP34XX_NR_GPIOS;
1672 gpio_bank = gpio_bank_44xx;
44169075 1673 }
5e1c5ff4
TL		 1674#endif
1675 for (i = 0; i < gpio_bank_count; i++) {
1676 int j, gpio_count = 16;
1677
1678 bank = &gpio_bank[i];
5e1c5ff4 1679 spin_lock_init(&bank->lock);
9f7065da
TL		 1680
1681 /* Static mapping, never released */
1682 bank->base = ioremap(bank->pbase, bank_size);
1683 if (!bank->base) {
1684 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1685 continue;
1686 }
1687
e5c56ed3 1688 if (bank_is_mpuio(bank))
7c7095aa 1689 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1690 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1691 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1692 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1693 }
d11ac979 1694 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1695 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1696 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1697 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1698 }
7c006926
AB		 1699 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1700 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1701 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
5e1c5ff4 1702
7c006926 1703 gpio_count = 32; /* 7xx has 32-bit GPIOs */
5e1c5ff4 1704 }
d11ac979 1705
44169075
SS		 1706#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1707 defined(CONFIG_ARCH_OMAP4)
92105bb7 1708 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1709 static const u32 non_wakeup_gpios[] = {
1710 0xe203ffc0, 0x08700040
1711 };
78a1a6d3
SR		 1712 if (cpu_is_omap44xx()) {
1713 __raw_writel(0xffffffff, bank->base +
1714 OMAP4_GPIO_IRQSTATUSCLR0);
1715 __raw_writew(0x0015, bank->base +
1716 OMAP4_GPIO_SYSCONFIG);
1717 __raw_writel(0x00000000, bank->base +
1718 OMAP4_GPIO_DEBOUNCENABLE);
1719 /* Initialize interface clock ungated, module enabled */
1720 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1721 } else {
92105bb7
TL		 1722 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1723 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf 1724 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
cb5793db 1725 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
14f1c3bf
JY		 1726
1727 /* Initialize interface clock ungated, module enabled */
1728 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
78a1a6d3 1729 }
3ac4fa99
JY		 1730 if (i < ARRAY_SIZE(non_wakeup_gpios))
1731 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1732 gpio_count = 32;
1733 }
5e1c5ff4 1734#endif
52e31344
DB		 1735 /* REVISIT eventually switch from OMAP-specific gpio structs
1736 * over to the generic ones
1737 */
3ff164e1
JN		 1738 bank->chip.request = omap_gpio_request;
1739 bank->chip.free = omap_gpio_free;
52e31344
DB		 1740 bank->chip.direction_input = gpio_input;
1741 bank->chip.get = gpio_get;
1742 bank->chip.direction_output = gpio_output;
1743 bank->chip.set = gpio_set;
a007b709 1744 bank->chip.to_irq = gpio_2irq;
52e31344
DB		 1745 if (bank_is_mpuio(bank)) {
1746 bank->chip.label = "mpuio";
69114a47 1747#ifdef CONFIG_ARCH_OMAP16XX
d8f388d8
DB		 1748 bank->chip.dev = &omap_mpuio_device.dev;
1749#endif
52e31344
DB		 1750 bank->chip.base = OMAP_MPUIO(0);
1751 } else {
1752 bank->chip.label = "gpio";
1753 bank->chip.base = gpio;
1754 gpio += gpio_count;
1755 }
1756 bank->chip.ngpio = gpio_count;
1757
1758 gpiochip_add(&bank->chip);
1759
5e1c5ff4
TL		 1760 for (j = bank->virtual_irq_start;
1761 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1762 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1763 set_irq_chip_data(j, bank);
e5c56ed3 1764 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1765 set_irq_chip(j, &mpuio_irq_chip);
1766 else
1767 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1768 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1769 set_irq_flags(j, IRQF_VALID);
1770 }
1771 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1772 set_irq_data(bank->irq, bank);
89db9482 1773
44169075 1774 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
89db9482
JH		 1775 sprintf(clk_name, "gpio%d_dbck", i + 1);
1776 bank->dbck = clk_get(NULL, clk_name);
1777 if (IS_ERR(bank->dbck))
1778 printk(KERN_ERR "Could not get %s\n", clk_name);
1779 }
5e1c5ff4
TL		 1780 }
1781
1782 /* Enable system clock for GPIO module.
1783 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1784 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1785 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1786
14f1c3bf
JY		 1787 /* Enable autoidle for the OCP interface */
1788 if (cpu_is_omap24xx())
1789 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1790 if (cpu_is_omap34xx())
1791 omap_writel(1 << 0, 0x48306814);
d11ac979 1792
9f7065da
TL		 1793 omap_gpio_show_rev();
1794
5e1c5ff4
TL		 1795 return 0;
1796}
1797
44169075
SS		 1798#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1799 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 1800static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1801{
1802 int i;
1803
5492fb1a 1804 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1805 return 0;
1806
1807 for (i = 0; i < gpio_bank_count; i++) {
1808 struct gpio_bank *bank = &gpio_bank[i];
1809 void __iomem *wake_status;
1810 void __iomem *wake_clear;
1811 void __iomem *wake_set;
a6472533 1812 unsigned long flags;
92105bb7
TL		 1813
1814 switch (bank->method) {
e5c56ed3 1815#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1816 case METHOD_GPIO_1610:
1817 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1818 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1819 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1820 break;
e5c56ed3 1821#endif
78a1a6d3 1822#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1823 case METHOD_GPIO_24XX:
723fdb78 1824 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1825 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1826 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1827 break;
78a1a6d3
SR		 1828#endif
1829#ifdef CONFIG_ARCH_OMAP4
1830 case METHOD_GPIO_24XX:
1831 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1832 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1833 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1834 break;
e5c56ed3 1835#endif
92105bb7
TL		 1836 default:
1837 continue;
1838 }
1839
a6472533 1840 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1841 bank->saved_wakeup = __raw_readl(wake_status);
1842 __raw_writel(0xffffffff, wake_clear);
1843 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1844 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1845 }
1846
1847 return 0;
1848}
1849
1850static int omap_gpio_resume(struct sys_device *dev)
1851{
1852 int i;
1853
723fdb78 1854 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1855 return 0;
1856
1857 for (i = 0; i < gpio_bank_count; i++) {
1858 struct gpio_bank *bank = &gpio_bank[i];
1859 void __iomem *wake_clear;
1860 void __iomem *wake_set;
a6472533 1861 unsigned long flags;
92105bb7
TL		 1862
1863 switch (bank->method) {
e5c56ed3 1864#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1865 case METHOD_GPIO_1610:
1866 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1867 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1868 break;
e5c56ed3 1869#endif
78a1a6d3 1870#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1871 case METHOD_GPIO_24XX:
0d9356cb
TL		 1872 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1873 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1874 break;
78a1a6d3
SR		 1875#endif
1876#ifdef CONFIG_ARCH_OMAP4
1877 case METHOD_GPIO_24XX:
1878 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1879 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1880 break;
e5c56ed3 1881#endif
92105bb7
TL		 1882 default:
1883 continue;
1884 }
1885
a6472533 1886 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1887 __raw_writel(0xffffffff, wake_clear);
1888 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1889 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1890 }
1891
1892 return 0;
1893}
1894
1895static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1896 .name = "gpio",
92105bb7
TL		 1897 .suspend = omap_gpio_suspend,
1898 .resume = omap_gpio_resume,
1899};
1900
1901static struct sys_device omap_gpio_device = {
1902 .id = 0,
1903 .cls = &omap_gpio_sysclass,
1904};
3ac4fa99
JY		 1905
1906#endif
1907
44169075
SS		 1908#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1909 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 1910
1911static int workaround_enabled;
1912
1913void omap2_gpio_prepare_for_retention(void)
1914{
1915 int i, c = 0;
1916
1917 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1918 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1919 for (i = 0; i < gpio_bank_count; i++) {
1920 struct gpio_bank *bank = &gpio_bank[i];
1921 u32 l1, l2;
1922
1923 if (!(bank->enabled_non_wakeup_gpios))
1924 continue;
78a1a6d3 1925#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1926 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1927 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1928 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
78a1a6d3
SR		 1929#endif
1930#ifdef CONFIG_ARCH_OMAP4
1931 bank->saved_datain = __raw_readl(bank->base +
1932 OMAP4_GPIO_DATAIN);
1933 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
1934 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
5492fb1a 1935#endif
3ac4fa99
JY		 1936 bank->saved_fallingdetect = l1;
1937 bank->saved_risingdetect = l2;
1938 l1 &= ~bank->enabled_non_wakeup_gpios;
1939 l2 &= ~bank->enabled_non_wakeup_gpios;
78a1a6d3 1940#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1941 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1942 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
78a1a6d3
SR		 1943#endif
1944#ifdef CONFIG_ARCH_OMAP4
1945 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1946 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
5492fb1a 1947#endif
3ac4fa99
JY		 1948 c++;
1949 }
1950 if (!c) {
1951 workaround_enabled = 0;
1952 return;
1953 }
1954 workaround_enabled = 1;
1955}
1956
1957void omap2_gpio_resume_after_retention(void)
1958{
1959 int i;
1960
1961 if (!workaround_enabled)
1962 return;
1963 for (i = 0; i < gpio_bank_count; i++) {
1964 struct gpio_bank *bank = &gpio_bank[i];
82dbb9d3 1965 u32 l, gen, gen0, gen1;
3ac4fa99
JY		 1966
1967 if (!(bank->enabled_non_wakeup_gpios))
1968 continue;
78a1a6d3 1969#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1970 __raw_writel(bank->saved_fallingdetect,
1971 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1972 __raw_writel(bank->saved_risingdetect,
1973 bank->base + OMAP24XX_GPIO_RISINGDETECT);
78a1a6d3
SR		 1974 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1975#endif
1976#ifdef CONFIG_ARCH_OMAP4
1977 __raw_writel(bank->saved_fallingdetect,
1978 bank->base + OMAP4_GPIO_FALLINGDETECT);
1979 __raw_writel(bank->saved_risingdetect,
1980 bank->base + OMAP4_GPIO_RISINGDETECT);
1981 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
5492fb1a 1982#endif
3ac4fa99
JY		 1983 /* Check if any of the non-wakeup interrupt GPIOs have changed
1984 * state. If so, generate an IRQ by software. This is
1985 * horribly racy, but it's the best we can do to work around
1986 * this silicon bug. */
3ac4fa99
JY		 1987 l ^= bank->saved_datain;
1988 l &= bank->non_wakeup_gpios;
82dbb9d3
EN		 1989
1990 /*
1991 * No need to generate IRQs for the rising edge for gpio IRQs
1992 * configured with falling edge only; and vice versa.
1993 */
1994 gen0 = l & bank->saved_fallingdetect;
1995 gen0 &= bank->saved_datain;
1996
1997 gen1 = l & bank->saved_risingdetect;
1998 gen1 &= ~(bank->saved_datain);
1999
2000 /* FIXME: Consider GPIO IRQs with level detections properly! */
2001 gen = l & (~(bank->saved_fallingdetect) &
2002 ~(bank->saved_risingdetect));
2003 /* Consider all GPIO IRQs needed to be updated */
2004 gen |= gen0 | gen1;
2005
2006 if (gen) {
3ac4fa99 2007 u32 old0, old1;
78a1a6d3 2008#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 2009 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2010 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
82dbb9d3
EN		 2011 __raw_writel(old0 | gen, bank->base +
2012 OMAP24XX_GPIO_LEVELDETECT0);
2013 __raw_writel(old1 | gen, bank->base +
2014 OMAP24XX_GPIO_LEVELDETECT1);
3ac4fa99
JY		 2015 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2016 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
78a1a6d3
SR		 2017#endif
2018#ifdef CONFIG_ARCH_OMAP4
2019 old0 = __raw_readl(bank->base +
2020 OMAP4_GPIO_LEVELDETECT0);
2021 old1 = __raw_readl(bank->base +
2022 OMAP4_GPIO_LEVELDETECT1);
2023 __raw_writel(old0 | l, bank->base +
2024 OMAP4_GPIO_LEVELDETECT0);
2025 __raw_writel(old1 | l, bank->base +
2026 OMAP4_GPIO_LEVELDETECT1);
2027 __raw_writel(old0, bank->base +
2028 OMAP4_GPIO_LEVELDETECT0);
2029 __raw_writel(old1, bank->base +
2030 OMAP4_GPIO_LEVELDETECT1);
5492fb1a 2031#endif
3ac4fa99
JY		 2032 }
2033 }
2034
2035}
2036
92105bb7
TL		 2037#endif
2038
5e1c5ff4
TL		 2039/*
2040 * This may get called early from board specific init
1a8bfa1e 2041 * for boards that have interrupts routed via FPGA.
5e1c5ff4 2042 */
277d58ef 2043int __init omap_gpio_init(void)
5e1c5ff4
TL		 2044{
2045 if (!initialized)
2046 return _omap_gpio_init();
2047 else
2048 return 0;
2049}
2050
92105bb7
TL		 2051static int __init omap_gpio_sysinit(void)
2052{
2053 int ret = 0;
2054
2055 if (!initialized)
2056 ret = _omap_gpio_init();
2057
11a78b79
DB		 2058 mpuio_init();
2059
44169075
SS		 2060#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2061 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
5492fb1a 2062 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 2063 if (ret == 0) {
2064 ret = sysdev_class_register(&omap_gpio_sysclass);
2065 if (ret == 0)
2066 ret = sysdev_register(&omap_gpio_device);
2067 }
2068 }
2069#endif
2070
2071 return ret;
2072}
2073
92105bb7 2074arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 2075
2076
2077#ifdef CONFIG_DEBUG_FS
2078
2079#include <linux/debugfs.h>
2080#include <linux/seq_file.h>
2081
b9772a22
DB		 2082static int dbg_gpio_show(struct seq_file *s, void *unused)
2083{
2084 unsigned i, j, gpio;
2085
2086 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2087 struct gpio_bank *bank = gpio_bank + i;
2088 unsigned bankwidth = 16;
2089 u32 mask = 1;
2090
e5c56ed3 2091 if (bank_is_mpuio(bank))
b9772a22 2092 gpio = OMAP_MPUIO(0);
b718aa81 2093 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
b9772a22
DB		 2094 bankwidth = 32;
2095
2096 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2097 unsigned irq, value, is_in, irqstat;
52e31344 2098 const char *label;
b9772a22 2099
52e31344
DB		 2100 label = gpiochip_is_requested(&bank->chip, j);
2101 if (!label)
b9772a22
DB		 2102 continue;
2103
2104 irq = bank->virtual_irq_start + j;
0b84b5ca 2105 value = gpio_get_value(gpio);
b9772a22
DB		 2106 is_in = gpio_is_input(bank, mask);
2107
e5c56ed3 2108 if (bank_is_mpuio(bank))
52e31344 2109 seq_printf(s, "MPUIO %2d ", j);
b9772a22 2110 else
52e31344 2111 seq_printf(s, "GPIO %3d ", gpio);
21c867f1 2112 seq_printf(s, "(%-20.20s): %s %s",
52e31344 2113 label,
b9772a22
DB		 2114 is_in ? "in " : "out",
2115 value ? "hi" : "lo");
2116
52e31344
DB		 2117/* FIXME for at least omap2, show pullup/pulldown state */
2118
b9772a22 2119 irqstat = irq_desc[irq].status;
3a26e331 2120#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
44169075 2121 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
b9772a22
DB		 2122 if (is_in && ((bank->suspend_wakeup & mask)
2123 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2124 char *trigger = NULL;
2125
2126 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2127 case IRQ_TYPE_EDGE_FALLING:
2128 trigger = "falling";
2129 break;
2130 case IRQ_TYPE_EDGE_RISING:
2131 trigger = "rising";
2132 break;
2133 case IRQ_TYPE_EDGE_BOTH:
2134 trigger = "bothedge";
2135 break;
2136 case IRQ_TYPE_LEVEL_LOW:
2137 trigger = "low";
2138 break;
2139 case IRQ_TYPE_LEVEL_HIGH:
2140 trigger = "high";
2141 break;
2142 case IRQ_TYPE_NONE:
52e31344 2143 trigger = "(?)";
b9772a22
DB		 2144 break;
2145 }
52e31344 2146 seq_printf(s, ", irq-%d %-8s%s",
b9772a22
DB		 2147 irq, trigger,
2148 (bank->suspend_wakeup & mask)
2149 ? " wakeup" : "");
2150 }
3a26e331 2151#endif
b9772a22
DB		 2152 seq_printf(s, "\n");
2153 }
2154
e5c56ed3 2155 if (bank_is_mpuio(bank)) {
b9772a22
DB		 2156 seq_printf(s, "\n");
2157 gpio = 0;
2158 }
2159 }
2160 return 0;
2161}
2162
2163static int dbg_gpio_open(struct inode *inode, struct file *file)
2164{
e5c56ed3 2165 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 2166}
2167
2168static const struct file_operations debug_fops = {
2169 .open = dbg_gpio_open,
2170 .read = seq_read,
2171 .llseek = seq_lseek,
2172 .release = single_release,
2173};
2174
2175static int __init omap_gpio_debuginit(void)
2176{
e5c56ed3
DB		 2177 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2178 NULL, NULL, &debug_fops);
b9772a22
DB		 2179 return 0;
2180}
2181late_initcall(omap_gpio_debuginit);
2182#endif
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