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ARM: OMAP4: Add UART4 support
[net-next-2.6.git] / arch / arm / plat-omap / gpio.c
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5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
5e1c5ff4
TL		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
5e1c5ff4
TL		 17#include <linux/init.h>
18#include <linux/module.h>
5e1c5ff4 19#include <linux/interrupt.h>
92105bb7
TL		 20#include <linux/sysdev.h>
21#include <linux/err.h>
f8ce2547 22#include <linux/clk.h>
fced80c7 23#include <linux/io.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4
TL		 31/*
32 * OMAP1510 GPIO registers
33 */
7c7095aa 34#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
5e1c5ff4
TL		 35#define OMAP1510_GPIO_DATA_INPUT 0x00
36#define OMAP1510_GPIO_DATA_OUTPUT 0x04
37#define OMAP1510_GPIO_DIR_CONTROL 0x08
38#define OMAP1510_GPIO_INT_CONTROL 0x0c
39#define OMAP1510_GPIO_INT_MASK 0x10
40#define OMAP1510_GPIO_INT_STATUS 0x14
41#define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43#define OMAP1510_IH_GPIO_BASE 64
44
45/*
46 * OMAP1610 specific GPIO registers
47 */
7c7095aa
RK		 48#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
49#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
50#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
51#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
5e1c5ff4
TL		 52#define OMAP1610_GPIO_REVISION 0x0000
53#define OMAP1610_GPIO_SYSCONFIG 0x0010
54#define OMAP1610_GPIO_SYSSTATUS 0x0014
55#define OMAP1610_GPIO_IRQSTATUS1 0x0018
56#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 57#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 58#define OMAP1610_GPIO_DATAIN 0x002c
59#define OMAP1610_GPIO_DATAOUT 0x0030
60#define OMAP1610_GPIO_DIRECTION 0x0034
61#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 64#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 67#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70/*
71 * OMAP730 specific GPIO registers
72 */
7c7095aa
RK		 73#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
74#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
75#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
76#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
77#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
78#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
5e1c5ff4
TL		 79#define OMAP730_GPIO_DATA_INPUT 0x00
80#define OMAP730_GPIO_DATA_OUTPUT 0x04
81#define OMAP730_GPIO_DIR_CONTROL 0x08
82#define OMAP730_GPIO_INT_CONTROL 0x0c
83#define OMAP730_GPIO_INT_MASK 0x10
84#define OMAP730_GPIO_INT_STATUS 0x14
85
56739a69
ZM		 86/*
87 * OMAP850 specific GPIO registers
88 */
89#define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
90#define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
91#define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
92#define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
93#define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
94#define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
95#define OMAP850_GPIO_DATA_INPUT 0x00
96#define OMAP850_GPIO_DATA_OUTPUT 0x04
97#define OMAP850_GPIO_DIR_CONTROL 0x08
98#define OMAP850_GPIO_INT_CONTROL 0x0c
99#define OMAP850_GPIO_INT_MASK 0x10
100#define OMAP850_GPIO_INT_STATUS 0x14
101
92105bb7
TL		 102/*
103 * omap24xx specific GPIO registers
104 */
7c7095aa
RK		 105#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
106#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
107#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
108#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
56a25641 109
7c7095aa
RK		 110#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
111#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
112#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
113#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
114#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
56a25641 115
92105bb7
TL		 116#define OMAP24XX_GPIO_REVISION 0x0000
117#define OMAP24XX_GPIO_SYSCONFIG 0x0010
118#define OMAP24XX_GPIO_SYSSTATUS 0x0014
119#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 120#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
121#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 122#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 123#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 124#define OMAP24XX_GPIO_CTRL 0x0030
125#define OMAP24XX_GPIO_OE 0x0034
126#define OMAP24XX_GPIO_DATAIN 0x0038
127#define OMAP24XX_GPIO_DATAOUT 0x003c
128#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
129#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
130#define OMAP24XX_GPIO_RISINGDETECT 0x0048
131#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 132#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
133#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 134#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
135#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
136#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
137#define OMAP24XX_GPIO_SETWKUENA 0x0084
138#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
139#define OMAP24XX_GPIO_SETDATAOUT 0x0094
140
5492fb1a
SMK		 141/*
142 * omap34xx specific GPIO registers
143 */
144
7c7095aa
RK		 145#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
146#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
147#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
148#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
149#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
150#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
5492fb1a 151
44169075
SS		 152/*
153 * OMAP44XX specific GPIO registers
154 */
155#define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000)
156#define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000)
157#define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000)
158#define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000)
159#define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000)
160#define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000)
161
7c7095aa 162#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
5492fb1a 163
5e1c5ff4 164struct gpio_bank {
92105bb7 165 void __iomem *base;
5e1c5ff4
TL		 166 u16 irq;
167 u16 virtual_irq_start;
92105bb7 168 int method;
44169075
SS		 169#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
170 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 171 u32 suspend_wakeup;
172 u32 saved_wakeup;
3ac4fa99 173#endif
44169075
SS		 174#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
175 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 176 u32 non_wakeup_gpios;
177 u32 enabled_non_wakeup_gpios;
178
179 u32 saved_datain;
180 u32 saved_fallingdetect;
181 u32 saved_risingdetect;
182#endif
b144ff6f 183 u32 level_mask;
5e1c5ff4 184 spinlock_t lock;
52e31344 185 struct gpio_chip chip;
89db9482 186 struct clk *dbck;
5e1c5ff4
TL		 187};
188
189#define METHOD_MPUIO 0
190#define METHOD_GPIO_1510 1
191#define METHOD_GPIO_1610 2
192#define METHOD_GPIO_730 3
56739a69
ZM		 193#define METHOD_GPIO_850 4
194#define METHOD_GPIO_24XX 5
5e1c5ff4 195
92105bb7 196#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 197static struct gpio_bank gpio_bank_1610[5] = {
7c7095aa 198 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
5e1c5ff4
TL		 199 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
200 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
201 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
202 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
203};
204#endif
205
1a8bfa1e 206#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 207static struct gpio_bank gpio_bank_1510[2] = {
7c7095aa 208 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
5e1c5ff4
TL		 209 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
210};
211#endif
212
213#ifdef CONFIG_ARCH_OMAP730
214static struct gpio_bank gpio_bank_730[7] = {
7c7095aa 215 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
5e1c5ff4
TL		 216 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
217 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
218 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
219 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
220 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
221 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
222};
223#endif
224
56739a69
ZM		 225#ifdef CONFIG_ARCH_OMAP850
226static struct gpio_bank gpio_bank_850[7] = {
227 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
228 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
229 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
230 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
231 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
232 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
233 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
234};
235#endif
236
237
92105bb7 238#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 239
240static struct gpio_bank gpio_bank_242x[4] = {
241 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
242 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
243 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
244 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
92105bb7 245};
56a25641
SMK		 246
247static struct gpio_bank gpio_bank_243x[5] = {
248 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
249 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
250 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
251 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
252 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
253};
254
92105bb7
TL		 255#endif
256
5492fb1a
SMK		 257#ifdef CONFIG_ARCH_OMAP34XX
258static struct gpio_bank gpio_bank_34xx[6] = {
259 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
260 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
261 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
262 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
263 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
264 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
265};
266
267#endif
268
44169075
SS		 269#ifdef CONFIG_ARCH_OMAP4
270static struct gpio_bank gpio_bank_44xx[6] = {
271 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
272 METHOD_GPIO_24XX },
273 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \
274 METHOD_GPIO_24XX },
275 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \
276 METHOD_GPIO_24XX },
277 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \
278 METHOD_GPIO_24XX },
279 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
280 METHOD_GPIO_24XX },
281 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
282 METHOD_GPIO_24XX },
283};
284
285#endif
286
5e1c5ff4
TL		 287static struct gpio_bank *gpio_bank;
288static int gpio_bank_count;
289
290static inline struct gpio_bank *get_gpio_bank(int gpio)
291{
6e60e79a 292 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 293 if (OMAP_GPIO_IS_MPUIO(gpio))
294 return &gpio_bank[0];
295 return &gpio_bank[1];
296 }
5e1c5ff4
TL		 297 if (cpu_is_omap16xx()) {
298 if (OMAP_GPIO_IS_MPUIO(gpio))
299 return &gpio_bank[0];
300 return &gpio_bank[1 + (gpio >> 4)];
301 }
56739a69 302 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 303 if (OMAP_GPIO_IS_MPUIO(gpio))
304 return &gpio_bank[0];
305 return &gpio_bank[1 + (gpio >> 5)];
306 }
92105bb7
TL		 307 if (cpu_is_omap24xx())
308 return &gpio_bank[gpio >> 5];
44169075 309 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 310 return &gpio_bank[gpio >> 5];
e031ab23
DB		 311 BUG();
312 return NULL;
5e1c5ff4
TL		 313}
314
315static inline int get_gpio_index(int gpio)
316{
56739a69 317 if (cpu_is_omap7xx())
5e1c5ff4 318 return gpio & 0x1f;
92105bb7
TL		 319 if (cpu_is_omap24xx())
320 return gpio & 0x1f;
44169075 321 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 322 return gpio & 0x1f;
92105bb7 323 return gpio & 0x0f;
5e1c5ff4
TL		 324}
325
326static inline int gpio_valid(int gpio)
327{
328 if (gpio < 0)
329 return -1;
d11ac979 330 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 331 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 332 return -1;
333 return 0;
334 }
6e60e79a 335 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 336 return 0;
5e1c5ff4
TL		 337 if ((cpu_is_omap16xx()) && gpio < 64)
338 return 0;
56739a69 339 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 340 return 0;
92105bb7
TL		 341 if (cpu_is_omap24xx() && gpio < 128)
342 return 0;
44169075 343 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 344 return 0;
5e1c5ff4
TL		 345 return -1;
346}
347
348static int check_gpio(int gpio)
349{
350 if (unlikely(gpio_valid(gpio)) < 0) {
351 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
352 dump_stack();
353 return -1;
354 }
355 return 0;
356}
357
358static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
359{
92105bb7 360 void __iomem *reg = bank->base;
5e1c5ff4
TL		 361 u32 l;
362
363 switch (bank->method) {
e5c56ed3 364#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 365 case METHOD_MPUIO:
366 reg += OMAP_MPUIO_IO_CNTL;
367 break;
e5c56ed3
DB		 368#endif
369#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 370 case METHOD_GPIO_1510:
371 reg += OMAP1510_GPIO_DIR_CONTROL;
372 break;
e5c56ed3
DB		 373#endif
374#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 375 case METHOD_GPIO_1610:
376 reg += OMAP1610_GPIO_DIRECTION;
377 break;
e5c56ed3
DB		 378#endif
379#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 380 case METHOD_GPIO_730:
381 reg += OMAP730_GPIO_DIR_CONTROL;
382 break;
e5c56ed3 383#endif
56739a69
ZM		 384#ifdef CONFIG_ARCH_OMAP850
385 case METHOD_GPIO_850:
386 reg += OMAP850_GPIO_DIR_CONTROL;
387 break;
388#endif
44169075
SS		 389#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
390 defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 391 case METHOD_GPIO_24XX:
392 reg += OMAP24XX_GPIO_OE;
393 break;
e5c56ed3
DB		 394#endif
395 default:
396 WARN_ON(1);
397 return;
5e1c5ff4
TL		 398 }
399 l = __raw_readl(reg);
400 if (is_input)
401 l |= 1 << gpio;
402 else
403 l &= ~(1 << gpio);
404 __raw_writel(l, reg);
405}
406
5e1c5ff4
TL		 407static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
408{
92105bb7 409 void __iomem *reg = bank->base;
5e1c5ff4
TL		 410 u32 l = 0;
411
412 switch (bank->method) {
e5c56ed3 413#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 414 case METHOD_MPUIO:
415 reg += OMAP_MPUIO_OUTPUT;
416 l = __raw_readl(reg);
417 if (enable)
418 l |= 1 << gpio;
419 else
420 l &= ~(1 << gpio);
421 break;
e5c56ed3
DB		 422#endif
423#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 424 case METHOD_GPIO_1510:
425 reg += OMAP1510_GPIO_DATA_OUTPUT;
426 l = __raw_readl(reg);
427 if (enable)
428 l |= 1 << gpio;
429 else
430 l &= ~(1 << gpio);
431 break;
e5c56ed3
DB		 432#endif
433#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 434 case METHOD_GPIO_1610:
435 if (enable)
436 reg += OMAP1610_GPIO_SET_DATAOUT;
437 else
438 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
439 l = 1 << gpio;
440 break;
e5c56ed3
DB		 441#endif
442#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 443 case METHOD_GPIO_730:
444 reg += OMAP730_GPIO_DATA_OUTPUT;
445 l = __raw_readl(reg);
446 if (enable)
447 l |= 1 << gpio;
448 else
449 l &= ~(1 << gpio);
450 break;
e5c56ed3 451#endif
56739a69
ZM		 452#ifdef CONFIG_ARCH_OMAP850
453 case METHOD_GPIO_850:
454 reg += OMAP850_GPIO_DATA_OUTPUT;
455 l = __raw_readl(reg);
456 if (enable)
457 l |= 1 << gpio;
458 else
459 l &= ~(1 << gpio);
460 break;
461#endif
44169075
SS		 462#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
463 defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 464 case METHOD_GPIO_24XX:
465 if (enable)
466 reg += OMAP24XX_GPIO_SETDATAOUT;
467 else
468 reg += OMAP24XX_GPIO_CLEARDATAOUT;
469 l = 1 << gpio;
470 break;
e5c56ed3 471#endif
5e1c5ff4 472 default:
e5c56ed3 473 WARN_ON(1);
5e1c5ff4
TL		 474 return;
475 }
476 __raw_writel(l, reg);
477}
478
0b84b5ca 479static int __omap_get_gpio_datain(int gpio)
5e1c5ff4
TL		 480{
481 struct gpio_bank *bank;
92105bb7 482 void __iomem *reg;
5e1c5ff4
TL		 483
484 if (check_gpio(gpio) < 0)
e5c56ed3 485 return -EINVAL;
5e1c5ff4
TL		 486 bank = get_gpio_bank(gpio);
487 reg = bank->base;
488 switch (bank->method) {
e5c56ed3 489#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 490 case METHOD_MPUIO:
491 reg += OMAP_MPUIO_INPUT_LATCH;
492 break;
e5c56ed3
DB		 493#endif
494#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 495 case METHOD_GPIO_1510:
496 reg += OMAP1510_GPIO_DATA_INPUT;
497 break;
e5c56ed3
DB		 498#endif
499#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 500 case METHOD_GPIO_1610:
501 reg += OMAP1610_GPIO_DATAIN;
502 break;
e5c56ed3
DB		 503#endif
504#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 505 case METHOD_GPIO_730:
506 reg += OMAP730_GPIO_DATA_INPUT;
507 break;
e5c56ed3 508#endif
56739a69
ZM		 509#ifdef CONFIG_ARCH_OMAP850
510 case METHOD_GPIO_850:
511 reg += OMAP850_GPIO_DATA_INPUT;
512 break;
513#endif
44169075
SS		 514#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
515 defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 516 case METHOD_GPIO_24XX:
517 reg += OMAP24XX_GPIO_DATAIN;
518 break;
e5c56ed3 519#endif
5e1c5ff4 520 default:
e5c56ed3 521 return -EINVAL;
5e1c5ff4 522 }
92105bb7
TL		 523 return (__raw_readl(reg)
524 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 525}
526
92105bb7
TL		 527#define MOD_REG_BIT(reg, bit_mask, set) \
528do { \
529 int l = __raw_readl(base + reg); \
530 if (set) l |= bit_mask; \
531 else l &= ~bit_mask; \
532 __raw_writel(l, base + reg); \
533} while(0)
534
5eb3bb9c
KH		 535void omap_set_gpio_debounce(int gpio, int enable)
536{
537 struct gpio_bank *bank;
538 void __iomem *reg;
e031ab23 539 unsigned long flags;
5eb3bb9c
KH		 540 u32 val, l = 1 << get_gpio_index(gpio);
541
542 if (cpu_class_is_omap1())
543 return;
544
545 bank = get_gpio_bank(gpio);
546 reg = bank->base;
5eb3bb9c 547 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
e031ab23
DB		 548
549 spin_lock_irqsave(&bank->lock, flags);
5eb3bb9c
KH		 550 val = __raw_readl(reg);
551
89db9482 552 if (enable && !(val & l))
5eb3bb9c 553 val |= l;
e031ab23 554 else if (!enable && (val & l))
5eb3bb9c 555 val &= ~l;
89db9482 556 else
e031ab23 557 goto done;
89db9482 558
44169075 559 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
e031ab23
DB		 560 if (enable)
561 clk_enable(bank->dbck);
562 else
563 clk_disable(bank->dbck);
564 }
5eb3bb9c
KH		 565
566 __raw_writel(val, reg);
e031ab23
DB		 567done:
568 spin_unlock_irqrestore(&bank->lock, flags);
5eb3bb9c
KH		 569}
570EXPORT_SYMBOL(omap_set_gpio_debounce);
571
572void omap_set_gpio_debounce_time(int gpio, int enc_time)
573{
574 struct gpio_bank *bank;
575 void __iomem *reg;
576
577 if (cpu_class_is_omap1())
578 return;
579
580 bank = get_gpio_bank(gpio);
581 reg = bank->base;
582
583 enc_time &= 0xff;
584 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
585 __raw_writel(enc_time, reg);
586}
587EXPORT_SYMBOL(omap_set_gpio_debounce_time);
588
44169075
SS		 589#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
590 defined(CONFIG_ARCH_OMAP4)
5eb3bb9c
KH		 591static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
592 int trigger)
5e1c5ff4 593{
3ac4fa99 594 void __iomem *base = bank->base;
92105bb7
TL		 595 u32 gpio_bit = 1 << gpio;
596
597 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
6cab4860 598 trigger & IRQ_TYPE_LEVEL_LOW);
92105bb7 599 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
6cab4860 600 trigger & IRQ_TYPE_LEVEL_HIGH);
92105bb7 601 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
6cab4860 602 trigger & IRQ_TYPE_EDGE_RISING);
92105bb7 603 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
6cab4860 604 trigger & IRQ_TYPE_EDGE_FALLING);
5eb3bb9c 605
3ac4fa99
JY		 606 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
607 if (trigger != 0)
5eb3bb9c
KH		 608 __raw_writel(1 << gpio, bank->base
609 + OMAP24XX_GPIO_SETWKUENA);
3ac4fa99 610 else
5eb3bb9c
KH		 611 __raw_writel(1 << gpio, bank->base
612 + OMAP24XX_GPIO_CLEARWKUENA);
3ac4fa99
JY		 613 } else {
614 if (trigger != 0)
615 bank->enabled_non_wakeup_gpios |= gpio_bit;
616 else
617 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
618 }
5eb3bb9c 619
b144ff6f
KH		 620 bank->level_mask =
621 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
622 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
92105bb7 623}
3ac4fa99 624#endif
92105bb7
TL		 625
626static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
627{
628 void __iomem *reg = bank->base;
629 u32 l = 0;
5e1c5ff4
TL		 630
631 switch (bank->method) {
e5c56ed3 632#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 633 case METHOD_MPUIO:
634 reg += OMAP_MPUIO_GPIO_INT_EDGE;
635 l = __raw_readl(reg);
6cab4860 636 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 637 l |= 1 << gpio;
6cab4860 638 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 639 l &= ~(1 << gpio);
92105bb7
TL		 640 else
641 goto bad;
5e1c5ff4 642 break;
e5c56ed3
DB		 643#endif
644#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 645 case METHOD_GPIO_1510:
646 reg += OMAP1510_GPIO_INT_CONTROL;
647 l = __raw_readl(reg);
6cab4860 648 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 649 l |= 1 << gpio;
6cab4860 650 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 651 l &= ~(1 << gpio);
92105bb7
TL		 652 else
653 goto bad;
5e1c5ff4 654 break;
e5c56ed3 655#endif
3ac4fa99 656#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 657 case METHOD_GPIO_1610:
5e1c5ff4
TL		 658 if (gpio & 0x08)
659 reg += OMAP1610_GPIO_EDGE_CTRL2;
660 else
661 reg += OMAP1610_GPIO_EDGE_CTRL1;
662 gpio &= 0x07;
663 l = __raw_readl(reg);
664 l &= ~(3 << (gpio << 1));
6cab4860 665 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 666 l |= 2 << (gpio << 1);
6cab4860 667 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 668 l |= 1 << (gpio << 1);
3ac4fa99
JY		 669 if (trigger)
670 /* Enable wake-up during idle for dynamic tick */
671 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
672 else
673 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 674 break;
3ac4fa99
JY		 675#endif
676#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 677 case METHOD_GPIO_730:
678 reg += OMAP730_GPIO_INT_CONTROL;
679 l = __raw_readl(reg);
6cab4860 680 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 681 l |= 1 << gpio;
6cab4860 682 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 683 l &= ~(1 << gpio);
92105bb7
TL		 684 else
685 goto bad;
686 break;
3ac4fa99 687#endif
56739a69
ZM		 688#ifdef CONFIG_ARCH_OMAP850
689 case METHOD_GPIO_850:
690 reg += OMAP850_GPIO_INT_CONTROL;
691 l = __raw_readl(reg);
692 if (trigger & IRQ_TYPE_EDGE_RISING)
693 l |= 1 << gpio;
694 else if (trigger & IRQ_TYPE_EDGE_FALLING)
695 l &= ~(1 << gpio);
696 else
697 goto bad;
698 break;
699#endif
44169075
SS		 700#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
701 defined(CONFIG_ARCH_OMAP4)
92105bb7 702 case METHOD_GPIO_24XX:
3ac4fa99 703 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 704 break;
3ac4fa99 705#endif
5e1c5ff4 706 default:
92105bb7 707 goto bad;
5e1c5ff4 708 }
92105bb7
TL		 709 __raw_writel(l, reg);
710 return 0;
711bad:
712 return -EINVAL;
5e1c5ff4
TL		 713}
714
92105bb7 715static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 716{
717 struct gpio_bank *bank;
92105bb7
TL		 718 unsigned gpio;
719 int retval;
a6472533 720 unsigned long flags;
92105bb7 721
5492fb1a 722 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 723 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
724 else
725 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 726
727 if (check_gpio(gpio) < 0)
92105bb7
TL		 728 return -EINVAL;
729
e5c56ed3 730 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 731 return -EINVAL;
e5c56ed3
DB		 732
733 /* OMAP1 allows only only edge triggering */
5492fb1a 734 if (!cpu_class_is_omap2()
e5c56ed3 735 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 736 return -EINVAL;
737
58781016 738 bank = get_irq_chip_data(irq);
a6472533 739 spin_lock_irqsave(&bank->lock, flags);
92105bb7 740 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 741 if (retval == 0) {
742 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
743 irq_desc[irq].status |= type;
744 }
a6472533 745 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 746
747 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
748 __set_irq_handler_unlocked(irq, handle_level_irq);
749 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
750 __set_irq_handler_unlocked(irq, handle_edge_irq);
751
92105bb7 752 return retval;
5e1c5ff4
TL		 753}
754
755static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
756{
92105bb7 757 void __iomem *reg = bank->base;
5e1c5ff4
TL		 758
759 switch (bank->method) {
e5c56ed3 760#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 761 case METHOD_MPUIO:
762 /* MPUIO irqstatus is reset by reading the status register,
763 * so do nothing here */
764 return;
e5c56ed3
DB		 765#endif
766#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 767 case METHOD_GPIO_1510:
768 reg += OMAP1510_GPIO_INT_STATUS;
769 break;
e5c56ed3
DB		 770#endif
771#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 772 case METHOD_GPIO_1610:
773 reg += OMAP1610_GPIO_IRQSTATUS1;
774 break;
e5c56ed3
DB		 775#endif
776#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 777 case METHOD_GPIO_730:
778 reg += OMAP730_GPIO_INT_STATUS;
779 break;
e5c56ed3 780#endif
56739a69
ZM		 781#ifdef CONFIG_ARCH_OMAP850
782 case METHOD_GPIO_850:
783 reg += OMAP850_GPIO_INT_STATUS;
784 break;
785#endif
44169075
SS		 786#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
787 defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 788 case METHOD_GPIO_24XX:
789 reg += OMAP24XX_GPIO_IRQSTATUS1;
790 break;
e5c56ed3 791#endif
5e1c5ff4 792 default:
e5c56ed3 793 WARN_ON(1);
5e1c5ff4
TL		 794 return;
795 }
796 __raw_writel(gpio_mask, reg);
bee7930f
HD		 797
798 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a 799#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
bedfd154 800 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
5492fb1a 801 if (cpu_is_omap24xx() || cpu_is_omap34xx())
bedfd154
RQ		 802 __raw_writel(gpio_mask, reg);
803
804 /* Flush posted write for the irq status to avoid spurious interrupts */
805 __raw_readl(reg);
5492fb1a 806#endif
5e1c5ff4
TL		 807}
808
809static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
810{
811 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
812}
813
ea6dedd7
ID		 814static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
815{
816 void __iomem *reg = bank->base;
99c47707
ID		 817 int inv = 0;
818 u32 l;
819 u32 mask;
ea6dedd7
ID		 820
821 switch (bank->method) {
e5c56ed3 822#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 823 case METHOD_MPUIO:
824 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 825 mask = 0xffff;
826 inv = 1;
ea6dedd7 827 break;
e5c56ed3
DB		 828#endif
829#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 830 case METHOD_GPIO_1510:
831 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 832 mask = 0xffff;
833 inv = 1;
ea6dedd7 834 break;
e5c56ed3
DB		 835#endif
836#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 837 case METHOD_GPIO_1610:
838 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 839 mask = 0xffff;
ea6dedd7 840 break;
e5c56ed3
DB		 841#endif
842#ifdef CONFIG_ARCH_OMAP730
ea6dedd7
ID		 843 case METHOD_GPIO_730:
844 reg += OMAP730_GPIO_INT_MASK;
99c47707
ID		 845 mask = 0xffffffff;
846 inv = 1;
ea6dedd7 847 break;
e5c56ed3 848#endif
56739a69
ZM		 849#ifdef CONFIG_ARCH_OMAP850
850 case METHOD_GPIO_850:
851 reg += OMAP850_GPIO_INT_MASK;
852 mask = 0xffffffff;
853 inv = 1;
854 break;
855#endif
44169075
SS		 856#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
857 defined(CONFIG_ARCH_OMAP4)
ea6dedd7
ID		 858 case METHOD_GPIO_24XX:
859 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 860 mask = 0xffffffff;
ea6dedd7 861 break;
e5c56ed3 862#endif
ea6dedd7 863 default:
e5c56ed3 864 WARN_ON(1);
ea6dedd7
ID		 865 return 0;
866 }
867
99c47707
ID		 868 l = __raw_readl(reg);
869 if (inv)
870 l = ~l;
871 l &= mask;
872 return l;
ea6dedd7
ID		 873}
874
5e1c5ff4
TL		 875static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
876{
92105bb7 877 void __iomem *reg = bank->base;
5e1c5ff4
TL		 878 u32 l;
879
880 switch (bank->method) {
e5c56ed3 881#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 882 case METHOD_MPUIO:
883 reg += OMAP_MPUIO_GPIO_MASKIT;
884 l = __raw_readl(reg);
885 if (enable)
886 l &= ~(gpio_mask);
887 else
888 l |= gpio_mask;
889 break;
e5c56ed3
DB		 890#endif
891#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 892 case METHOD_GPIO_1510:
893 reg += OMAP1510_GPIO_INT_MASK;
894 l = __raw_readl(reg);
895 if (enable)
896 l &= ~(gpio_mask);
897 else
898 l |= gpio_mask;
899 break;
e5c56ed3
DB		 900#endif
901#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 902 case METHOD_GPIO_1610:
903 if (enable)
904 reg += OMAP1610_GPIO_SET_IRQENABLE1;
905 else
906 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
907 l = gpio_mask;
908 break;
e5c56ed3
DB		 909#endif
910#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 911 case METHOD_GPIO_730:
912 reg += OMAP730_GPIO_INT_MASK;
913 l = __raw_readl(reg);
914 if (enable)
915 l &= ~(gpio_mask);
916 else
917 l |= gpio_mask;
918 break;
e5c56ed3 919#endif
56739a69
ZM		 920#ifdef CONFIG_ARCH_OMAP850
921 case METHOD_GPIO_850:
922 reg += OMAP850_GPIO_INT_MASK;
923 l = __raw_readl(reg);
924 if (enable)
925 l &= ~(gpio_mask);
926 else
927 l |= gpio_mask;
928 break;
929#endif
44169075
SS		 930#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
931 defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 932 case METHOD_GPIO_24XX:
933 if (enable)
934 reg += OMAP24XX_GPIO_SETIRQENABLE1;
935 else
936 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
937 l = gpio_mask;
938 break;
e5c56ed3 939#endif
5e1c5ff4 940 default:
e5c56ed3 941 WARN_ON(1);
5e1c5ff4
TL		 942 return;
943 }
944 __raw_writel(l, reg);
945}
946
947static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
948{
949 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
950}
951
92105bb7
TL		 952/*
953 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
954 * 1510 does not seem to have a wake-up register. If JTAG is connected
955 * to the target, system will wake up always on GPIO events. While
956 * system is running all registered GPIO interrupts need to have wake-up
957 * enabled. When system is suspended, only selected GPIO interrupts need
958 * to have wake-up enabled.
959 */
960static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
961{
a6472533
DB		 962 unsigned long flags;
963
92105bb7 964 switch (bank->method) {
3ac4fa99 965#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 966 case METHOD_MPUIO:
92105bb7 967 case METHOD_GPIO_1610:
a6472533 968 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 969 if (enable)
92105bb7 970 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 971 else
92105bb7 972 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 973 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 974 return 0;
3ac4fa99 975#endif
44169075
SS		 976#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
977 defined(CONFIG_ARCH_OMAP4)
3ac4fa99 978 case METHOD_GPIO_24XX:
11a78b79
DB		 979 if (bank->non_wakeup_gpios & (1 << gpio)) {
980 printk(KERN_ERR "Unable to modify wakeup on "
981 "non-wakeup GPIO%d\n",
982 (bank - gpio_bank) * 32 + gpio);
983 return -EINVAL;
984 }
a6472533 985 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 986 if (enable)
3ac4fa99 987 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 988 else
3ac4fa99 989 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 990 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 991 return 0;
992#endif
92105bb7
TL		 993 default:
994 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
995 bank->method);
996 return -EINVAL;
997 }
998}
999
4196dd6b
TL		 1000static void _reset_gpio(struct gpio_bank *bank, int gpio)
1001{
1002 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1003 _set_gpio_irqenable(bank, gpio, 0);
1004 _clear_gpio_irqstatus(bank, gpio);
6cab4860 1005 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 1006}
1007
92105bb7
TL		 1008/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1009static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1010{
1011 unsigned int gpio = irq - IH_GPIO_BASE;
1012 struct gpio_bank *bank;
1013 int retval;
1014
1015 if (check_gpio(gpio) < 0)
1016 return -ENODEV;
58781016 1017 bank = get_irq_chip_data(irq);
92105bb7 1018 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 1019
1020 return retval;
1021}
1022
3ff164e1 1023static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1024{
3ff164e1 1025 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1026 unsigned long flags;
52e31344 1027
a6472533 1028 spin_lock_irqsave(&bank->lock, flags);
92105bb7 1029
4196dd6b
TL		 1030 /* Set trigger to none. You need to enable the desired trigger with
1031 * request_irq() or set_irq_type().
1032 */
3ff164e1 1033 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 1034
1a8bfa1e 1035#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 1036 if (bank->method == METHOD_GPIO_1510) {
92105bb7 1037 void __iomem *reg;
5e1c5ff4 1038
92105bb7 1039 /* Claim the pin for MPU */
5e1c5ff4 1040 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 1041 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 1042 }
1043#endif
a6472533 1044 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1045
1046 return 0;
1047}
1048
3ff164e1 1049static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1050{
3ff164e1 1051 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1052 unsigned long flags;
5e1c5ff4 1053
a6472533 1054 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1055#ifdef CONFIG_ARCH_OMAP16XX
1056 if (bank->method == METHOD_GPIO_1610) {
1057 /* Disable wake-up during idle for dynamic tick */
1058 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 1059 __raw_writel(1 << offset, reg);
92105bb7
TL		 1060 }
1061#endif
44169075
SS		 1062#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1063 defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 1064 if (bank->method == METHOD_GPIO_24XX) {
1065 /* Disable wake-up during idle for dynamic tick */
1066 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 1067 __raw_writel(1 << offset, reg);
92105bb7
TL		 1068 }
1069#endif
3ff164e1 1070 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1071 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1072}
1073
1074/*
1075 * We need to unmask the GPIO bank interrupt as soon as possible to
1076 * avoid missing GPIO interrupts for other lines in the bank.
1077 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1078 * in the bank to avoid missing nested interrupts for a GPIO line.
1079 * If we wait to unmask individual GPIO lines in the bank after the
1080 * line's interrupt handler has been run, we may miss some nested
1081 * interrupts.
1082 */
10dd5ce2 1083static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1084{
92105bb7 1085 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 1086 u32 isr;
1087 unsigned int gpio_irq;
1088 struct gpio_bank *bank;
ea6dedd7
ID		 1089 u32 retrigger = 0;
1090 int unmasked = 0;
5e1c5ff4
TL		 1091
1092 desc->chip->ack(irq);
1093
418ca1f0 1094 bank = get_irq_data(irq);
e5c56ed3 1095#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 1096 if (bank->method == METHOD_MPUIO)
1097 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 1098#endif
1a8bfa1e 1099#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1100 if (bank->method == METHOD_GPIO_1510)
1101 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1102#endif
1103#if defined(CONFIG_ARCH_OMAP16XX)
1104 if (bank->method == METHOD_GPIO_1610)
1105 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1106#endif
1107#ifdef CONFIG_ARCH_OMAP730
1108 if (bank->method == METHOD_GPIO_730)
1109 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1110#endif
56739a69
ZM		 1111#ifdef CONFIG_ARCH_OMAP850
1112 if (bank->method == METHOD_GPIO_850)
1113 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1114#endif
44169075
SS		 1115#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1116 defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 1117 if (bank->method == METHOD_GPIO_24XX)
1118 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1119#endif
92105bb7 1120 while(1) {
6e60e79a 1121 u32 isr_saved, level_mask = 0;
ea6dedd7 1122 u32 enabled;
6e60e79a 1123
ea6dedd7
ID		 1124 enabled = _get_gpio_irqbank_mask(bank);
1125 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1126
1127 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1128 isr &= 0x0000ffff;
1129
5492fb1a 1130 if (cpu_class_is_omap2()) {
b144ff6f 1131 level_mask = bank->level_mask & enabled;
ea6dedd7 1132 }
6e60e79a
TL		 1133
1134 /* clear edge sensitive interrupts before handler(s) are
1135 called so that we don't miss any interrupt occurred while
1136 executing them */
1137 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1138 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1139 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1140
1141 /* if there is only edge sensitive GPIO pin interrupts
1142 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1143 if (!level_mask && !unmasked) {
1144 unmasked = 1;
6e60e79a 1145 desc->chip->unmask(irq);
ea6dedd7 1146 }
92105bb7 1147
ea6dedd7
ID		 1148 isr |= retrigger;
1149 retrigger = 0;
92105bb7
TL		 1150 if (!isr)
1151 break;
1152
1153 gpio_irq = bank->virtual_irq_start;
1154 for (; isr != 0; isr >>= 1, gpio_irq++) {
92105bb7
TL		 1155 if (!(isr & 1))
1156 continue;
29454dde 1157
d8aa0251 1158 generic_handle_irq(gpio_irq);
92105bb7 1159 }
1a8bfa1e 1160 }
ea6dedd7
ID		 1161 /* if bank has any level sensitive GPIO pin interrupt
1162 configured, we must unmask the bank interrupt only after
1163 handler(s) are executed in order to avoid spurious bank
1164 interrupt */
1165 if (!unmasked)
1166 desc->chip->unmask(irq);
1167
5e1c5ff4
TL		 1168}
1169
4196dd6b
TL		 1170static void gpio_irq_shutdown(unsigned int irq)
1171{
1172 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1173 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1174
1175 _reset_gpio(bank, gpio);
1176}
1177
5e1c5ff4
TL		 1178static void gpio_ack_irq(unsigned int irq)
1179{
1180 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1181 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1182
1183 _clear_gpio_irqstatus(bank, gpio);
1184}
1185
1186static void gpio_mask_irq(unsigned int irq)
1187{
1188 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1189 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1190
1191 _set_gpio_irqenable(bank, gpio, 0);
1192}
1193
1194static void gpio_unmask_irq(unsigned int irq)
1195{
1196 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1197 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f
KH		 1198 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1199
1200 /* For level-triggered GPIOs, the clearing must be done after
1201 * the HW source is cleared, thus after the handler has run */
1202 if (bank->level_mask & irq_mask) {
1203 _set_gpio_irqenable(bank, gpio, 0);
1204 _clear_gpio_irqstatus(bank, gpio);
1205 }
5e1c5ff4 1206
4de8c75b 1207 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1208}
1209
e5c56ed3
DB		 1210static struct irq_chip gpio_irq_chip = {
1211 .name = "GPIO",
1212 .shutdown = gpio_irq_shutdown,
1213 .ack = gpio_ack_irq,
1214 .mask = gpio_mask_irq,
1215 .unmask = gpio_unmask_irq,
1216 .set_type = gpio_irq_type,
1217 .set_wake = gpio_wake_enable,
1218};
1219
1220/*---------------------------------------------------------------------*/
1221
1222#ifdef CONFIG_ARCH_OMAP1
1223
1224/* MPUIO uses the always-on 32k clock */
1225
5e1c5ff4
TL		 1226static void mpuio_ack_irq(unsigned int irq)
1227{
1228 /* The ISR is reset automatically, so do nothing here. */
1229}
1230
1231static void mpuio_mask_irq(unsigned int irq)
1232{
1233 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1234 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1235
1236 _set_gpio_irqenable(bank, gpio, 0);
1237}
1238
1239static void mpuio_unmask_irq(unsigned int irq)
1240{
1241 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1242 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1243
1244 _set_gpio_irqenable(bank, gpio, 1);
1245}
1246
e5c56ed3
DB		 1247static struct irq_chip mpuio_irq_chip = {
1248 .name = "MPUIO",
1249 .ack = mpuio_ack_irq,
1250 .mask = mpuio_mask_irq,
1251 .unmask = mpuio_unmask_irq,
92105bb7 1252 .set_type = gpio_irq_type,
11a78b79
DB		 1253#ifdef CONFIG_ARCH_OMAP16XX
1254 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1255 .set_wake = gpio_wake_enable,
1256#endif
5e1c5ff4
TL		 1257};
1258
e5c56ed3
DB		 1259
1260#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1261
11a78b79
DB		 1262
1263#ifdef CONFIG_ARCH_OMAP16XX
1264
1265#include <linux/platform_device.h>
1266
1267static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1268{
1269 struct gpio_bank *bank = platform_get_drvdata(pdev);
1270 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1271 unsigned long flags;
11a78b79 1272
a6472533 1273 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1274 bank->saved_wakeup = __raw_readl(mask_reg);
1275 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1276 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1277
1278 return 0;
1279}
1280
1281static int omap_mpuio_resume_early(struct platform_device *pdev)
1282{
1283 struct gpio_bank *bank = platform_get_drvdata(pdev);
1284 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1285 unsigned long flags;
11a78b79 1286
a6472533 1287 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1288 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1289 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1290
1291 return 0;
1292}
1293
1294/* use platform_driver for this, now that there's no longer any
1295 * point to sys_device (other than not disturbing old code).
1296 */
1297static struct platform_driver omap_mpuio_driver = {
1298 .suspend_late = omap_mpuio_suspend_late,
1299 .resume_early = omap_mpuio_resume_early,
1300 .driver = {
1301 .name = "mpuio",
1302 },
1303};
1304
1305static struct platform_device omap_mpuio_device = {
1306 .name = "mpuio",
1307 .id = -1,
1308 .dev = {
1309 .driver = &omap_mpuio_driver.driver,
1310 }
1311 /* could list the /proc/iomem resources */
1312};
1313
1314static inline void mpuio_init(void)
1315{
fcf126d8
DB		 1316 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1317
11a78b79
DB		 1318 if (platform_driver_register(&omap_mpuio_driver) == 0)
1319 (void) platform_device_register(&omap_mpuio_device);
1320}
1321
1322#else
1323static inline void mpuio_init(void) {}
1324#endif /* 16xx */
1325
e5c56ed3
DB		 1326#else
1327
1328extern struct irq_chip mpuio_irq_chip;
1329
1330#define bank_is_mpuio(bank) 0
11a78b79 1331static inline void mpuio_init(void) {}
e5c56ed3
DB		 1332
1333#endif
1334
1335/*---------------------------------------------------------------------*/
5e1c5ff4 1336
52e31344
DB		 1337/* REVISIT these are stupid implementations! replace by ones that
1338 * don't switch on METHOD_* and which mostly avoid spinlocks
1339 */
1340
1341static int gpio_input(struct gpio_chip *chip, unsigned offset)
1342{
1343 struct gpio_bank *bank;
1344 unsigned long flags;
1345
1346 bank = container_of(chip, struct gpio_bank, chip);
1347 spin_lock_irqsave(&bank->lock, flags);
1348 _set_gpio_direction(bank, offset, 1);
1349 spin_unlock_irqrestore(&bank->lock, flags);
1350 return 0;
1351}
1352
1353static int gpio_get(struct gpio_chip *chip, unsigned offset)
1354{
0b84b5ca 1355 return __omap_get_gpio_datain(chip->base + offset);
52e31344
DB		 1356}
1357
1358static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1359{
1360 struct gpio_bank *bank;
1361 unsigned long flags;
1362
1363 bank = container_of(chip, struct gpio_bank, chip);
1364 spin_lock_irqsave(&bank->lock, flags);
1365 _set_gpio_dataout(bank, offset, value);
1366 _set_gpio_direction(bank, offset, 0);
1367 spin_unlock_irqrestore(&bank->lock, flags);
1368 return 0;
1369}
1370
1371static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1372{
1373 struct gpio_bank *bank;
1374 unsigned long flags;
1375
1376 bank = container_of(chip, struct gpio_bank, chip);
1377 spin_lock_irqsave(&bank->lock, flags);
1378 _set_gpio_dataout(bank, offset, value);
1379 spin_unlock_irqrestore(&bank->lock, flags);
1380}
1381
a007b709
DB		 1382static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1383{
1384 struct gpio_bank *bank;
1385
1386 bank = container_of(chip, struct gpio_bank, chip);
1387 return bank->virtual_irq_start + offset;
1388}
1389
52e31344
DB		 1390/*---------------------------------------------------------------------*/
1391
1a8bfa1e 1392static int initialized;
44169075 1393#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1a8bfa1e 1394static struct clk * gpio_ick;
5492fb1a
SMK		 1395#endif
1396
1397#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1398static struct clk * gpio_fck;
5492fb1a 1399#endif
5e1c5ff4 1400
5492fb1a 1401#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1402static struct clk * gpio5_ick;
1403static struct clk * gpio5_fck;
1404#endif
1405
44169075 1406#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
5492fb1a
SMK		 1407static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1408#endif
1409
8ba55c5c
DB		 1410/* This lock class tells lockdep that GPIO irqs are in a different
1411 * category than their parents, so it won't report false recursion.
1412 */
1413static struct lock_class_key gpio_lock_class;
1414
5e1c5ff4
TL		 1415static int __init _omap_gpio_init(void)
1416{
1417 int i;
52e31344 1418 int gpio = 0;
5e1c5ff4 1419 struct gpio_bank *bank;
5492fb1a 1420 char clk_name[11];
5e1c5ff4
TL		 1421
1422 initialized = 1;
1423
5492fb1a 1424#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1425 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1426 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1427 if (IS_ERR(gpio_ick))
92105bb7
TL		 1428 printk("Could not get arm_gpio_ck\n");
1429 else
30ff720b 1430 clk_enable(gpio_ick);
1a8bfa1e 1431 }
5492fb1a
SMK		 1432#endif
1433#if defined(CONFIG_ARCH_OMAP2)
1434 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1435 gpio_ick = clk_get(NULL, "gpios_ick");
1436 if (IS_ERR(gpio_ick))
1437 printk("Could not get gpios_ick\n");
1438 else
30ff720b 1439 clk_enable(gpio_ick);
1a8bfa1e 1440 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1441 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1442 printk("Could not get gpios_fck\n");
1443 else
30ff720b 1444 clk_enable(gpio_fck);
56a25641
SMK		 1445
1446 /*
5492fb1a 1447 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1448 */
5492fb1a 1449#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1450 if (cpu_is_omap2430()) {
1451 gpio5_ick = clk_get(NULL, "gpio5_ick");
1452 if (IS_ERR(gpio5_ick))
1453 printk("Could not get gpio5_ick\n");
1454 else
1455 clk_enable(gpio5_ick);
1456 gpio5_fck = clk_get(NULL, "gpio5_fck");
1457 if (IS_ERR(gpio5_fck))
1458 printk("Could not get gpio5_fck\n");
1459 else
1460 clk_enable(gpio5_fck);
1461 }
1462#endif
5492fb1a
SMK		 1463 }
1464#endif
1465
44169075
SS		 1466#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1467 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
5492fb1a
SMK		 1468 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1469 sprintf(clk_name, "gpio%d_ick", i + 1);
1470 gpio_iclks[i] = clk_get(NULL, clk_name);
1471 if (IS_ERR(gpio_iclks[i]))
1472 printk(KERN_ERR "Could not get %s\n", clk_name);
1473 else
1474 clk_enable(gpio_iclks[i]);
5492fb1a
SMK		 1475 }
1476 }
1477#endif
1478
92105bb7 1479
1a8bfa1e 1480#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1481 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1482 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1483 gpio_bank_count = 2;
1484 gpio_bank = gpio_bank_1510;
1485 }
1486#endif
1487#if defined(CONFIG_ARCH_OMAP16XX)
1488 if (cpu_is_omap16xx()) {
92105bb7 1489 u32 rev;
5e1c5ff4
TL		 1490
1491 gpio_bank_count = 5;
1492 gpio_bank = gpio_bank_1610;
7c7095aa 1493 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
5e1c5ff4
TL		 1494 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1495 (rev >> 4) & 0x0f, rev & 0x0f);
1496 }
1497#endif
1498#ifdef CONFIG_ARCH_OMAP730
1499 if (cpu_is_omap730()) {
1500 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1501 gpio_bank_count = 7;
1502 gpio_bank = gpio_bank_730;
1503 }
92105bb7 1504#endif
56739a69
ZM		 1505#ifdef CONFIG_ARCH_OMAP850
1506 if (cpu_is_omap850()) {
1507 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1508 gpio_bank_count = 7;
1509 gpio_bank = gpio_bank_850;
1510 }
1511#endif
56a25641 1512
92105bb7 1513#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1514 if (cpu_is_omap242x()) {
92105bb7
TL		 1515 int rev;
1516
1517 gpio_bank_count = 4;
56a25641 1518 gpio_bank = gpio_bank_242x;
7c7095aa 1519 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641
SMK		 1520 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1521 (rev >> 4) & 0x0f, rev & 0x0f);
1522 }
1523 if (cpu_is_omap243x()) {
1524 int rev;
1525
1526 gpio_bank_count = 5;
1527 gpio_bank = gpio_bank_243x;
7c7095aa 1528 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641 1529 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
92105bb7
TL		 1530 (rev >> 4) & 0x0f, rev & 0x0f);
1531 }
5492fb1a
SMK		 1532#endif
1533#ifdef CONFIG_ARCH_OMAP34XX
1534 if (cpu_is_omap34xx()) {
1535 int rev;
1536
1537 gpio_bank_count = OMAP34XX_NR_GPIOS;
1538 gpio_bank = gpio_bank_34xx;
7c7095aa 1539 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
5492fb1a
SMK		 1540 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1541 (rev >> 4) & 0x0f, rev & 0x0f);
1542 }
44169075
SS		 1543#endif
1544#ifdef CONFIG_ARCH_OMAP4
1545 if (cpu_is_omap44xx()) {
1546 int rev;
1547
1548 gpio_bank_count = OMAP34XX_NR_GPIOS;
1549 gpio_bank = gpio_bank_44xx;
1550 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1551 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1552 (rev >> 4) & 0x0f, rev & 0x0f);
1553 }
5e1c5ff4
TL		 1554#endif
1555 for (i = 0; i < gpio_bank_count; i++) {
1556 int j, gpio_count = 16;
1557
1558 bank = &gpio_bank[i];
5e1c5ff4 1559 spin_lock_init(&bank->lock);
e5c56ed3 1560 if (bank_is_mpuio(bank))
7c7095aa 1561 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1562 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1563 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1564 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1565 }
d11ac979 1566 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1567 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1568 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1569 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1570 }
56739a69 1571 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
5e1c5ff4
TL		 1572 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1573 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1574
1575 gpio_count = 32; /* 730 has 32-bit GPIOs */
1576 }
d11ac979 1577
44169075
SS		 1578#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1579 defined(CONFIG_ARCH_OMAP4)
92105bb7 1580 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1581 static const u32 non_wakeup_gpios[] = {
1582 0xe203ffc0, 0x08700040
1583 };
1584
92105bb7
TL		 1585 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1586 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf 1587 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
cb5793db 1588 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
14f1c3bf
JY		 1589
1590 /* Initialize interface clock ungated, module enabled */
1591 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
3ac4fa99
JY		 1592 if (i < ARRAY_SIZE(non_wakeup_gpios))
1593 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1594 gpio_count = 32;
1595 }
5e1c5ff4 1596#endif
52e31344
DB		 1597
1598 /* REVISIT eventually switch from OMAP-specific gpio structs
1599 * over to the generic ones
1600 */
3ff164e1
JN		 1601 bank->chip.request = omap_gpio_request;
1602 bank->chip.free = omap_gpio_free;
52e31344
DB		 1603 bank->chip.direction_input = gpio_input;
1604 bank->chip.get = gpio_get;
1605 bank->chip.direction_output = gpio_output;
1606 bank->chip.set = gpio_set;
a007b709 1607 bank->chip.to_irq = gpio_2irq;
52e31344
DB		 1608 if (bank_is_mpuio(bank)) {
1609 bank->chip.label = "mpuio";
69114a47 1610#ifdef CONFIG_ARCH_OMAP16XX
d8f388d8
DB		 1611 bank->chip.dev = &omap_mpuio_device.dev;
1612#endif
52e31344
DB		 1613 bank->chip.base = OMAP_MPUIO(0);
1614 } else {
1615 bank->chip.label = "gpio";
1616 bank->chip.base = gpio;
1617 gpio += gpio_count;
1618 }
1619 bank->chip.ngpio = gpio_count;
1620
1621 gpiochip_add(&bank->chip);
1622
5e1c5ff4
TL		 1623 for (j = bank->virtual_irq_start;
1624 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1625 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1626 set_irq_chip_data(j, bank);
e5c56ed3 1627 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1628 set_irq_chip(j, &mpuio_irq_chip);
1629 else
1630 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1631 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1632 set_irq_flags(j, IRQF_VALID);
1633 }
1634 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1635 set_irq_data(bank->irq, bank);
89db9482 1636
44169075 1637 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
89db9482
JH		 1638 sprintf(clk_name, "gpio%d_dbck", i + 1);
1639 bank->dbck = clk_get(NULL, clk_name);
1640 if (IS_ERR(bank->dbck))
1641 printk(KERN_ERR "Could not get %s\n", clk_name);
1642 }
5e1c5ff4
TL		 1643 }
1644
1645 /* Enable system clock for GPIO module.
1646 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1647 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1648 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1649
14f1c3bf
JY		 1650 /* Enable autoidle for the OCP interface */
1651 if (cpu_is_omap24xx())
1652 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1653 if (cpu_is_omap34xx())
1654 omap_writel(1 << 0, 0x48306814);
d11ac979 1655
5e1c5ff4
TL		 1656 return 0;
1657}
1658
44169075
SS		 1659#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1660 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 1661static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1662{
1663 int i;
1664
5492fb1a 1665 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1666 return 0;
1667
1668 for (i = 0; i < gpio_bank_count; i++) {
1669 struct gpio_bank *bank = &gpio_bank[i];
1670 void __iomem *wake_status;
1671 void __iomem *wake_clear;
1672 void __iomem *wake_set;
a6472533 1673 unsigned long flags;
92105bb7
TL		 1674
1675 switch (bank->method) {
e5c56ed3 1676#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1677 case METHOD_GPIO_1610:
1678 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1679 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1680 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1681 break;
e5c56ed3 1682#endif
44169075
SS		 1683#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1684 defined(CONFIG_ARCH_OMAP4)
92105bb7 1685 case METHOD_GPIO_24XX:
723fdb78 1686 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1687 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1688 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1689 break;
e5c56ed3 1690#endif
92105bb7
TL		 1691 default:
1692 continue;
1693 }
1694
a6472533 1695 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1696 bank->saved_wakeup = __raw_readl(wake_status);
1697 __raw_writel(0xffffffff, wake_clear);
1698 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1699 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1700 }
1701
1702 return 0;
1703}
1704
1705static int omap_gpio_resume(struct sys_device *dev)
1706{
1707 int i;
1708
723fdb78 1709 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1710 return 0;
1711
1712 for (i = 0; i < gpio_bank_count; i++) {
1713 struct gpio_bank *bank = &gpio_bank[i];
1714 void __iomem *wake_clear;
1715 void __iomem *wake_set;
a6472533 1716 unsigned long flags;
92105bb7
TL		 1717
1718 switch (bank->method) {
e5c56ed3 1719#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1720 case METHOD_GPIO_1610:
1721 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1722 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1723 break;
e5c56ed3 1724#endif
44169075
SS		 1725#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1726 defined(CONFIG_ARCH_OMAP4)
92105bb7 1727 case METHOD_GPIO_24XX:
0d9356cb
TL		 1728 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1729 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1730 break;
e5c56ed3 1731#endif
92105bb7
TL		 1732 default:
1733 continue;
1734 }
1735
a6472533 1736 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1737 __raw_writel(0xffffffff, wake_clear);
1738 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1739 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1740 }
1741
1742 return 0;
1743}
1744
1745static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1746 .name = "gpio",
92105bb7
TL		 1747 .suspend = omap_gpio_suspend,
1748 .resume = omap_gpio_resume,
1749};
1750
1751static struct sys_device omap_gpio_device = {
1752 .id = 0,
1753 .cls = &omap_gpio_sysclass,
1754};
3ac4fa99
JY		 1755
1756#endif
1757
44169075
SS		 1758#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1759 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 1760
1761static int workaround_enabled;
1762
1763void omap2_gpio_prepare_for_retention(void)
1764{
1765 int i, c = 0;
1766
1767 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1768 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1769 for (i = 0; i < gpio_bank_count; i++) {
1770 struct gpio_bank *bank = &gpio_bank[i];
1771 u32 l1, l2;
1772
1773 if (!(bank->enabled_non_wakeup_gpios))
1774 continue;
44169075
SS		 1775#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1776 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 1777 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1778 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1779 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1780#endif
3ac4fa99
JY		 1781 bank->saved_fallingdetect = l1;
1782 bank->saved_risingdetect = l2;
1783 l1 &= ~bank->enabled_non_wakeup_gpios;
1784 l2 &= ~bank->enabled_non_wakeup_gpios;
44169075
SS		 1785#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1786 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 1787 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1788 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1789#endif
3ac4fa99
JY		 1790 c++;
1791 }
1792 if (!c) {
1793 workaround_enabled = 0;
1794 return;
1795 }
1796 workaround_enabled = 1;
1797}
1798
1799void omap2_gpio_resume_after_retention(void)
1800{
1801 int i;
1802
1803 if (!workaround_enabled)
1804 return;
1805 for (i = 0; i < gpio_bank_count; i++) {
1806 struct gpio_bank *bank = &gpio_bank[i];
1807 u32 l;
1808
1809 if (!(bank->enabled_non_wakeup_gpios))
1810 continue;
44169075
SS		 1811#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1812 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 1813 __raw_writel(bank->saved_fallingdetect,
1814 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1815 __raw_writel(bank->saved_risingdetect,
1816 bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1817#endif
3ac4fa99
JY		 1818 /* Check if any of the non-wakeup interrupt GPIOs have changed
1819 * state. If so, generate an IRQ by software. This is
1820 * horribly racy, but it's the best we can do to work around
1821 * this silicon bug. */
44169075
SS		 1822#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1823 defined(CONFIG_ARCH_OMAP4)
3ac4fa99 1824 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
5492fb1a 1825#endif
3ac4fa99
JY		 1826 l ^= bank->saved_datain;
1827 l &= bank->non_wakeup_gpios;
1828 if (l) {
1829 u32 old0, old1;
44169075
SS		 1830#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1831 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 1832 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1833 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1834 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1835 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1836 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1837 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5492fb1a 1838#endif
3ac4fa99
JY		 1839 }
1840 }
1841
1842}
1843
92105bb7
TL		 1844#endif
1845
5e1c5ff4
TL		 1846/*
1847 * This may get called early from board specific init
1a8bfa1e 1848 * for boards that have interrupts routed via FPGA.
5e1c5ff4 1849 */
277d58ef 1850int __init omap_gpio_init(void)
5e1c5ff4
TL		 1851{
1852 if (!initialized)
1853 return _omap_gpio_init();
1854 else
1855 return 0;
1856}
1857
92105bb7
TL		 1858static int __init omap_gpio_sysinit(void)
1859{
1860 int ret = 0;
1861
1862 if (!initialized)
1863 ret = _omap_gpio_init();
1864
11a78b79
DB		 1865 mpuio_init();
1866
44169075
SS		 1867#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1868 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
5492fb1a 1869 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 1870 if (ret == 0) {
1871 ret = sysdev_class_register(&omap_gpio_sysclass);
1872 if (ret == 0)
1873 ret = sysdev_register(&omap_gpio_device);
1874 }
1875 }
1876#endif
1877
1878 return ret;
1879}
1880
92105bb7 1881arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 1882
1883
1884#ifdef CONFIG_DEBUG_FS
1885
1886#include <linux/debugfs.h>
1887#include <linux/seq_file.h>
1888
1889static int gpio_is_input(struct gpio_bank *bank, int mask)
1890{
1891 void __iomem *reg = bank->base;
1892
1893 switch (bank->method) {
1894 case METHOD_MPUIO:
1895 reg += OMAP_MPUIO_IO_CNTL;
1896 break;
1897 case METHOD_GPIO_1510:
1898 reg += OMAP1510_GPIO_DIR_CONTROL;
1899 break;
1900 case METHOD_GPIO_1610:
1901 reg += OMAP1610_GPIO_DIRECTION;
1902 break;
1903 case METHOD_GPIO_730:
1904 reg += OMAP730_GPIO_DIR_CONTROL;
1905 break;
56739a69
ZM		 1906 case METHOD_GPIO_850:
1907 reg += OMAP850_GPIO_DIR_CONTROL;
1908 break;
b9772a22
DB		 1909 case METHOD_GPIO_24XX:
1910 reg += OMAP24XX_GPIO_OE;
1911 break;
1912 }
1913 return __raw_readl(reg) & mask;
1914}
1915
1916
1917static int dbg_gpio_show(struct seq_file *s, void *unused)
1918{
1919 unsigned i, j, gpio;
1920
1921 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1922 struct gpio_bank *bank = gpio_bank + i;
1923 unsigned bankwidth = 16;
1924 u32 mask = 1;
1925
e5c56ed3 1926 if (bank_is_mpuio(bank))
b9772a22 1927 gpio = OMAP_MPUIO(0);
56739a69
ZM		 1928 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
1929 cpu_is_omap850())
b9772a22
DB		 1930 bankwidth = 32;
1931
1932 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1933 unsigned irq, value, is_in, irqstat;
52e31344 1934 const char *label;
b9772a22 1935
52e31344
DB		 1936 label = gpiochip_is_requested(&bank->chip, j);
1937 if (!label)
b9772a22
DB		 1938 continue;
1939
1940 irq = bank->virtual_irq_start + j;
0b84b5ca 1941 value = gpio_get_value(gpio);
b9772a22
DB		 1942 is_in = gpio_is_input(bank, mask);
1943
e5c56ed3 1944 if (bank_is_mpuio(bank))
52e31344 1945 seq_printf(s, "MPUIO %2d ", j);
b9772a22 1946 else
52e31344 1947 seq_printf(s, "GPIO %3d ", gpio);
21c867f1 1948 seq_printf(s, "(%-20.20s): %s %s",
52e31344 1949 label,
b9772a22
DB		 1950 is_in ? "in " : "out",
1951 value ? "hi" : "lo");
1952
52e31344
DB		 1953/* FIXME for at least omap2, show pullup/pulldown state */
1954
b9772a22 1955 irqstat = irq_desc[irq].status;
3a26e331 1956#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
44169075 1957 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
b9772a22
DB		 1958 if (is_in && ((bank->suspend_wakeup & mask)
1959 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1960 char *trigger = NULL;
1961
1962 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1963 case IRQ_TYPE_EDGE_FALLING:
1964 trigger = "falling";
1965 break;
1966 case IRQ_TYPE_EDGE_RISING:
1967 trigger = "rising";
1968 break;
1969 case IRQ_TYPE_EDGE_BOTH:
1970 trigger = "bothedge";
1971 break;
1972 case IRQ_TYPE_LEVEL_LOW:
1973 trigger = "low";
1974 break;
1975 case IRQ_TYPE_LEVEL_HIGH:
1976 trigger = "high";
1977 break;
1978 case IRQ_TYPE_NONE:
52e31344 1979 trigger = "(?)";
b9772a22
DB		 1980 break;
1981 }
52e31344 1982 seq_printf(s, ", irq-%d %-8s%s",
b9772a22
DB		 1983 irq, trigger,
1984 (bank->suspend_wakeup & mask)
1985 ? " wakeup" : "");
1986 }
3a26e331 1987#endif
b9772a22
DB		 1988 seq_printf(s, "\n");
1989 }
1990
e5c56ed3 1991 if (bank_is_mpuio(bank)) {
b9772a22
DB		 1992 seq_printf(s, "\n");
1993 gpio = 0;
1994 }
1995 }
1996 return 0;
1997}
1998
1999static int dbg_gpio_open(struct inode *inode, struct file *file)
2000{
e5c56ed3 2001 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 2002}
2003
2004static const struct file_operations debug_fops = {
2005 .open = dbg_gpio_open,
2006 .read = seq_read,
2007 .llseek = seq_lseek,
2008 .release = single_release,
2009};
2010
2011static int __init omap_gpio_debuginit(void)
2012{
e5c56ed3
DB		 2013 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2014 NULL, NULL, &debug_fops);
b9772a22
DB		 2015 return 0;
2016}
2017late_initcall(omap_gpio_debuginit);
2018#endif
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