]> bbs.cooldavid.org Git - net-next-2.6.git/blame - arch/arm/plat-omap/dma.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'header-move' of git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemo...
[net-next-2.6.git] / arch / arm / plat-omap / dma.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/dma.c
3 *
97b7f715 4 * Copyright (C) 2003 - 2008 Nokia Corporation
96de0e25 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
f8151e5c 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
1a8bfa1e 10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
5e1c5ff4
TL		 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Support functions for the OMAP internal DMA channels.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 *
19 */
20
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/sched.h>
24#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/interrupt.h>
418ca1f0 27#include <linux/irq.h>
97b7f715 28#include <linux/io.h>
5e1c5ff4
TL		 29
30#include <asm/system.h>
be509729 31#include <asm/arch/hardware.h>
5e1c5ff4 32#include <asm/dma.h>
5e1c5ff4
TL		 33
34#include <asm/arch/tc.h>
35
f8151e5c
AG		 36#undef DEBUG
37
38#ifndef CONFIG_ARCH_OMAP1
39enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
41};
42
43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
1a8bfa1e 44#endif
5e1c5ff4 45
97b7f715
TL		 46#define OMAP_DMA_ACTIVE 0x01
47#define OMAP_DMA_CCR_EN (1 << 7)
7ff879db 48#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
5e1c5ff4 49
97b7f715 50#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
5e1c5ff4 51
97b7f715 52static int enable_1510_mode;
5e1c5ff4
TL		 53
54struct omap_dma_lch {
55 int next_lch;
56 int dev_id;
57 u16 saved_csr;
58 u16 enabled_irqs;
59 const char *dev_name;
97b7f715 60 void (*callback)(int lch, u16 ch_status, void *data);
5e1c5ff4 61 void *data;
f8151e5c
AG		 62
63#ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
65 int prev_linked_ch;
66 int next_linked_ch;
67 int state;
68 int chain_id;
69
70 int status;
71#endif
5e1c5ff4
TL		 72 long flags;
73};
74
f8151e5c
AG		 75struct dma_link_info {
76 int *linked_dmach_q;
77 int no_of_lchs_linked;
78
79 int q_count;
80 int q_tail;
81 int q_head;
82
83 int chain_state;
84 int chain_mode;
85
86};
87
4d96372e
TL		 88static struct dma_link_info *dma_linked_lch;
89
90#ifndef CONFIG_ARCH_OMAP1
f8151e5c
AG		 91
92/* Chain handling macros */
93#define OMAP_DMA_CHAIN_QINIT(chain_id) \
94 do { \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
98 } while (0)
99#define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102#define OMAP_DMA_CHAIN_QLAST(chain_id) \
103 do { \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
106 } while (0)
107#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109#define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
112 do { \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
115 } while (0)
116
117#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
118 do { \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
121 } while (0)
122#endif
4d96372e
TL		 123
124static int dma_lch_count;
5e1c5ff4
TL		 125static int dma_chan_count;
126
127static spinlock_t dma_chan_lock;
4d96372e 128static struct omap_dma_lch *dma_chan;
0499bdeb 129static void __iomem *omap_dma_base;
5e1c5ff4 130
4d96372e 131static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
5e1c5ff4
TL		 132 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
133 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
134 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
135 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
136 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
137};
138
f8151e5c
AG		 139static inline void disable_lnk(int lch);
140static void omap_disable_channel_irq(int lch);
141static inline void omap_enable_channel_irq(int lch);
142
1a8bfa1e 143#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
8e86f427 144 __func__);
1a8bfa1e 145
0499bdeb
TL		 146#define dma_read(reg) \
147({ \
148 u32 __val; \
149 if (cpu_class_is_omap1()) \
150 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
151 else \
152 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
153 __val; \
154})
155
156#define dma_write(val, reg) \
157({ \
158 if (cpu_class_is_omap1()) \
159 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
160 else \
161 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
162})
163
1a8bfa1e
TL		 164#ifdef CONFIG_ARCH_OMAP15XX
165/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
166int omap_dma_in_1510_mode(void)
167{
168 return enable_1510_mode;
169}
170#else
171#define omap_dma_in_1510_mode() 0
172#endif
173
174#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 175static inline int get_gdma_dev(int req)
176{
177 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
178 int shift = ((req - 1) % 5) * 6;
179
180 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
181}
182
183static inline void set_gdma_dev(int req, int dev)
184{
185 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
186 int shift = ((req - 1) % 5) * 6;
187 u32 l;
188
189 l = omap_readl(reg);
190 l &= ~(0x3f << shift);
191 l |= (dev - 1) << shift;
192 omap_writel(l, reg);
193}
1a8bfa1e
TL		 194#else
195#define set_gdma_dev(req, dev) do {} while (0)
196#endif
5e1c5ff4 197
0499bdeb 198/* Omap1 only */
5e1c5ff4
TL		 199static void clear_lch_regs(int lch)
200{
201 int i;
0499bdeb 202 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
5e1c5ff4
TL		 203
204 for (i = 0; i < 0x2c; i += 2)
0499bdeb 205 __raw_writew(0, lch_base + i);
5e1c5ff4
TL		 206}
207
709eb3e5 208void omap_set_dma_priority(int lch, int dst_port, int priority)
5e1c5ff4
TL		 209{
210 unsigned long reg;
211 u32 l;
212
709eb3e5
TL		 213 if (cpu_class_is_omap1()) {
214 switch (dst_port) {
215 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
216 reg = OMAP_TC_OCPT1_PRIOR;
217 break;
218 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
219 reg = OMAP_TC_OCPT2_PRIOR;
220 break;
221 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
222 reg = OMAP_TC_EMIFF_PRIOR;
223 break;
224 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
225 reg = OMAP_TC_EMIFS_PRIOR;
226 break;
227 default:
228 BUG();
229 return;
230 }
231 l = omap_readl(reg);
232 l &= ~(0xf << 8);
233 l |= (priority & 0xf) << 8;
234 omap_writel(l, reg);
235 }
236
f8151e5c 237 if (cpu_class_is_omap2()) {
0499bdeb
TL		 238 u32 ccr;
239
240 ccr = dma_read(CCR(lch));
709eb3e5 241 if (priority)
0499bdeb 242 ccr |= (1 << 6);
709eb3e5 243 else
0499bdeb
TL		 244 ccr &= ~(1 << 6);
245 dma_write(ccr, CCR(lch));
5e1c5ff4 246 }
5e1c5ff4 247}
97b7f715 248EXPORT_SYMBOL(omap_set_dma_priority);
5e1c5ff4
TL		 249
250void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
1a8bfa1e
TL		 251 int frame_count, int sync_mode,
252 int dma_trigger, int src_or_dst_synch)
5e1c5ff4 253{
0499bdeb
TL		 254 u32 l;
255
256 l = dma_read(CSDP(lch));
257 l &= ~0x03;
258 l |= data_type;
259 dma_write(l, CSDP(lch));
5e1c5ff4 260
1a8bfa1e 261 if (cpu_class_is_omap1()) {
0499bdeb
TL		 262 u16 ccr;
263
264 ccr = dma_read(CCR(lch));
265 ccr &= ~(1 << 5);
1a8bfa1e 266 if (sync_mode == OMAP_DMA_SYNC_FRAME)
0499bdeb
TL		 267 ccr |= 1 << 5;
268 dma_write(ccr, CCR(lch));
1a8bfa1e 269
0499bdeb
TL		 270 ccr = dma_read(CCR2(lch));
271 ccr &= ~(1 << 2);
1a8bfa1e 272 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
0499bdeb
TL		 273 ccr |= 1 << 2;
274 dma_write(ccr, CCR2(lch));
1a8bfa1e
TL		 275 }
276
f8151e5c 277 if (cpu_class_is_omap2() && dma_trigger) {
0499bdeb 278 u32 val;
1a8bfa1e 279
0499bdeb 280 val = dma_read(CCR(lch));
eca9e56e 281 val &= ~(3 << 19);
1a8bfa1e
TL		 282 if (dma_trigger > 63)
283 val |= 1 << 20;
284 if (dma_trigger > 31)
285 val |= 1 << 19;
5e1c5ff4 286
eca9e56e 287 val &= ~(0x1f);
1a8bfa1e 288 val |= (dma_trigger & 0x1f);
5e1c5ff4 289
1a8bfa1e
TL		 290 if (sync_mode & OMAP_DMA_SYNC_FRAME)
291 val |= 1 << 5;
eca9e56e
PU		 292 else
293 val &= ~(1 << 5);
5e1c5ff4 294
1a8bfa1e
TL		 295 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
296 val |= 1 << 18;
eca9e56e
PU		 297 else
298 val &= ~(1 << 18);
5e1c5ff4 299
1a8bfa1e
TL		 300 if (src_or_dst_synch)
301 val |= 1 << 24; /* source synch */
302 else
303 val &= ~(1 << 24); /* dest synch */
304
0499bdeb 305 dma_write(val, CCR(lch));
1a8bfa1e
TL		 306 }
307
0499bdeb
TL		 308 dma_write(elem_count, CEN(lch));
309 dma_write(frame_count, CFN(lch));
5e1c5ff4 310}
97b7f715 311EXPORT_SYMBOL(omap_set_dma_transfer_params);
1a8bfa1e 312
5e1c5ff4
TL		 313void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
314{
315 u16 w;
316
317 BUG_ON(omap_dma_in_1510_mode());
318
f8151e5c 319 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 320 REVISIT_24XX();
321 return;
322 }
323
0499bdeb
TL		 324 w = dma_read(CCR2(lch));
325 w &= ~0x03;
326
5e1c5ff4
TL		 327 switch (mode) {
328 case OMAP_DMA_CONSTANT_FILL:
329 w |= 0x01;
330 break;
331 case OMAP_DMA_TRANSPARENT_COPY:
332 w |= 0x02;
333 break;
334 case OMAP_DMA_COLOR_DIS:
335 break;
336 default:
337 BUG();
338 }
0499bdeb 339 dma_write(w, CCR2(lch));
5e1c5ff4 340
0499bdeb
TL		 341 w = dma_read(LCH_CTRL(lch));
342 w &= ~0x0f;
5e1c5ff4
TL		 343 /* Default is channel type 2D */
344 if (mode) {
0499bdeb
TL		 345 dma_write((u16)color, COLOR_L(lch));
346 dma_write((u16)(color >> 16), COLOR_U(lch));
5e1c5ff4
TL		 347 w |= 1; /* Channel type G */
348 }
0499bdeb 349 dma_write(w, LCH_CTRL(lch));
5e1c5ff4 350}
97b7f715 351EXPORT_SYMBOL(omap_set_dma_color_mode);
5e1c5ff4 352
709eb3e5
TL		 353void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
354{
f8151e5c 355 if (cpu_class_is_omap2()) {
0499bdeb
TL		 356 u32 csdp;
357
358 csdp = dma_read(CSDP(lch));
359 csdp &= ~(0x3 << 16);
360 csdp |= (mode << 16);
361 dma_write(csdp, CSDP(lch));
709eb3e5
TL		 362 }
363}
97b7f715 364EXPORT_SYMBOL(omap_set_dma_write_mode);
709eb3e5 365
0499bdeb
TL		 366void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
367{
368 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
369 u32 l;
370
371 l = dma_read(LCH_CTRL(lch));
372 l &= ~0x7;
373 l |= mode;
374 dma_write(l, LCH_CTRL(lch));
375 }
376}
377EXPORT_SYMBOL(omap_set_dma_channel_mode);
378
1a8bfa1e 379/* Note that src_port is only for omap1 */
5e1c5ff4 380void omap_set_dma_src_params(int lch, int src_port, int src_amode,
1a8bfa1e
TL		 381 unsigned long src_start,
382 int src_ei, int src_fi)
5e1c5ff4 383{
97b7f715
TL		 384 u32 l;
385
1a8bfa1e 386 if (cpu_class_is_omap1()) {
0499bdeb 387 u16 w;
1a8bfa1e 388
0499bdeb
TL		 389 w = dma_read(CSDP(lch));
390 w &= ~(0x1f << 2);
391 w |= src_port << 2;
392 dma_write(w, CSDP(lch));
97b7f715 393 }
1a8bfa1e 394
97b7f715
TL		 395 l = dma_read(CCR(lch));
396 l &= ~(0x03 << 12);
397 l |= src_amode << 12;
398 dma_write(l, CCR(lch));
0499bdeb 399
97b7f715 400 if (cpu_class_is_omap1()) {
0499bdeb
TL		 401 dma_write(src_start >> 16, CSSA_U(lch));
402 dma_write((u16)src_start, CSSA_L(lch));
1a8bfa1e 403 }
5e1c5ff4 404
97b7f715 405 if (cpu_class_is_omap2())
0499bdeb 406 dma_write(src_start, CSSA(lch));
97b7f715
TL		 407
408 dma_write(src_ei, CSEI(lch));
409 dma_write(src_fi, CSFI(lch));
1a8bfa1e 410}
97b7f715 411EXPORT_SYMBOL(omap_set_dma_src_params);
5e1c5ff4 412
97b7f715 413void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
1a8bfa1e
TL		 414{
415 omap_set_dma_transfer_params(lch, params->data_type,
416 params->elem_count, params->frame_count,
417 params->sync_mode, params->trigger,
418 params->src_or_dst_synch);
419 omap_set_dma_src_params(lch, params->src_port,
420 params->src_amode, params->src_start,
421 params->src_ei, params->src_fi);
422
423 omap_set_dma_dest_params(lch, params->dst_port,
424 params->dst_amode, params->dst_start,
425 params->dst_ei, params->dst_fi);
f8151e5c
AG		 426 if (params->read_prio || params->write_prio)
427 omap_dma_set_prio_lch(lch, params->read_prio,
428 params->write_prio);
5e1c5ff4 429}
97b7f715 430EXPORT_SYMBOL(omap_set_dma_params);
5e1c5ff4
TL		 431
432void omap_set_dma_src_index(int lch, int eidx, int fidx)
433{
97b7f715 434 if (cpu_class_is_omap2())
1a8bfa1e 435 return;
97b7f715 436
0499bdeb
TL		 437 dma_write(eidx, CSEI(lch));
438 dma_write(fidx, CSFI(lch));
5e1c5ff4 439}
97b7f715 440EXPORT_SYMBOL(omap_set_dma_src_index);
5e1c5ff4
TL		 441
442void omap_set_dma_src_data_pack(int lch, int enable)
443{
0499bdeb
TL		 444 u32 l;
445
446 l = dma_read(CSDP(lch));
447 l &= ~(1 << 6);
1a8bfa1e 448 if (enable)
0499bdeb
TL		 449 l |= (1 << 6);
450 dma_write(l, CSDP(lch));
5e1c5ff4 451}
97b7f715 452EXPORT_SYMBOL(omap_set_dma_src_data_pack);
5e1c5ff4
TL		 453
454void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
455{
6dc3c8f2 456 unsigned int burst = 0;
0499bdeb
TL		 457 u32 l;
458
459 l = dma_read(CSDP(lch));
460 l &= ~(0x03 << 7);
5e1c5ff4 461
5e1c5ff4
TL		 462 switch (burst_mode) {
463 case OMAP_DMA_DATA_BURST_DIS:
464 break;
465 case OMAP_DMA_DATA_BURST_4:
f8151e5c 466 if (cpu_class_is_omap2())
6dc3c8f2
KP		 467 burst = 0x1;
468 else
469 burst = 0x2;
5e1c5ff4
TL		 470 break;
471 case OMAP_DMA_DATA_BURST_8:
f8151e5c 472 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 473 burst = 0x2;
474 break;
475 }
476 /* not supported by current hardware on OMAP1
5e1c5ff4
TL		 477 * w |= (0x03 << 7);
478 * fall through
479 */
6dc3c8f2 480 case OMAP_DMA_DATA_BURST_16:
f8151e5c 481 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 482 burst = 0x3;
483 break;
484 }
485 /* OMAP1 don't support burst 16
486 * fall through
487 */
5e1c5ff4
TL		 488 default:
489 BUG();
490 }
0499bdeb
TL		 491
492 l |= (burst << 7);
493 dma_write(l, CSDP(lch));
5e1c5ff4 494}
97b7f715 495EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
5e1c5ff4 496
1a8bfa1e 497/* Note that dest_port is only for OMAP1 */
5e1c5ff4 498void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
1a8bfa1e
TL		 499 unsigned long dest_start,
500 int dst_ei, int dst_fi)
5e1c5ff4 501{
0499bdeb
TL		 502 u32 l;
503
1a8bfa1e 504 if (cpu_class_is_omap1()) {
0499bdeb
TL		 505 l = dma_read(CSDP(lch));
506 l &= ~(0x1f << 9);
507 l |= dest_port << 9;
508 dma_write(l, CSDP(lch));
1a8bfa1e 509 }
5e1c5ff4 510
0499bdeb
TL		 511 l = dma_read(CCR(lch));
512 l &= ~(0x03 << 14);
513 l |= dest_amode << 14;
514 dma_write(l, CCR(lch));
1a8bfa1e
TL		 515
516 if (cpu_class_is_omap1()) {
0499bdeb
TL		 517 dma_write(dest_start >> 16, CDSA_U(lch));
518 dma_write(dest_start, CDSA_L(lch));
1a8bfa1e 519 }
5e1c5ff4 520
f8151e5c 521 if (cpu_class_is_omap2())
0499bdeb 522 dma_write(dest_start, CDSA(lch));
5e1c5ff4 523
0499bdeb
TL		 524 dma_write(dst_ei, CDEI(lch));
525 dma_write(dst_fi, CDFI(lch));
5e1c5ff4 526}
97b7f715 527EXPORT_SYMBOL(omap_set_dma_dest_params);
5e1c5ff4
TL		 528
529void omap_set_dma_dest_index(int lch, int eidx, int fidx)
530{
97b7f715 531 if (cpu_class_is_omap2())
1a8bfa1e 532 return;
97b7f715 533
0499bdeb
TL		 534 dma_write(eidx, CDEI(lch));
535 dma_write(fidx, CDFI(lch));
5e1c5ff4 536}
97b7f715 537EXPORT_SYMBOL(omap_set_dma_dest_index);
5e1c5ff4
TL		 538
539void omap_set_dma_dest_data_pack(int lch, int enable)
540{
0499bdeb
TL		 541 u32 l;
542
543 l = dma_read(CSDP(lch));
544 l &= ~(1 << 13);
1a8bfa1e 545 if (enable)
0499bdeb
TL		 546 l |= 1 << 13;
547 dma_write(l, CSDP(lch));
5e1c5ff4 548}
97b7f715 549EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
5e1c5ff4
TL		 550
551void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
552{
6dc3c8f2 553 unsigned int burst = 0;
0499bdeb
TL		 554 u32 l;
555
556 l = dma_read(CSDP(lch));
557 l &= ~(0x03 << 14);
5e1c5ff4 558
5e1c5ff4
TL		 559 switch (burst_mode) {
560 case OMAP_DMA_DATA_BURST_DIS:
561 break;
562 case OMAP_DMA_DATA_BURST_4:
f8151e5c 563 if (cpu_class_is_omap2())
6dc3c8f2
KP		 564 burst = 0x1;
565 else
566 burst = 0x2;
5e1c5ff4
TL		 567 break;
568 case OMAP_DMA_DATA_BURST_8:
f8151e5c 569 if (cpu_class_is_omap2())
6dc3c8f2
KP		 570 burst = 0x2;
571 else
572 burst = 0x3;
5e1c5ff4 573 break;
6dc3c8f2 574 case OMAP_DMA_DATA_BURST_16:
f8151e5c 575 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 576 burst = 0x3;
577 break;
578 }
579 /* OMAP1 don't support burst 16
580 * fall through
581 */
5e1c5ff4
TL		 582 default:
583 printk(KERN_ERR "Invalid DMA burst mode\n");
584 BUG();
585 return;
586 }
0499bdeb
TL		 587 l |= (burst << 14);
588 dma_write(l, CSDP(lch));
5e1c5ff4 589}
97b7f715 590EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
5e1c5ff4 591
1a8bfa1e 592static inline void omap_enable_channel_irq(int lch)
5e1c5ff4 593{
1a8bfa1e 594 u32 status;
5e1c5ff4 595
7ff879db
TL		 596 /* Clear CSR */
597 if (cpu_class_is_omap1())
0499bdeb 598 status = dma_read(CSR(lch));
f8151e5c 599 else if (cpu_class_is_omap2())
0499bdeb 600 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
1a8bfa1e 601
5e1c5ff4 602 /* Enable some nice interrupts. */
0499bdeb 603 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
5e1c5ff4
TL		 604}
605
1a8bfa1e 606static void omap_disable_channel_irq(int lch)
5e1c5ff4 607{
f8151e5c 608 if (cpu_class_is_omap2())
0499bdeb 609 dma_write(0, CICR(lch));
1a8bfa1e
TL		 610}
611
612void omap_enable_dma_irq(int lch, u16 bits)
613{
614 dma_chan[lch].enabled_irqs |= bits;
615}
97b7f715 616EXPORT_SYMBOL(omap_enable_dma_irq);
5e1c5ff4 617
1a8bfa1e
TL		 618void omap_disable_dma_irq(int lch, u16 bits)
619{
620 dma_chan[lch].enabled_irqs &= ~bits;
621}
97b7f715 622EXPORT_SYMBOL(omap_disable_dma_irq);
1a8bfa1e
TL		 623
624static inline void enable_lnk(int lch)
625{
0499bdeb
TL		 626 u32 l;
627
628 l = dma_read(CLNK_CTRL(lch));
629
1a8bfa1e 630 if (cpu_class_is_omap1())
0499bdeb 631 l &= ~(1 << 14);
5e1c5ff4 632
1a8bfa1e 633 /* Set the ENABLE_LNK bits */
5e1c5ff4 634 if (dma_chan[lch].next_lch != -1)
0499bdeb 635 l = dma_chan[lch].next_lch | (1 << 15);
f8151e5c
AG		 636
637#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 638 if (cpu_class_is_omap2())
639 if (dma_chan[lch].next_linked_ch != -1)
640 l = dma_chan[lch].next_linked_ch | (1 << 15);
f8151e5c 641#endif
0499bdeb
TL		 642
643 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 644}
645
646static inline void disable_lnk(int lch)
647{
0499bdeb
TL		 648 u32 l;
649
650 l = dma_read(CLNK_CTRL(lch));
651
5e1c5ff4 652 /* Disable interrupts */
1a8bfa1e 653 if (cpu_class_is_omap1()) {
0499bdeb 654 dma_write(0, CICR(lch));
1a8bfa1e 655 /* Set the STOP_LNK bit */
0499bdeb 656 l |= 1 << 14;
1a8bfa1e 657 }
5e1c5ff4 658
f8151e5c 659 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 660 omap_disable_channel_irq(lch);
661 /* Clear the ENABLE_LNK bit */
0499bdeb 662 l &= ~(1 << 15);
1a8bfa1e 663 }
5e1c5ff4 664
0499bdeb 665 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 666 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
667}
668
1a8bfa1e 669static inline void omap2_enable_irq_lch(int lch)
5e1c5ff4 670{
1a8bfa1e
TL		 671 u32 val;
672
f8151e5c 673 if (!cpu_class_is_omap2())
1a8bfa1e
TL		 674 return;
675
0499bdeb 676 val = dma_read(IRQENABLE_L0);
1a8bfa1e 677 val |= 1 << lch;
0499bdeb 678 dma_write(val, IRQENABLE_L0);
1a8bfa1e
TL		 679}
680
681int omap_request_dma(int dev_id, const char *dev_name,
97b7f715 682 void (*callback)(int lch, u16 ch_status, void *data),
1a8bfa1e
TL		 683 void *data, int *dma_ch_out)
684{
685 int ch, free_ch = -1;
686 unsigned long flags;
687 struct omap_dma_lch *chan;
688
689 spin_lock_irqsave(&dma_chan_lock, flags);
690 for (ch = 0; ch < dma_chan_count; ch++) {
691 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
692 free_ch = ch;
693 if (dev_id == 0)
694 break;
695 }
696 }
697 if (free_ch == -1) {
698 spin_unlock_irqrestore(&dma_chan_lock, flags);
699 return -EBUSY;
700 }
701 chan = dma_chan + free_ch;
702 chan->dev_id = dev_id;
703
704 if (cpu_class_is_omap1())
705 clear_lch_regs(free_ch);
5e1c5ff4 706
f8151e5c 707 if (cpu_class_is_omap2())
1a8bfa1e
TL		 708 omap_clear_dma(free_ch);
709
710 spin_unlock_irqrestore(&dma_chan_lock, flags);
711
712 chan->dev_name = dev_name;
713 chan->callback = callback;
714 chan->data = data;
97b7f715 715
f8151e5c 716#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 717 if (cpu_class_is_omap2()) {
718 chan->chain_id = -1;
719 chan->next_linked_ch = -1;
720 }
f8151e5c 721#endif
97b7f715 722
7ff879db 723 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
1a8bfa1e 724
7ff879db
TL		 725 if (cpu_class_is_omap1())
726 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
f8151e5c 727 else if (cpu_class_is_omap2())
7ff879db
TL		 728 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
729 OMAP2_DMA_TRANS_ERR_IRQ;
1a8bfa1e
TL		 730
731 if (cpu_is_omap16xx()) {
732 /* If the sync device is set, configure it dynamically. */
733 if (dev_id != 0) {
734 set_gdma_dev(free_ch + 1, dev_id);
735 dev_id = free_ch + 1;
736 }
97b7f715
TL		 737 /*
738 * Disable the 1510 compatibility mode and set the sync device
739 * id.
740 */
0499bdeb 741 dma_write(dev_id | (1 << 10), CCR(free_ch));
1a8bfa1e 742 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
0499bdeb 743 dma_write(dev_id, CCR(free_ch));
1a8bfa1e
TL		 744 }
745
f8151e5c 746 if (cpu_class_is_omap2()) {
1a8bfa1e 747 omap2_enable_irq_lch(free_ch);
1a8bfa1e
TL		 748 omap_enable_channel_irq(free_ch);
749 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 750 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
751 dma_write(1 << free_ch, IRQSTATUS_L0);
1a8bfa1e
TL		 752 }
753
754 *dma_ch_out = free_ch;
755
756 return 0;
757}
97b7f715 758EXPORT_SYMBOL(omap_request_dma);
1a8bfa1e
TL		 759
760void omap_free_dma(int lch)
761{
762 unsigned long flags;
763
764 spin_lock_irqsave(&dma_chan_lock, flags);
765 if (dma_chan[lch].dev_id == -1) {
97b7f715 766 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
1a8bfa1e
TL		 767 lch);
768 spin_unlock_irqrestore(&dma_chan_lock, flags);
769 return;
770 }
97b7f715 771
1a8bfa1e
TL		 772 dma_chan[lch].dev_id = -1;
773 dma_chan[lch].next_lch = -1;
774 dma_chan[lch].callback = NULL;
775 spin_unlock_irqrestore(&dma_chan_lock, flags);
776
777 if (cpu_class_is_omap1()) {
778 /* Disable all DMA interrupts for the channel. */
0499bdeb 779 dma_write(0, CICR(lch));
1a8bfa1e 780 /* Make sure the DMA transfer is stopped. */
0499bdeb 781 dma_write(0, CCR(lch));
1a8bfa1e
TL		 782 }
783
f8151e5c 784 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 785 u32 val;
786 /* Disable interrupts */
0499bdeb 787 val = dma_read(IRQENABLE_L0);
1a8bfa1e 788 val &= ~(1 << lch);
0499bdeb 789 dma_write(val, IRQENABLE_L0);
1a8bfa1e
TL		 790
791 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 792 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
793 dma_write(1 << lch, IRQSTATUS_L0);
1a8bfa1e
TL		 794
795 /* Disable all DMA interrupts for the channel. */
0499bdeb 796 dma_write(0, CICR(lch));
1a8bfa1e
TL		 797
798 /* Make sure the DMA transfer is stopped. */
0499bdeb 799 dma_write(0, CCR(lch));
1a8bfa1e
TL		 800 omap_clear_dma(lch);
801 }
802}
97b7f715 803EXPORT_SYMBOL(omap_free_dma);
1a8bfa1e 804
f8151e5c
AG		 805/**
806 * @brief omap_dma_set_global_params : Set global priority settings for dma
807 *
808 * @param arb_rate
809 * @param max_fifo_depth
810 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
811 * DMA_THREAD_RESERVE_ONET
812 * DMA_THREAD_RESERVE_TWOT
813 * DMA_THREAD_RESERVE_THREET
814 */
815void
816omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
817{
818 u32 reg;
819
820 if (!cpu_class_is_omap2()) {
8e86f427 821 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
f8151e5c
AG		 822 return;
823 }
824
825 if (arb_rate == 0)
826 arb_rate = 1;
827
828 reg = (arb_rate & 0xff) << 16;
829 reg |= (0xff & max_fifo_depth);
830
0499bdeb 831 dma_write(reg, GCR);
f8151e5c
AG		 832}
833EXPORT_SYMBOL(omap_dma_set_global_params);
834
835/**
836 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
837 *
838 * @param lch
839 * @param read_prio - Read priority
840 * @param write_prio - Write priority
841 * Both of the above can be set with one of the following values :
842 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
843 */
844int
845omap_dma_set_prio_lch(int lch, unsigned char read_prio,
846 unsigned char write_prio)
847{
0499bdeb 848 u32 l;
f8151e5c 849
4d96372e 850 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
f8151e5c
AG		 851 printk(KERN_ERR "Invalid channel id\n");
852 return -EINVAL;
853 }
0499bdeb
TL		 854 l = dma_read(CCR(lch));
855 l &= ~((1 << 6) | (1 << 26));
f8151e5c 856 if (cpu_is_omap2430() || cpu_is_omap34xx())
0499bdeb 857 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
f8151e5c 858 else
0499bdeb
TL		 859 l |= ((read_prio & 0x1) << 6);
860
861 dma_write(l, CCR(lch));
f8151e5c 862
f8151e5c
AG		 863 return 0;
864}
865EXPORT_SYMBOL(omap_dma_set_prio_lch);
866
1a8bfa1e
TL		 867/*
868 * Clears any DMA state so the DMA engine is ready to restart with new buffers
869 * through omap_start_dma(). Any buffers in flight are discarded.
870 */
871void omap_clear_dma(int lch)
872{
873 unsigned long flags;
874
875 local_irq_save(flags);
876
877 if (cpu_class_is_omap1()) {
0499bdeb
TL		 878 u32 l;
879
880 l = dma_read(CCR(lch));
881 l &= ~OMAP_DMA_CCR_EN;
882 dma_write(l, CCR(lch));
1a8bfa1e
TL		 883
884 /* Clear pending interrupts */
0499bdeb 885 l = dma_read(CSR(lch));
1a8bfa1e
TL		 886 }
887
f8151e5c 888 if (cpu_class_is_omap2()) {
1a8bfa1e 889 int i;
0499bdeb 890 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
1a8bfa1e 891 for (i = 0; i < 0x44; i += 4)
0499bdeb 892 __raw_writel(0, lch_base + i);
1a8bfa1e
TL		 893 }
894
895 local_irq_restore(flags);
896}
97b7f715 897EXPORT_SYMBOL(omap_clear_dma);
1a8bfa1e
TL		 898
899void omap_start_dma(int lch)
900{
0499bdeb
TL		 901 u32 l;
902
5e1c5ff4
TL		 903 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
904 int next_lch, cur_lch;
4d96372e 905 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 906
907 dma_chan_link_map[lch] = 1;
908 /* Set the link register of the first channel */
909 enable_lnk(lch);
910
911 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
912 cur_lch = dma_chan[lch].next_lch;
913 do {
914 next_lch = dma_chan[cur_lch].next_lch;
915
1a8bfa1e 916 /* The loop case: we've been here already */
5e1c5ff4
TL		 917 if (dma_chan_link_map[cur_lch])
918 break;
919 /* Mark the current channel */
920 dma_chan_link_map[cur_lch] = 1;
921
922 enable_lnk(cur_lch);
1a8bfa1e 923 omap_enable_channel_irq(cur_lch);
5e1c5ff4
TL		 924
925 cur_lch = next_lch;
926 } while (next_lch != -1);
f8151e5c 927 } else if (cpu_class_is_omap2()) {
1a8bfa1e 928 /* Errata: Need to write lch even if not using chaining */
0499bdeb 929 dma_write(lch, CLNK_CTRL(lch));
5e1c5ff4
TL		 930 }
931
1a8bfa1e
TL		 932 omap_enable_channel_irq(lch);
933
0499bdeb
TL		 934 l = dma_read(CCR(lch));
935
97b7f715
TL		 936 /*
937 * Errata: On ES2.0 BUFFERING disable must be set.
938 * This will always fail on ES1.0
939 */
0499bdeb
TL		 940 if (cpu_is_omap24xx())
941 l |= OMAP_DMA_CCR_EN;
1a8bfa1e 942
0499bdeb
TL		 943 l |= OMAP_DMA_CCR_EN;
944 dma_write(l, CCR(lch));
5e1c5ff4 945
5e1c5ff4
TL		 946 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
947}
97b7f715 948EXPORT_SYMBOL(omap_start_dma);
5e1c5ff4
TL		 949
950void omap_stop_dma(int lch)
951{
0499bdeb
TL		 952 u32 l;
953
5e1c5ff4
TL		 954 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
955 int next_lch, cur_lch = lch;
4d96372e 956 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 957
958 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
959 do {
960 /* The loop case: we've been here already */
961 if (dma_chan_link_map[cur_lch])
962 break;
963 /* Mark the current channel */
964 dma_chan_link_map[cur_lch] = 1;
965
966 disable_lnk(cur_lch);
967
968 next_lch = dma_chan[cur_lch].next_lch;
969 cur_lch = next_lch;
970 } while (next_lch != -1);
971
972 return;
973 }
1a8bfa1e 974
5e1c5ff4 975 /* Disable all interrupts on the channel */
1a8bfa1e 976 if (cpu_class_is_omap1())
0499bdeb
TL		 977 dma_write(0, CICR(lch));
978
979 l = dma_read(CCR(lch));
980 l &= ~OMAP_DMA_CCR_EN;
981 dma_write(l, CCR(lch));
5e1c5ff4 982
5e1c5ff4
TL		 983 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
984}
97b7f715 985EXPORT_SYMBOL(omap_stop_dma);
5e1c5ff4 986
709eb3e5
TL		 987/*
988 * Allows changing the DMA callback function or data. This may be needed if
989 * the driver shares a single DMA channel for multiple dma triggers.
990 */
991int omap_set_dma_callback(int lch,
97b7f715 992 void (*callback)(int lch, u16 ch_status, void *data),
709eb3e5
TL		 993 void *data)
994{
995 unsigned long flags;
996
997 if (lch < 0)
998 return -ENODEV;
999
1000 spin_lock_irqsave(&dma_chan_lock, flags);
1001 if (dma_chan[lch].dev_id == -1) {
1002 printk(KERN_ERR "DMA callback for not set for free channel\n");
1003 spin_unlock_irqrestore(&dma_chan_lock, flags);
1004 return -EINVAL;
1005 }
1006 dma_chan[lch].callback = callback;
1007 dma_chan[lch].data = data;
1008 spin_unlock_irqrestore(&dma_chan_lock, flags);
1009
1010 return 0;
1011}
97b7f715 1012EXPORT_SYMBOL(omap_set_dma_callback);
709eb3e5 1013
1a8bfa1e
TL		 1014/*
1015 * Returns current physical source address for the given DMA channel.
1016 * If the channel is running the caller must disable interrupts prior calling
1017 * this function and process the returned value before re-enabling interrupt to
1018 * prevent races with the interrupt handler. Note that in continuous mode there
1019 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1020 * in incorrect return value.
1021 */
1022dma_addr_t omap_get_dma_src_pos(int lch)
5e1c5ff4 1023{
0695de32 1024 dma_addr_t offset = 0;
5e1c5ff4 1025
0499bdeb
TL		 1026 if (cpu_is_omap15xx())
1027 offset = dma_read(CPC(lch));
1028 else
1029 offset = dma_read(CSAC(lch));
5e1c5ff4 1030
0499bdeb
TL		 1031 /*
1032 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1033 * read before the DMA controller finished disabling the channel.
1034 */
1035 if (!cpu_is_omap15xx() && offset == 0)
1036 offset = dma_read(CSAC(lch));
1037
1038 if (cpu_class_is_omap1())
1039 offset |= (dma_read(CSSA_U(lch)) << 16);
5e1c5ff4 1040
1a8bfa1e 1041 return offset;
5e1c5ff4 1042}
97b7f715 1043EXPORT_SYMBOL(omap_get_dma_src_pos);
5e1c5ff4 1044
1a8bfa1e
TL		 1045/*
1046 * Returns current physical destination address for the given DMA channel.
1047 * If the channel is running the caller must disable interrupts prior calling
1048 * this function and process the returned value before re-enabling interrupt to
1049 * prevent races with the interrupt handler. Note that in continuous mode there
1050 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1051 * in incorrect return value.
1052 */
1053dma_addr_t omap_get_dma_dst_pos(int lch)
5e1c5ff4 1054{
0695de32 1055 dma_addr_t offset = 0;
5e1c5ff4 1056
0499bdeb
TL		 1057 if (cpu_is_omap15xx())
1058 offset = dma_read(CPC(lch));
1059 else
1060 offset = dma_read(CDAC(lch));
5e1c5ff4 1061
0499bdeb
TL		 1062 /*
1063 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1064 * read before the DMA controller finished disabling the channel.
1065 */
1066 if (!cpu_is_omap15xx() && offset == 0)
1067 offset = dma_read(CDAC(lch));
1068
1069 if (cpu_class_is_omap1())
1070 offset |= (dma_read(CDSA_U(lch)) << 16);
5e1c5ff4 1071
1a8bfa1e 1072 return offset;
5e1c5ff4 1073}
97b7f715 1074EXPORT_SYMBOL(omap_get_dma_dst_pos);
0499bdeb
TL		 1075
1076int omap_get_dma_active_status(int lch)
1077{
1078 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
5e1c5ff4 1079}
0499bdeb 1080EXPORT_SYMBOL(omap_get_dma_active_status);
5e1c5ff4 1081
1a8bfa1e 1082int omap_dma_running(void)
5e1c5ff4 1083{
1a8bfa1e 1084 int lch;
5e1c5ff4 1085
1a8bfa1e
TL		 1086 /* Check if LCD DMA is running */
1087 if (cpu_is_omap16xx())
1088 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1089 return 1;
5e1c5ff4 1090
1a8bfa1e 1091 for (lch = 0; lch < dma_chan_count; lch++)
0499bdeb 1092 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1a8bfa1e 1093 return 1;
5e1c5ff4 1094
1a8bfa1e 1095 return 0;
5e1c5ff4
TL		 1096}
1097
1098/*
1099 * lch_queue DMA will start right after lch_head one is finished.
1100 * For this DMA link to start, you still need to start (see omap_start_dma)
1101 * the first one. That will fire up the entire queue.
1102 */
97b7f715 1103void omap_dma_link_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1104{
1105 if (omap_dma_in_1510_mode()) {
1106 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1107 BUG();
1108 return;
1109 }
1110
1111 if ((dma_chan[lch_head].dev_id == -1) ||
1112 (dma_chan[lch_queue].dev_id == -1)) {
1a8bfa1e
TL		 1113 printk(KERN_ERR "omap_dma: trying to link "
1114 "non requested channels\n");
5e1c5ff4
TL		 1115 dump_stack();
1116 }
1117
1118 dma_chan[lch_head].next_lch = lch_queue;
1119}
97b7f715 1120EXPORT_SYMBOL(omap_dma_link_lch);
5e1c5ff4
TL		 1121
1122/*
1123 * Once the DMA queue is stopped, we can destroy it.
1124 */
97b7f715 1125void omap_dma_unlink_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1126{
1127 if (omap_dma_in_1510_mode()) {
1128 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1129 BUG();
1130 return;
1131 }
1132
1133 if (dma_chan[lch_head].next_lch != lch_queue ||
1134 dma_chan[lch_head].next_lch == -1) {
1a8bfa1e
TL		 1135 printk(KERN_ERR "omap_dma: trying to unlink "
1136 "non linked channels\n");
5e1c5ff4
TL		 1137 dump_stack();
1138 }
1139
5e1c5ff4
TL		 1140 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1141 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1a8bfa1e
TL		 1142 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1143 "before unlinking\n");
5e1c5ff4
TL		 1144 dump_stack();
1145 }
1146
1147 dma_chan[lch_head].next_lch = -1;
1148}
97b7f715
TL		 1149EXPORT_SYMBOL(omap_dma_unlink_lch);
1150
1151/*----------------------------------------------------------------------------*/
5e1c5ff4 1152
f8151e5c
AG		 1153#ifndef CONFIG_ARCH_OMAP1
1154/* Create chain of DMA channesls */
1155static void create_dma_lch_chain(int lch_head, int lch_queue)
1156{
0499bdeb 1157 u32 l;
f8151e5c
AG		 1158
1159 /* Check if this is the first link in chain */
1160 if (dma_chan[lch_head].next_linked_ch == -1) {
1161 dma_chan[lch_head].next_linked_ch = lch_queue;
1162 dma_chan[lch_head].prev_linked_ch = lch_queue;
1163 dma_chan[lch_queue].next_linked_ch = lch_head;
1164 dma_chan[lch_queue].prev_linked_ch = lch_head;
1165 }
1166
1167 /* a link exists, link the new channel in circular chain */
1168 else {
1169 dma_chan[lch_queue].next_linked_ch =
1170 dma_chan[lch_head].next_linked_ch;
1171 dma_chan[lch_queue].prev_linked_ch = lch_head;
1172 dma_chan[lch_head].next_linked_ch = lch_queue;
1173 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1174 lch_queue;
1175 }
1176
0499bdeb
TL		 1177 l = dma_read(CLNK_CTRL(lch_head));
1178 l &= ~(0x1f);
1179 l |= lch_queue;
1180 dma_write(l, CLNK_CTRL(lch_head));
f8151e5c 1181
0499bdeb
TL		 1182 l = dma_read(CLNK_CTRL(lch_queue));
1183 l &= ~(0x1f);
1184 l |= (dma_chan[lch_queue].next_linked_ch);
1185 dma_write(l, CLNK_CTRL(lch_queue));
f8151e5c
AG		 1186}
1187
1188/**
1189 * @brief omap_request_dma_chain : Request a chain of DMA channels
1190 *
1191 * @param dev_id - Device id using the dma channel
1192 * @param dev_name - Device name
1193 * @param callback - Call back function
1194 * @chain_id -
1195 * @no_of_chans - Number of channels requested
1196 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1197 * OMAP_DMA_DYNAMIC_CHAIN
1198 * @params - Channel parameters
1199 *
1200 * @return - Succes : 0
1201 * Failure: -EINVAL/-ENOMEM
1202 */
1203int omap_request_dma_chain(int dev_id, const char *dev_name,
1204 void (*callback) (int chain_id, u16 ch_status,
1205 void *data),
1206 int *chain_id, int no_of_chans, int chain_mode,
1207 struct omap_dma_channel_params params)
1208{
1209 int *channels;
1210 int i, err;
1211
1212 /* Is the chain mode valid ? */
1213 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1214 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1215 printk(KERN_ERR "Invalid chain mode requested\n");
1216 return -EINVAL;
1217 }
1218
1219 if (unlikely((no_of_chans < 1
4d96372e 1220 || no_of_chans > dma_lch_count))) {
f8151e5c
AG		 1221 printk(KERN_ERR "Invalid Number of channels requested\n");
1222 return -EINVAL;
1223 }
1224
1225 /* Allocate a queue to maintain the status of the channels
1226 * in the chain */
1227 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1228 if (channels == NULL) {
1229 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1230 return -ENOMEM;
1231 }
1232
1233 /* request and reserve DMA channels for the chain */
1234 for (i = 0; i < no_of_chans; i++) {
1235 err = omap_request_dma(dev_id, dev_name,
1236 callback, 0, &channels[i]);
1237 if (err < 0) {
1238 int j;
1239 for (j = 0; j < i; j++)
1240 omap_free_dma(channels[j]);
1241 kfree(channels);
1242 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1243 return err;
1244 }
f8151e5c
AG		 1245 dma_chan[channels[i]].prev_linked_ch = -1;
1246 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1247
1248 /*
1249 * Allowing client drivers to set common parameters now,
1250 * so that later only relevant (src_start, dest_start
1251 * and element count) can be set
1252 */
1253 omap_set_dma_params(channels[i], &params);
1254 }
1255
1256 *chain_id = channels[0];
1257 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1258 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1259 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1260 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1261
1262 for (i = 0; i < no_of_chans; i++)
1263 dma_chan[channels[i]].chain_id = *chain_id;
1264
1265 /* Reset the Queue pointers */
1266 OMAP_DMA_CHAIN_QINIT(*chain_id);
1267
1268 /* Set up the chain */
1269 if (no_of_chans == 1)
1270 create_dma_lch_chain(channels[0], channels[0]);
1271 else {
1272 for (i = 0; i < (no_of_chans - 1); i++)
1273 create_dma_lch_chain(channels[i], channels[i + 1]);
1274 }
97b7f715 1275
f8151e5c
AG		 1276 return 0;
1277}
1278EXPORT_SYMBOL(omap_request_dma_chain);
1279
1280/**
1281 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1282 * params after setting it. Dont do this while dma is running!!
1283 *
1284 * @param chain_id - Chained logical channel id.
1285 * @param params
1286 *
1287 * @return - Success : 0
1288 * Failure : -EINVAL
1289 */
1290int omap_modify_dma_chain_params(int chain_id,
1291 struct omap_dma_channel_params params)
1292{
1293 int *channels;
1294 u32 i;
1295
1296 /* Check for input params */
1297 if (unlikely((chain_id < 0
4d96372e 1298 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1299 printk(KERN_ERR "Invalid chain id\n");
1300 return -EINVAL;
1301 }
1302
1303 /* Check if the chain exists */
1304 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1305 printk(KERN_ERR "Chain doesn't exists\n");
1306 return -EINVAL;
1307 }
1308 channels = dma_linked_lch[chain_id].linked_dmach_q;
1309
1310 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1311 /*
1312 * Allowing client drivers to set common parameters now,
1313 * so that later only relevant (src_start, dest_start
1314 * and element count) can be set
1315 */
1316 omap_set_dma_params(channels[i], &params);
1317 }
97b7f715 1318
f8151e5c
AG		 1319 return 0;
1320}
1321EXPORT_SYMBOL(omap_modify_dma_chain_params);
1322
1323/**
1324 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1325 *
1326 * @param chain_id
1327 *
1328 * @return - Success : 0
1329 * Failure : -EINVAL
1330 */
1331int omap_free_dma_chain(int chain_id)
1332{
1333 int *channels;
1334 u32 i;
1335
1336 /* Check for input params */
4d96372e 1337 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1338 printk(KERN_ERR "Invalid chain id\n");
1339 return -EINVAL;
1340 }
1341
1342 /* Check if the chain exists */
1343 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1344 printk(KERN_ERR "Chain doesn't exists\n");
1345 return -EINVAL;
1346 }
1347
1348 channels = dma_linked_lch[chain_id].linked_dmach_q;
1349 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1350 dma_chan[channels[i]].next_linked_ch = -1;
1351 dma_chan[channels[i]].prev_linked_ch = -1;
1352 dma_chan[channels[i]].chain_id = -1;
1353 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1354 omap_free_dma(channels[i]);
1355 }
1356
1357 kfree(channels);
1358
1359 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1360 dma_linked_lch[chain_id].chain_mode = -1;
1361 dma_linked_lch[chain_id].chain_state = -1;
97b7f715 1362
f8151e5c
AG		 1363 return (0);
1364}
1365EXPORT_SYMBOL(omap_free_dma_chain);
1366
1367/**
1368 * @brief omap_dma_chain_status - Check if the chain is in
1369 * active / inactive state.
1370 * @param chain_id
1371 *
1372 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1373 * Failure : -EINVAL
1374 */
1375int omap_dma_chain_status(int chain_id)
1376{
1377 /* Check for input params */
4d96372e 1378 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1379 printk(KERN_ERR "Invalid chain id\n");
1380 return -EINVAL;
1381 }
1382
1383 /* Check if the chain exists */
1384 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1385 printk(KERN_ERR "Chain doesn't exists\n");
1386 return -EINVAL;
1387 }
1388 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1389 dma_linked_lch[chain_id].q_count);
1390
1391 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1392 return OMAP_DMA_CHAIN_INACTIVE;
97b7f715 1393
f8151e5c
AG		 1394 return OMAP_DMA_CHAIN_ACTIVE;
1395}
1396EXPORT_SYMBOL(omap_dma_chain_status);
1397
1398/**
1399 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1400 * set the params and start the transfer.
1401 *
1402 * @param chain_id
1403 * @param src_start - buffer start address
1404 * @param dest_start - Dest address
1405 * @param elem_count
1406 * @param frame_count
1407 * @param callbk_data - channel callback parameter data.
1408 *
f4b6a7ef 1409 * @return - Success : 0
f8151e5c
AG		 1410 * Failure: -EINVAL/-EBUSY
1411 */
1412int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1413 int elem_count, int frame_count, void *callbk_data)
1414{
1415 int *channels;
0499bdeb 1416 u32 l, lch;
f8151e5c
AG		 1417 int start_dma = 0;
1418
97b7f715
TL		 1419 /*
1420 * if buffer size is less than 1 then there is
1421 * no use of starting the chain
1422 */
f8151e5c
AG		 1423 if (elem_count < 1) {
1424 printk(KERN_ERR "Invalid buffer size\n");
1425 return -EINVAL;
1426 }
1427
1428 /* Check for input params */
1429 if (unlikely((chain_id < 0
4d96372e 1430 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1431 printk(KERN_ERR "Invalid chain id\n");
1432 return -EINVAL;
1433 }
1434
1435 /* Check if the chain exists */
1436 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1437 printk(KERN_ERR "Chain doesn't exist\n");
1438 return -EINVAL;
1439 }
1440
1441 /* Check if all the channels in chain are in use */
1442 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1443 return -EBUSY;
1444
1445 /* Frame count may be negative in case of indexed transfers */
1446 channels = dma_linked_lch[chain_id].linked_dmach_q;
1447
1448 /* Get a free channel */
1449 lch = channels[dma_linked_lch[chain_id].q_tail];
1450
1451 /* Store the callback data */
1452 dma_chan[lch].data = callbk_data;
1453
1454 /* Increment the q_tail */
1455 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1456
1457 /* Set the params to the free channel */
1458 if (src_start != 0)
0499bdeb 1459 dma_write(src_start, CSSA(lch));
f8151e5c 1460 if (dest_start != 0)
0499bdeb 1461 dma_write(dest_start, CDSA(lch));
f8151e5c
AG		 1462
1463 /* Write the buffer size */
0499bdeb
TL		 1464 dma_write(elem_count, CEN(lch));
1465 dma_write(frame_count, CFN(lch));
f8151e5c 1466
97b7f715
TL		 1467 /*
1468 * If the chain is dynamically linked,
1469 * then we may have to start the chain if its not active
1470 */
f8151e5c
AG		 1471 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1472
97b7f715
TL		 1473 /*
1474 * In Dynamic chain, if the chain is not started,
1475 * queue the channel
1476 */
f8151e5c
AG		 1477 if (dma_linked_lch[chain_id].chain_state ==
1478 DMA_CHAIN_NOTSTARTED) {
1479 /* Enable the link in previous channel */
1480 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1481 DMA_CH_QUEUED)
1482 enable_lnk(dma_chan[lch].prev_linked_ch);
1483 dma_chan[lch].state = DMA_CH_QUEUED;
1484 }
1485
97b7f715
TL		 1486 /*
1487 * Chain is already started, make sure its active,
1488 * if not then start the chain
1489 */
f8151e5c
AG		 1490 else {
1491 start_dma = 1;
1492
1493 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1494 DMA_CH_STARTED) {
1495 enable_lnk(dma_chan[lch].prev_linked_ch);
1496 dma_chan[lch].state = DMA_CH_QUEUED;
1497 start_dma = 0;
0499bdeb
TL		 1498 if (0 == ((1 << 7) & dma_read(
1499 CCR(dma_chan[lch].prev_linked_ch)))) {
f8151e5c
AG		 1500 disable_lnk(dma_chan[lch].
1501 prev_linked_ch);
1502 pr_debug("\n prev ch is stopped\n");
1503 start_dma = 1;
1504 }
1505 }
1506
1507 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1508 == DMA_CH_QUEUED) {
1509 enable_lnk(dma_chan[lch].prev_linked_ch);
1510 dma_chan[lch].state = DMA_CH_QUEUED;
1511 start_dma = 0;
1512 }
1513 omap_enable_channel_irq(lch);
1514
0499bdeb 1515 l = dma_read(CCR(lch));
f8151e5c 1516
0499bdeb
TL		 1517 if ((0 == (l & (1 << 24))))
1518 l &= ~(1 << 25);
f8151e5c 1519 else
0499bdeb 1520 l |= (1 << 25);
f8151e5c 1521 if (start_dma == 1) {
0499bdeb
TL		 1522 if (0 == (l & (1 << 7))) {
1523 l |= (1 << 7);
f8151e5c
AG		 1524 dma_chan[lch].state = DMA_CH_STARTED;
1525 pr_debug("starting %d\n", lch);
0499bdeb 1526 dma_write(l, CCR(lch));
f8151e5c
AG		 1527 } else
1528 start_dma = 0;
1529 } else {
0499bdeb
TL		 1530 if (0 == (l & (1 << 7)))
1531 dma_write(l, CCR(lch));
f8151e5c
AG		 1532 }
1533 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1534 }
1535 }
97b7f715 1536
f4b6a7ef 1537 return 0;
f8151e5c
AG		 1538}
1539EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1540
1541/**
1542 * @brief omap_start_dma_chain_transfers - Start the chain
1543 *
1544 * @param chain_id
1545 *
1546 * @return - Success : 0
1547 * Failure : -EINVAL/-EBUSY
1548 */
1549int omap_start_dma_chain_transfers(int chain_id)
1550{
1551 int *channels;
0499bdeb 1552 u32 l, i;
f8151e5c 1553
4d96372e 1554 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1555 printk(KERN_ERR "Invalid chain id\n");
1556 return -EINVAL;
1557 }
1558
1559 channels = dma_linked_lch[chain_id].linked_dmach_q;
1560
1561 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1562 printk(KERN_ERR "Chain is already started\n");
1563 return -EBUSY;
1564 }
1565
1566 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1567 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1568 i++) {
1569 enable_lnk(channels[i]);
1570 omap_enable_channel_irq(channels[i]);
1571 }
1572 } else {
1573 omap_enable_channel_irq(channels[0]);
1574 }
1575
0499bdeb
TL		 1576 l = dma_read(CCR(channels[0]));
1577 l |= (1 << 7);
f8151e5c
AG		 1578 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1579 dma_chan[channels[0]].state = DMA_CH_STARTED;
1580
0499bdeb
TL		 1581 if ((0 == (l & (1 << 24))))
1582 l &= ~(1 << 25);
f8151e5c 1583 else
0499bdeb
TL		 1584 l |= (1 << 25);
1585 dma_write(l, CCR(channels[0]));
f8151e5c
AG		 1586
1587 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
97b7f715 1588
f8151e5c
AG		 1589 return 0;
1590}
1591EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1592
1593/**
1594 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1595 *
1596 * @param chain_id
1597 *
1598 * @return - Success : 0
1599 * Failure : EINVAL
1600 */
1601int omap_stop_dma_chain_transfers(int chain_id)
1602{
1603 int *channels;
0499bdeb 1604 u32 l, i;
f8151e5c
AG		 1605 u32 sys_cf;
1606
1607 /* Check for input params */
4d96372e 1608 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1609 printk(KERN_ERR "Invalid chain id\n");
1610 return -EINVAL;
1611 }
1612
1613 /* Check if the chain exists */
1614 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1615 printk(KERN_ERR "Chain doesn't exists\n");
1616 return -EINVAL;
1617 }
1618 channels = dma_linked_lch[chain_id].linked_dmach_q;
1619
97b7f715
TL		 1620 /*
1621 * DMA Errata:
f8151e5c
AG		 1622 * Special programming model needed to disable DMA before end of block
1623 */
0499bdeb
TL		 1624 sys_cf = dma_read(OCP_SYSCONFIG);
1625 l = sys_cf;
f8151e5c 1626 /* Middle mode reg set no Standby */
0499bdeb
TL		 1627 l &= ~((1 << 12)|(1 << 13));
1628 dma_write(l, OCP_SYSCONFIG);
f8151e5c
AG		 1629
1630 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1631
1632 /* Stop the Channel transmission */
0499bdeb
TL		 1633 l = dma_read(CCR(channels[i]));
1634 l &= ~(1 << 7);
1635 dma_write(l, CCR(channels[i]));
f8151e5c
AG		 1636
1637 /* Disable the link in all the channels */
1638 disable_lnk(channels[i]);
1639 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1640
1641 }
1642 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1643
1644 /* Reset the Queue pointers */
1645 OMAP_DMA_CHAIN_QINIT(chain_id);
1646
1647 /* Errata - put in the old value */
0499bdeb 1648 dma_write(sys_cf, OCP_SYSCONFIG);
97b7f715 1649
f8151e5c
AG		 1650 return 0;
1651}
1652EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1653
1654/* Get the index of the ongoing DMA in chain */
1655/**
1656 * @brief omap_get_dma_chain_index - Get the element and frame index
1657 * of the ongoing DMA in chain
1658 *
1659 * @param chain_id
1660 * @param ei - Element index
1661 * @param fi - Frame index
1662 *
1663 * @return - Success : 0
1664 * Failure : -EINVAL
1665 */
1666int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1667{
1668 int lch;
1669 int *channels;
1670
1671 /* Check for input params */
4d96372e 1672 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1673 printk(KERN_ERR "Invalid chain id\n");
1674 return -EINVAL;
1675 }
1676
1677 /* Check if the chain exists */
1678 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1679 printk(KERN_ERR "Chain doesn't exists\n");
1680 return -EINVAL;
1681 }
1682 if ((!ei) || (!fi))
1683 return -EINVAL;
1684
1685 channels = dma_linked_lch[chain_id].linked_dmach_q;
1686
1687 /* Get the current channel */
1688 lch = channels[dma_linked_lch[chain_id].q_head];
1689
0499bdeb
TL		 1690 *ei = dma_read(CCEN(lch));
1691 *fi = dma_read(CCFN(lch));
f8151e5c
AG		 1692
1693 return 0;
1694}
1695EXPORT_SYMBOL(omap_get_dma_chain_index);
1696
1697/**
1698 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1699 * ongoing DMA in chain
1700 *
1701 * @param chain_id
1702 *
1703 * @return - Success : Destination position
1704 * Failure : -EINVAL
1705 */
1706int omap_get_dma_chain_dst_pos(int chain_id)
1707{
1708 int lch;
1709 int *channels;
1710
1711 /* Check for input params */
4d96372e 1712 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1713 printk(KERN_ERR "Invalid chain id\n");
1714 return -EINVAL;
1715 }
1716
1717 /* Check if the chain exists */
1718 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1719 printk(KERN_ERR "Chain doesn't exists\n");
1720 return -EINVAL;
1721 }
1722
1723 channels = dma_linked_lch[chain_id].linked_dmach_q;
1724
1725 /* Get the current channel */
1726 lch = channels[dma_linked_lch[chain_id].q_head];
1727
0499bdeb 1728 return dma_read(CDAC(lch));
f8151e5c
AG		 1729}
1730EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1731
1732/**
1733 * @brief omap_get_dma_chain_src_pos - Get the source position
1734 * of the ongoing DMA in chain
1735 * @param chain_id
1736 *
1737 * @return - Success : Destination position
1738 * Failure : -EINVAL
1739 */
1740int omap_get_dma_chain_src_pos(int chain_id)
1741{
1742 int lch;
1743 int *channels;
1744
1745 /* Check for input params */
4d96372e 1746 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1747 printk(KERN_ERR "Invalid chain id\n");
1748 return -EINVAL;
1749 }
1750
1751 /* Check if the chain exists */
1752 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1753 printk(KERN_ERR "Chain doesn't exists\n");
1754 return -EINVAL;
1755 }
1756
1757 channels = dma_linked_lch[chain_id].linked_dmach_q;
1758
1759 /* Get the current channel */
1760 lch = channels[dma_linked_lch[chain_id].q_head];
1761
0499bdeb 1762 return dma_read(CSAC(lch));
f8151e5c
AG		 1763}
1764EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
97b7f715 1765#endif /* ifndef CONFIG_ARCH_OMAP1 */
f8151e5c 1766
1a8bfa1e
TL		 1767/*----------------------------------------------------------------------------*/
1768
1769#ifdef CONFIG_ARCH_OMAP1
1770
1771static int omap1_dma_handle_ch(int ch)
1772{
0499bdeb 1773 u32 csr;
1a8bfa1e
TL		 1774
1775 if (enable_1510_mode && ch >= 6) {
1776 csr = dma_chan[ch].saved_csr;
1777 dma_chan[ch].saved_csr = 0;
1778 } else
0499bdeb 1779 csr = dma_read(CSR(ch));
1a8bfa1e
TL		 1780 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1781 dma_chan[ch + 6].saved_csr = csr >> 7;
1782 csr &= 0x7f;
1783 }
1784 if ((csr & 0x3f) == 0)
1785 return 0;
1786 if (unlikely(dma_chan[ch].dev_id == -1)) {
1787 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1788 "%d (CSR %04x)\n", ch, csr);
1789 return 0;
1790 }
7ff879db 1791 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1a8bfa1e
TL		 1792 printk(KERN_WARNING "DMA timeout with device %d\n",
1793 dma_chan[ch].dev_id);
1794 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1795 printk(KERN_WARNING "DMA synchronization event drop occurred "
1796 "with device %d\n", dma_chan[ch].dev_id);
1797 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1798 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1799 if (likely(dma_chan[ch].callback != NULL))
1800 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
97b7f715 1801
1a8bfa1e
TL		 1802 return 1;
1803}
1804
0cd61b68 1805static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e
TL		 1806{
1807 int ch = ((int) dev_id) - 1;
1808 int handled = 0;
1809
1810 for (;;) {
1811 int handled_now = 0;
1812
1813 handled_now += omap1_dma_handle_ch(ch);
1814 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1815 handled_now += omap1_dma_handle_ch(ch + 6);
1816 if (!handled_now)
1817 break;
1818 handled += handled_now;
1819 }
1820
1821 return handled ? IRQ_HANDLED : IRQ_NONE;
1822}
1823
1824#else
1825#define omap1_dma_irq_handler NULL
1826#endif
1827
f8151e5c 1828#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1a8bfa1e
TL		 1829
1830static int omap2_dma_handle_ch(int ch)
1831{
0499bdeb 1832 u32 status = dma_read(CSR(ch));
1a8bfa1e 1833
3151369d
JY		 1834 if (!status) {
1835 if (printk_ratelimit())
97b7f715
TL		 1836 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1837 ch);
0499bdeb 1838 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1839 return 0;
3151369d
JY		 1840 }
1841 if (unlikely(dma_chan[ch].dev_id == -1)) {
1842 if (printk_ratelimit())
1843 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1844 "channel %d\n", status, ch);
1a8bfa1e 1845 return 0;
3151369d 1846 }
1a8bfa1e
TL		 1847 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1848 printk(KERN_INFO
1849 "DMA synchronization event drop occurred with device "
1850 "%d\n", dma_chan[ch].dev_id);
1a8bfa1e
TL		 1851 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
1852 printk(KERN_INFO "DMA transaction error with device %d\n",
1853 dma_chan[ch].dev_id);
7ff879db
TL		 1854 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1855 printk(KERN_INFO "DMA secure error with device %d\n",
1856 dma_chan[ch].dev_id);
1857 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1858 printk(KERN_INFO "DMA misaligned error with device %d\n",
1859 dma_chan[ch].dev_id);
1a8bfa1e 1860
0499bdeb
TL		 1861 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1862 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1863
f8151e5c
AG		 1864 /* If the ch is not chained then chain_id will be -1 */
1865 if (dma_chan[ch].chain_id != -1) {
1866 int chain_id = dma_chan[ch].chain_id;
1867 dma_chan[ch].state = DMA_CH_NOTSTARTED;
0499bdeb 1868 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
f8151e5c
AG		 1869 dma_chan[dma_chan[ch].next_linked_ch].state =
1870 DMA_CH_STARTED;
1871 if (dma_linked_lch[chain_id].chain_mode ==
1872 OMAP_DMA_DYNAMIC_CHAIN)
1873 disable_lnk(ch);
1874
1875 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1876 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1877
0499bdeb 1878 status = dma_read(CSR(ch));
f8151e5c
AG		 1879 }
1880
538528de
JN		 1881 if (likely(dma_chan[ch].callback != NULL))
1882 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
f8151e5c 1883
0499bdeb 1884 dma_write(status, CSR(ch));
1a8bfa1e
TL		 1885
1886 return 0;
1887}
1888
1889/* STATUS register count is from 1-32 while our is 0-31 */
0cd61b68 1890static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e
TL		 1891{
1892 u32 val;
1893 int i;
1894
0499bdeb 1895 val = dma_read(IRQSTATUS_L0);
3151369d
JY		 1896 if (val == 0) {
1897 if (printk_ratelimit())
1898 printk(KERN_WARNING "Spurious DMA IRQ\n");
1899 return IRQ_HANDLED;
1900 }
4d96372e 1901 for (i = 0; i < dma_lch_count && val != 0; i++) {
3151369d
JY		 1902 if (val & 1)
1903 omap2_dma_handle_ch(i);
1904 val >>= 1;
1a8bfa1e
TL		 1905 }
1906
1907 return IRQ_HANDLED;
1908}
1909
1910static struct irqaction omap24xx_dma_irq = {
1911 .name = "DMA",
1912 .handler = omap2_dma_irq_handler,
52e405ea 1913 .flags = IRQF_DISABLED
1a8bfa1e
TL		 1914};
1915
1916#else
1917static struct irqaction omap24xx_dma_irq;
1918#endif
1919
1920/*----------------------------------------------------------------------------*/
5e1c5ff4
TL		 1921
1922static struct lcd_dma_info {
1923 spinlock_t lock;
1924 int reserved;
97b7f715 1925 void (*callback)(u16 status, void *data);
5e1c5ff4
TL		 1926 void *cb_data;
1927
1928 int active;
1929 unsigned long addr, size;
1930 int rotate, data_type, xres, yres;
1931 int vxres;
1932 int mirror;
1933 int xscale, yscale;
1934 int ext_ctrl;
1935 int src_port;
1936 int single_transfer;
1937} lcd_dma;
1938
1939void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1940 int data_type)
1941{
1942 lcd_dma.addr = addr;
1943 lcd_dma.data_type = data_type;
1944 lcd_dma.xres = fb_xres;
1945 lcd_dma.yres = fb_yres;
1946}
97b7f715 1947EXPORT_SYMBOL(omap_set_lcd_dma_b1);
5e1c5ff4
TL		 1948
1949void omap_set_lcd_dma_src_port(int port)
1950{
1951 lcd_dma.src_port = port;
1952}
1953
1954void omap_set_lcd_dma_ext_controller(int external)
1955{
1956 lcd_dma.ext_ctrl = external;
1957}
97b7f715 1958EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
5e1c5ff4
TL		 1959
1960void omap_set_lcd_dma_single_transfer(int single)
1961{
1962 lcd_dma.single_transfer = single;
1963}
97b7f715 1964EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
5e1c5ff4
TL		 1965
1966void omap_set_lcd_dma_b1_rotation(int rotate)
1967{
1968 if (omap_dma_in_1510_mode()) {
1969 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1970 BUG();
1971 return;
1972 }
1973 lcd_dma.rotate = rotate;
1974}
97b7f715 1975EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
5e1c5ff4
TL		 1976
1977void omap_set_lcd_dma_b1_mirror(int mirror)
1978{
1979 if (omap_dma_in_1510_mode()) {
1980 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1981 BUG();
1982 }
1983 lcd_dma.mirror = mirror;
1984}
97b7f715 1985EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
5e1c5ff4
TL		 1986
1987void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1988{
1989 if (omap_dma_in_1510_mode()) {
1990 printk(KERN_ERR "DMA virtual resulotion is not supported "
1991 "in 1510 mode\n");
1992 BUG();
1993 }
1994 lcd_dma.vxres = vxres;
1995}
97b7f715 1996EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
5e1c5ff4
TL		 1997
1998void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1999{
2000 if (omap_dma_in_1510_mode()) {
2001 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2002 BUG();
2003 }
2004 lcd_dma.xscale = xscale;
2005 lcd_dma.yscale = yscale;
2006}
97b7f715 2007EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
5e1c5ff4
TL		 2008
2009static void set_b1_regs(void)
2010{
2011 unsigned long top, bottom;
2012 int es;
2013 u16 w;
2014 unsigned long en, fn;
2015 long ei, fi;
2016 unsigned long vxres;
2017 unsigned int xscale, yscale;
2018
2019 switch (lcd_dma.data_type) {
2020 case OMAP_DMA_DATA_TYPE_S8:
2021 es = 1;
2022 break;
2023 case OMAP_DMA_DATA_TYPE_S16:
2024 es = 2;
2025 break;
2026 case OMAP_DMA_DATA_TYPE_S32:
2027 es = 4;
2028 break;
2029 default:
2030 BUG();
2031 return;
2032 }
2033
2034 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2035 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2036 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2037 BUG_ON(vxres < lcd_dma.xres);
97b7f715
TL		 2038
2039#define PIXADDR(x, y) (lcd_dma.addr + \
2040 ((y) * vxres * yscale + (x) * xscale) * es)
5e1c5ff4 2041#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
97b7f715 2042
5e1c5ff4
TL		 2043 switch (lcd_dma.rotate) {
2044 case 0:
2045 if (!lcd_dma.mirror) {
2046 top = PIXADDR(0, 0);
2047 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2048 /* 1510 DMA requires the bottom address to be 2 more
2049 * than the actual last memory access location. */
2050 if (omap_dma_in_1510_mode() &&
97b7f715
TL		 2051 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2052 bottom += 2;
5e1c5ff4
TL		 2053 ei = PIXSTEP(0, 0, 1, 0);
2054 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2055 } else {
2056 top = PIXADDR(lcd_dma.xres - 1, 0);
2057 bottom = PIXADDR(0, lcd_dma.yres - 1);
2058 ei = PIXSTEP(1, 0, 0, 0);
2059 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2060 }
2061 en = lcd_dma.xres;
2062 fn = lcd_dma.yres;
2063 break;
2064 case 90:
2065 if (!lcd_dma.mirror) {
2066 top = PIXADDR(0, lcd_dma.yres - 1);
2067 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2068 ei = PIXSTEP(0, 1, 0, 0);
2069 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2070 } else {
2071 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2072 bottom = PIXADDR(0, 0);
2073 ei = PIXSTEP(0, 1, 0, 0);
2074 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2075 }
2076 en = lcd_dma.yres;
2077 fn = lcd_dma.xres;
2078 break;
2079 case 180:
2080 if (!lcd_dma.mirror) {
2081 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2082 bottom = PIXADDR(0, 0);
2083 ei = PIXSTEP(1, 0, 0, 0);
2084 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2085 } else {
2086 top = PIXADDR(0, lcd_dma.yres - 1);
2087 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2088 ei = PIXSTEP(0, 0, 1, 0);
2089 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2090 }
2091 en = lcd_dma.xres;
2092 fn = lcd_dma.yres;
2093 break;
2094 case 270:
2095 if (!lcd_dma.mirror) {
2096 top = PIXADDR(lcd_dma.xres - 1, 0);
2097 bottom = PIXADDR(0, lcd_dma.yres - 1);
2098 ei = PIXSTEP(0, 0, 0, 1);
2099 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2100 } else {
2101 top = PIXADDR(0, 0);
2102 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2103 ei = PIXSTEP(0, 0, 0, 1);
2104 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2105 }
2106 en = lcd_dma.yres;
2107 fn = lcd_dma.xres;
2108 break;
2109 default:
2110 BUG();
6cbdc8c5 2111 return; /* Suppress warning about uninitialized vars */
5e1c5ff4
TL		 2112 }
2113
2114 if (omap_dma_in_1510_mode()) {
2115 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2116 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2117 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2118 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2119
2120 return;
2121 }
2122
2123 /* 1610 regs */
2124 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2125 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2126 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2127 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2128
2129 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2130 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2131
2132 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2133 w &= ~0x03;
2134 w |= lcd_dma.data_type;
2135 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2136
2137 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2138 /* Always set the source port as SDRAM for now*/
2139 w &= ~(0x03 << 6);
5e1c5ff4 2140 if (lcd_dma.callback != NULL)
1a8bfa1e 2141 w |= 1 << 1; /* Block interrupt enable */
5e1c5ff4
TL		 2142 else
2143 w &= ~(1 << 1);
2144 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2145
2146 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2147 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2148 return;
2149
2150 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2151 /* Set the double-indexed addressing mode */
2152 w |= (0x03 << 12);
2153 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2154
2155 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2156 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2157 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2158}
2159
0cd61b68 2160static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
5e1c5ff4
TL		 2161{
2162 u16 w;
2163
2164 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2165 if (unlikely(!(w & (1 << 3)))) {
2166 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2167 return IRQ_NONE;
2168 }
2169 /* Ack the IRQ */
2170 w |= (1 << 3);
2171 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2172 lcd_dma.active = 0;
2173 if (lcd_dma.callback != NULL)
2174 lcd_dma.callback(w, lcd_dma.cb_data);
2175
2176 return IRQ_HANDLED;
2177}
2178
97b7f715 2179int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
5e1c5ff4
TL		 2180 void *data)
2181{
2182 spin_lock_irq(&lcd_dma.lock);
2183 if (lcd_dma.reserved) {
2184 spin_unlock_irq(&lcd_dma.lock);
2185 printk(KERN_ERR "LCD DMA channel already reserved\n");
2186 BUG();
2187 return -EBUSY;
2188 }
2189 lcd_dma.reserved = 1;
2190 spin_unlock_irq(&lcd_dma.lock);
2191 lcd_dma.callback = callback;
2192 lcd_dma.cb_data = data;
2193 lcd_dma.active = 0;
2194 lcd_dma.single_transfer = 0;
2195 lcd_dma.rotate = 0;
2196 lcd_dma.vxres = 0;
2197 lcd_dma.mirror = 0;
2198 lcd_dma.xscale = 0;
2199 lcd_dma.yscale = 0;
2200 lcd_dma.ext_ctrl = 0;
2201 lcd_dma.src_port = 0;
2202
2203 return 0;
2204}
97b7f715 2205EXPORT_SYMBOL(omap_request_lcd_dma);
5e1c5ff4
TL		 2206
2207void omap_free_lcd_dma(void)
2208{
2209 spin_lock(&lcd_dma.lock);
2210 if (!lcd_dma.reserved) {
2211 spin_unlock(&lcd_dma.lock);
2212 printk(KERN_ERR "LCD DMA is not reserved\n");
2213 BUG();
2214 return;
2215 }
2216 if (!enable_1510_mode)
1a8bfa1e
TL		 2217 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2218 OMAP1610_DMA_LCD_CCR);
5e1c5ff4
TL		 2219 lcd_dma.reserved = 0;
2220 spin_unlock(&lcd_dma.lock);
2221}
97b7f715 2222EXPORT_SYMBOL(omap_free_lcd_dma);
5e1c5ff4
TL		 2223
2224void omap_enable_lcd_dma(void)
2225{
2226 u16 w;
2227
97b7f715
TL		 2228 /*
2229 * Set the Enable bit only if an external controller is
5e1c5ff4
TL		 2230 * connected. Otherwise the OMAP internal controller will
2231 * start the transfer when it gets enabled.
2232 */
2233 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2234 return;
bb13b5fd
TL		 2235
2236 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2237 w |= 1 << 8;
2238 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2239
92105bb7
TL		 2240 lcd_dma.active = 1;
2241
5e1c5ff4
TL		 2242 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2243 w |= 1 << 7;
2244 omap_writew(w, OMAP1610_DMA_LCD_CCR);
5e1c5ff4 2245}
97b7f715 2246EXPORT_SYMBOL(omap_enable_lcd_dma);
5e1c5ff4
TL		 2247
2248void omap_setup_lcd_dma(void)
2249{
2250 BUG_ON(lcd_dma.active);
2251 if (!enable_1510_mode) {
2252 /* Set some reasonable defaults */
2253 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2254 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2255 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2256 }
2257 set_b1_regs();
2258 if (!enable_1510_mode) {
2259 u16 w;
2260
2261 w = omap_readw(OMAP1610_DMA_LCD_CCR);
97b7f715
TL		 2262 /*
2263 * If DMA was already active set the end_prog bit to have
5e1c5ff4
TL		 2264 * the programmed register set loaded into the active
2265 * register set.
2266 */
2267 w |= 1 << 11; /* End_prog */
2268 if (!lcd_dma.single_transfer)
97b7f715 2269 w |= (3 << 8); /* Auto_init, repeat */
5e1c5ff4
TL		 2270 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2271 }
2272}
97b7f715 2273EXPORT_SYMBOL(omap_setup_lcd_dma);
5e1c5ff4
TL		 2274
2275void omap_stop_lcd_dma(void)
2276{
bb13b5fd
TL		 2277 u16 w;
2278
5e1c5ff4 2279 lcd_dma.active = 0;
bb13b5fd
TL		 2280 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2281 return;
2282
2283 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2284 w &= ~(1 << 7);
2285 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2286
2287 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2288 w &= ~(1 << 8);
2289 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
5e1c5ff4 2290}
97b7f715 2291EXPORT_SYMBOL(omap_stop_lcd_dma);
5e1c5ff4 2292
1a8bfa1e 2293/*----------------------------------------------------------------------------*/
bb13b5fd 2294
5e1c5ff4
TL		 2295static int __init omap_init_dma(void)
2296{
2297 int ch, r;
2298
0499bdeb
TL		 2299 if (cpu_class_is_omap1()) {
2300 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
4d96372e 2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
0499bdeb
TL		 2302 } else if (cpu_is_omap24xx()) {
2303 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
4d96372e 2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
0499bdeb
TL		 2305 } else if (cpu_is_omap34xx()) {
2306 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2308 } else {
2309 pr_err("DMA init failed for unsupported omap\n");
2310 return -ENODEV;
2311 }
4d96372e
TL		 2312
2313 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2314 GFP_KERNEL);
2315 if (!dma_chan)
2316 return -ENOMEM;
2317
2318 if (cpu_class_is_omap2()) {
2319 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2320 dma_lch_count, GFP_KERNEL);
2321 if (!dma_linked_lch) {
2322 kfree(dma_chan);
2323 return -ENOMEM;
2324 }
2325 }
2326
1a8bfa1e
TL		 2327 if (cpu_is_omap15xx()) {
2328 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
5e1c5ff4
TL		 2329 dma_chan_count = 9;
2330 enable_1510_mode = 1;
2331 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2332 printk(KERN_INFO "OMAP DMA hardware version %d\n",
0499bdeb 2333 dma_read(HW_ID));
5e1c5ff4 2334 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
0499bdeb
TL		 2335 (dma_read(CAPS_0_U) << 16) |
2336 dma_read(CAPS_0_L),
2337 (dma_read(CAPS_1_U) << 16) |
2338 dma_read(CAPS_1_L),
2339 dma_read(CAPS_2), dma_read(CAPS_3),
2340 dma_read(CAPS_4));
5e1c5ff4
TL		 2341 if (!enable_1510_mode) {
2342 u16 w;
2343
2344 /* Disable OMAP 3.0/3.1 compatibility mode. */
0499bdeb 2345 w = dma_read(GSCR);
5e1c5ff4 2346 w |= 1 << 3;
0499bdeb 2347 dma_write(w, GSCR);
5e1c5ff4
TL		 2348 dma_chan_count = 16;
2349 } else
2350 dma_chan_count = 9;
b5beef5d
ID		 2351 if (cpu_is_omap16xx()) {
2352 u16 w;
2353
2354 /* this would prevent OMAP sleep */
2355 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2356 w &= ~(1 << 8);
2357 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2358 }
f8151e5c 2359 } else if (cpu_class_is_omap2()) {
0499bdeb 2360 u8 revision = dma_read(REVISION) & 0xff;
1a8bfa1e
TL		 2361 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2362 revision >> 4, revision & 0xf);
4d96372e 2363 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
5e1c5ff4
TL		 2364 } else {
2365 dma_chan_count = 0;
2366 return 0;
2367 }
2368
5e1c5ff4
TL		 2369 spin_lock_init(&lcd_dma.lock);
2370 spin_lock_init(&dma_chan_lock);
5e1c5ff4
TL		 2371
2372 for (ch = 0; ch < dma_chan_count; ch++) {
1a8bfa1e 2373 omap_clear_dma(ch);
5e1c5ff4
TL		 2374 dma_chan[ch].dev_id = -1;
2375 dma_chan[ch].next_lch = -1;
2376
2377 if (ch >= 6 && enable_1510_mode)
2378 continue;
2379
1a8bfa1e 2380 if (cpu_class_is_omap1()) {
97b7f715
TL		 2381 /*
2382 * request_irq() doesn't like dev_id (ie. ch) being
2383 * zero, so we have to kludge around this.
2384 */
1a8bfa1e
TL		 2385 r = request_irq(omap1_dma_irq[ch],
2386 omap1_dma_irq_handler, 0, "DMA",
2387 (void *) (ch + 1));
2388 if (r != 0) {
2389 int i;
2390
2391 printk(KERN_ERR "unable to request IRQ %d "
2392 "for DMA (error %d)\n",
2393 omap1_dma_irq[ch], r);
2394 for (i = 0; i < ch; i++)
2395 free_irq(omap1_dma_irq[i],
2396 (void *) (i + 1));
2397 return r;
2398 }
2399 }
2400 }
2401
f8151e5c
AG		 2402 if (cpu_is_omap2430() || cpu_is_omap34xx())
2403 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2404 DMA_DEFAULT_FIFO_DEPTH, 0);
2405
2406 if (cpu_class_is_omap2())
1a8bfa1e
TL		 2407 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2408
2409 /* FIXME: Update LCD DMA to work on 24xx */
2410 if (cpu_class_is_omap1()) {
2411 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2412 "LCD DMA", NULL);
5e1c5ff4
TL		 2413 if (r != 0) {
2414 int i;
2415
1a8bfa1e
TL		 2416 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2417 "(error %d)\n", r);
2418 for (i = 0; i < dma_chan_count; i++)
2419 free_irq(omap1_dma_irq[i], (void *) (i + 1));
5e1c5ff4
TL		 2420 return r;
2421 }
2422 }
5e1c5ff4 2423
5e1c5ff4
TL		 2424 return 0;
2425}
2426
2427arch_initcall(omap_init_dma);
2428
5e1c5ff4 2429
Clone of davem's net-next-2.6 tree