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52c543f9 QJ |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | */ | |
4 | ||
5 | /* | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_ARCH_MXC_IRQS_H__ | |
12 | #define __ASM_ARCH_MXC_IRQS_H__ | |
13 | ||
9d631b83 SH |
14 | /* |
15 | * So far all i.MX SoCs have 64 internal interrupts | |
16 | */ | |
17 | #define MXC_INTERNAL_IRQS 64 | |
18 | ||
19 | #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS | |
20 | ||
21 | #if defined CONFIG_ARCH_MX1 | |
22 | #define MXC_GPIO_IRQS (32 * 4) | |
23 | #elif defined CONFIG_ARCH_MX2 | |
24 | #define MXC_GPIO_IRQS (32 * 6) | |
25 | #elif defined CONFIG_ARCH_MX3 | |
26 | #define MXC_GPIO_IRQS (32 * 3) | |
27 | #endif | |
28 | ||
29 | /* | |
30 | * The next 16 interrupts are for board specific purposes. Since | |
31 | * the kernel can only run on one machine at a time, we can re-use | |
32 | * these. If you need more, increase MXC_BOARD_IRQS, but keep it | |
33 | * within sensible limits. | |
34 | */ | |
35 | #define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) | |
36 | #define MXC_BOARD_IRQS 16 | |
37 | ||
5296b56d GL |
38 | #define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) |
39 | ||
40 | #ifdef CONFIG_MX3_IPU_IRQS | |
41 | #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS | |
42 | #else | |
43 | #define MX3_IPU_IRQS 0 | |
44 | #endif | |
45 | ||
46 | #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) | |
9d631b83 | 47 | |
3f203016 | 48 | extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); |
52c543f9 | 49 | |
d7927e19 PZ |
50 | /* all normal IRQs can be FIQs */ |
51 | #define FIQ_START 0 | |
52 | /* switch betwean IRQ and FIQ */ | |
53 | extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); | |
54 | ||
f304fc42 | 55 | #endif /* __ASM_ARCH_MXC_IRQS_H__ */ |