[net-next-2.6.git] / arch / arm / plat-iop / pci.c

/*
 * arch/arm/plat-iop/pci.c
 *
 * PCI support for the Intel IOP32X and IOP33X processors
 *
 * Author: Rory Bolt <rorybolt@pacbell.net>
 * Copyright (C) 2002 Rory Bolt
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/hardware.h>
#include <asm/mach/pci.h>
#include <asm/hardware/iop3xx.h>

// #define DEBUG

#ifdef DEBUG
#define  DBG(x...) printk(x)
#else
#define  DBG(x...) do { } while (0)
#endif

/*
 * This routine builds either a type0 or type1 configuration command.  If the
 * bus is on the 803xx then a type0 made, else a type1 is created.
 */
static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
{
	struct pci_sys_data *sys = bus->sysdata;
	u32 addr;

	if (sys->busnr == bus->number)
		addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
	else
		addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;

	addr |=	PCI_FUNC(devfn) << 8 | (where & ~3);

	return addr;
}

/*
 * This routine checks the status of the last configuration cycle.  If an error
 * was detected it returns a 1, else it returns a 0.  The errors being checked
 * are parity, master abort, target abort (master and target).  These types of
 * errors occur during a config cycle where there is no device, like during
 * the discovery stage.
 */
static int iop3xx_pci_status(void)
{
	unsigned int status;
	int ret = 0;

	/*
	 * Check the status registers.
	 */
	status = *IOP3XX_ATUSR;
	if (status & 0xf900) {
		DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
		*IOP3XX_ATUSR = status & 0xf900;
		ret = 1;
	}

	status = *IOP3XX_ATUISR;
	if (status & 0x679f) {
		DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
		*IOP3XX_ATUISR = status & 0x679f;
		ret = 1;
	}

	return ret;
}

/*
 * Simply write the address register and read the configuration
 * data.  Note that the 4 nop's ensure that we are able to handle
 * a delayed abort (in theory.)
 */
static inline u32 iop3xx_read(unsigned long addr)
{
	u32 val;

	__asm__ __volatile__(
		"str	%1, [%2]\n\t"
		"ldr	%0, [%3]\n\t"
		"nop\n\t"
		"nop\n\t"
		"nop\n\t"
		"nop\n\t"
		: "=r" (val)
		: "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));

	return val;
}

/*
 * The read routines must check the error status of the last configuration
 * cycle.  If there was an error, the routine returns all hex f's.
 */
static int
iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
		int size, u32 *value)
{
	unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
	u32 val = iop3xx_read(addr) >> ((where & 3) * 8);

	if (iop3xx_pci_status())
		val = 0xffffffff;

	*value = val;

	return PCIBIOS_SUCCESSFUL;
}

static int
iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
		int size, u32 value)
{
	unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
	u32 val;

	if (size != 4) {
		val = iop3xx_read(addr);
		if (iop3xx_pci_status())
			return PCIBIOS_SUCCESSFUL;

		where = (where & 3) * 8;

		if (size == 1)
			val &= ~(0xff << where);
		else
			val &= ~(0xffff << where);

		*IOP3XX_OCCDR = val | value << where;
	} else {
		asm volatile(
			"str	%1, [%2]\n\t"
			"str	%0, [%3]\n\t"
			"nop\n\t"
			"nop\n\t"
			"nop\n\t"
			"nop\n\t"
			:
			: "r" (value), "r" (addr),
			  "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
	}

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops iop3xx_ops = {
	.read	= iop3xx_read_config,
	.write	= iop3xx_write_config,
};

/*
 * When a PCI device does not exist during config cycles, the 80200 gets a
 * bus error instead of returning 0xffffffff. This handler simply returns.
 */
static int
iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
	DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
		addr, fsr, regs->ARM_pc, regs->ARM_lr);

	/*
	 * If it was an imprecise abort, then we need to correct the
	 * return address to be _after_ the instruction.
	 */
	if (fsr & (1 << 10))
		regs->ARM_pc += 4;

	return 0;
}

int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
{
	struct resource *res;

	if (nr != 0)
		return 0;

	res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
	if (!res)
		panic("PCI: unable to alloc resources");

	res[0].start = IOP3XX_PCI_LOWER_IO_PA;
	res[0].end   = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
	res[0].name  = "IOP3XX PCI I/O Space";
	res[0].flags = IORESOURCE_IO;
	request_resource(&ioport_resource, &res[0]);

	res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
	res[1].end   = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
	res[1].name  = "IOP3XX PCI Memory Space";
	res[1].flags = IORESOURCE_MEM;
	request_resource(&iomem_resource, &res[1]);

	sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
	sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA;

	sys->resource[0] = &res[0];
	sys->resource[1] = &res[1];
	sys->resource[2] = NULL;

	return 1;
}

struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
	return pci_scan_bus(sys->busnr, &iop3xx_ops, sys);
}

void __init iop3xx_atu_setup(void)
{
	/* BAR 0 ( Disabled ) */
	*IOP3XX_IAUBAR0 = 0x0;
	*IOP3XX_IABAR0  = 0x0;
	*IOP3XX_IATVR0  = 0x0;
	*IOP3XX_IALR0   = 0x0;

	/* BAR 1 ( Disabled ) */
	*IOP3XX_IAUBAR1 = 0x0;
	*IOP3XX_IABAR1  = 0x0;
	*IOP3XX_IALR1   = 0x0;

	/* BAR 2 (1:1 mapping with Physical RAM) */
	/* Set limit and enable */
	*IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1;
	*IOP3XX_IAUBAR2 = 0x0;

	/* Align the inbound bar with the base of memory */
	*IOP3XX_IABAR2 = PHYS_OFFSET |
			       PCI_BASE_ADDRESS_MEM_TYPE_64 |
			       PCI_BASE_ADDRESS_MEM_PREFETCH;

	*IOP3XX_IATVR2 = PHYS_OFFSET;

	/* Outbound window 0 */
	*IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA;
	*IOP3XX_OUMWTVR0 = 0;

	/* Outbound window 1 */
	*IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE;
	*IOP3XX_OUMWTVR1 = 0;

	/* BAR 3 ( Disabled ) */
	*IOP3XX_IAUBAR3 = 0x0;
	*IOP3XX_IABAR3  = 0x0;
	*IOP3XX_IATVR3  = 0x0;
	*IOP3XX_IALR3   = 0x0;

	/* Setup the I/O Bar
	 */
	*IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;;

	/* Enable inbound and outbound cycles
	 */
	*IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
			       PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
	*IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN;
}

void __init iop3xx_atu_disable(void)
{
	*IOP3XX_ATUCMD = 0;
	*IOP3XX_ATUCR = 0;

	/* wait for cycles to quiesce */
	while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY |
				     IOP3XX_PCSR_IN_Q_BUSY))
		cpu_relax();

	/* BAR 0 ( Disabled ) */
	*IOP3XX_IAUBAR0 = 0x0;
	*IOP3XX_IABAR0  = 0x0;
	*IOP3XX_IATVR0  = 0x0;
	*IOP3XX_IALR0   = 0x0;

	/* BAR 1 ( Disabled ) */
	*IOP3XX_IAUBAR1 = 0x0;
	*IOP3XX_IABAR1  = 0x0;
	*IOP3XX_IALR1   = 0x0;

	/* BAR 2 ( Disabled ) */
	*IOP3XX_IAUBAR2 = 0x0;
	*IOP3XX_IABAR2  = 0x0;
	*IOP3XX_IATVR2  = 0x0;
	*IOP3XX_IALR2   = 0x0;

	/* BAR 3 ( Disabled ) */
	*IOP3XX_IAUBAR3 = 0x0;
	*IOP3XX_IABAR3  = 0x0;
	*IOP3XX_IATVR3  = 0x0;
	*IOP3XX_IALR3   = 0x0;

	/* Clear the outbound windows */
	*IOP3XX_OIOWTVR  = 0;

	/* Outbound window 0 */
	*IOP3XX_OMWTVR0 = 0;
	*IOP3XX_OUMWTVR0 = 0;

	/* Outbound window 1 */
	*IOP3XX_OMWTVR1 = 0;
	*IOP3XX_OUMWTVR1 = 0;
}

/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
int init_atu;

void iop3xx_pci_preinit(void)
{
	if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
		iop3xx_atu_disable();
		iop3xx_atu_setup();
	}

	DBG("PCI:  Intel 803xx PCI init code.\n");
	DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
	DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
			*IOP3XX_OMWTVR0,
			*IOP3XX_OIOWTVR);
	DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
	DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
			*IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
	DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
	DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
			*IOP3XX_IABAR1, *IOP3XX_IALR1);
	DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
			*IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
	DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
			*IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
	DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
			*IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);

	hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
}

/* allow init_atu to be user overridden */
static int __init iop3xx_init_atu_setup(char *str)
{
	init_atu = IOP3XX_INIT_ATU_DEFAULT;
	if (str) {
		while (*str != '\0') {
			switch (*str) {
			case 'y':
			case 'Y':
				init_atu = IOP3XX_INIT_ATU_ENABLE;
				break;
			case 'n':
			case 'N':
				init_atu = IOP3XX_INIT_ATU_DISABLE;
				break;
			case ',':
			case '=':
				break;
			default:
				printk(KERN_DEBUG "\"%s\" malformed at "
					    "character: \'%c\'",
					    __FUNCTION__,
					    *str);
				*(str + 1) = '\0';
			}
			str++;
		}
	}

	return 1;
}

__setup("iop3xx_init_atu", iop3xx_init_atu_setup);
Commit	Line	Data
0cb015f9 LB	1	/*
	2	* arch/arm/plat-iop/pci.c
	3	*
	4	* PCI support for the Intel IOP32X and IOP33X processors
	5	*
	6	* Author: Rory Bolt <rorybolt@pacbell.net>
	7	* Copyright (C) 2002 Rory Bolt
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/pci.h>
	16	#include <linux/slab.h>
	17	#include <linux/mm.h>
	18	#include <linux/init.h>
	19	#include <linux/ioport.h>
	20	#include <asm/io.h>
	21	#include <asm/irq.h>
e8edc6e0	22	#include <asm/signal.h>
0cb015f9 LB	23	#include <asm/system.h>
	24	#include <asm/hardware.h>
	25	#include <asm/mach/pci.h>
	26	#include <asm/hardware/iop3xx.h>
	27
	28	// #define DEBUG
	29
	30	#ifdef DEBUG
	31	#define DBG(x...) printk(x)
	32	#else
	33	#define DBG(x...) do { } while (0)
	34	#endif
	35
	36	/*
	37	* This routine builds either a type0 or type1 configuration command. If the
	38	* bus is on the 803xx then a type0 made, else a type1 is created.
	39	*/
	40	static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
	41	{
	42	struct pci_sys_data *sys = bus->sysdata;
	43	u32 addr;
	44
	45	if (sys->busnr == bus->number)
	46	addr = 1 << (PCI_SLOT(devfn) + 16) \| (PCI_SLOT(devfn) << 11);
	47	else
	48	addr = bus->number << 16 \| PCI_SLOT(devfn) << 11 \| 1;
	49
	50	addr \|= PCI_FUNC(devfn) << 8 \| (where & ~3);
	51
	52	return addr;
	53	}
	54
	55	/*
	56	* This routine checks the status of the last configuration cycle. If an error
	57	* was detected it returns a 1, else it returns a 0. The errors being checked
	58	* are parity, master abort, target abort (master and target). These types of
e90ddd81	59	* errors occur during a config cycle where there is no device, like during
0cb015f9 LB	60	* the discovery stage.
	61	*/
	62	static int iop3xx_pci_status(void)
	63	{
	64	unsigned int status;
	65	int ret = 0;
	66
	67	/*
	68	* Check the status registers.
	69	*/
	70	status = *IOP3XX_ATUSR;
	71	if (status & 0xf900) {
	72	DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
	73	*IOP3XX_ATUSR = status & 0xf900;
	74	ret = 1;
	75	}
	76
	77	status = *IOP3XX_ATUISR;
	78	if (status & 0x679f) {
	79	DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
	80	*IOP3XX_ATUISR = status & 0x679f;
	81	ret = 1;
	82	}
	83
	84	return ret;
	85	}
	86
	87	/*
	88	* Simply write the address register and read the configuration
	89	* data. Note that the 4 nop's ensure that we are able to handle
	90	* a delayed abort (in theory.)
	91	*/
	92	static inline u32 iop3xx_read(unsigned long addr)
	93	{
	94	u32 val;
	95
	96	__asm__ __volatile__(
	97	"str %1, [%2]\n\t"
	98	"ldr %0, [%3]\n\t"
	99	"nop\n\t"
	100	"nop\n\t"
	101	"nop\n\t"
	102	"nop\n\t"
	103	: "=r" (val)
	104	: "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
	105
	106	return val;
	107	}
	108
	109	/*
	110	* The read routines must check the error status of the last configuration
	111	* cycle. If there was an error, the routine returns all hex f's.
	112	*/
	113	static int
	114	iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
	115	int size, u32 *value)
	116	{
	117	unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
	118	u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
	119
	120	if (iop3xx_pci_status())
	121	val = 0xffffffff;
	122
	123	*value = val;
124
125	return PCIBIOS_SUCCESSFUL;
126	}
127
128	static int
129	iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
130	int size, u32 value)
131	{
132	unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
133	u32 val;
134
135	if (size != 4) {
136	val = iop3xx_read(addr);
137	if (iop3xx_pci_status())
138	return PCIBIOS_SUCCESSFUL;
139
140	where = (where & 3) * 8;
141
142	if (size == 1)
143	val &= ~(0xff << where);
144	else
145	val &= ~(0xffff << where);
146
147	*IOP3XX_OCCDR = val \| value << where;
148	} else {
149	asm volatile(
150	"str %1, [%2]\n\t"
151	"str %0, [%3]\n\t"
152	"nop\n\t"
153	"nop\n\t"
154	"nop\n\t"
155	"nop\n\t"
156	:
157	: "r" (value), "r" (addr),
158	"r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
159	}
160
161	return PCIBIOS_SUCCESSFUL;
162	}
163
164	static struct pci_ops iop3xx_ops = {
165	.read = iop3xx_read_config,
166	.write = iop3xx_write_config,
167	};
168
169	/*
170	* When a PCI device does not exist during config cycles, the 80200 gets a
171	* bus error instead of returning 0xffffffff. This handler simply returns.
172	*/
173	static int
174	iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
175	{
176	DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
177	addr, fsr, regs->ARM_pc, regs->ARM_lr);
178
179	/*
180	* If it was an imprecise abort, then we need to correct the
181	* return address to be _after_ the instruction.
182	*/
183	if (fsr & (1 << 10))
184	regs->ARM_pc += 4;
185
186	return 0;
187	}
188
189	int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
190	{
191	struct resource *res;
192
193	if (nr != 0)
194	return 0;
195
196	res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
197	if (!res)
198	panic("PCI: unable to alloc resources");
199
6df26700 DW	200	res[0].start = IOP3XX_PCI_LOWER_IO_PA;
6df26700 DW	201	res[0].end = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
0cb015f9 LB	202	res[0].name = "IOP3XX PCI I/O Space";
	203	res[0].flags = IORESOURCE_IO;
	204	request_resource(&ioport_resource, &res[0]);
	205
	206	res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
	207	res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
	208	res[1].name = "IOP3XX PCI Memory Space";
	209	res[1].flags = IORESOURCE_MEM;
	210	request_resource(&iomem_resource, &res[1]);
	211
	212	sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
6df26700	213	sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA;
0cb015f9 LB	214
	215	sys->resource[0] = &res[0];
	216	sys->resource[1] = &res[1];
	217	sys->resource[2] = NULL;
	218
	219	return 1;
	220	}
	221
	222	struct pci_bus iop3xx_pci_scan_bus(int nr, struct pci_sys_data sys)
	223	{
	224	return pci_scan_bus(sys->busnr, &iop3xx_ops, sys);
	225	}
	226
e90ddd81 DW	227	void __init iop3xx_atu_setup(void)
	228	{
	229	/* BAR 0 ( Disabled ) */
	230	*IOP3XX_IAUBAR0 = 0x0;
	231	*IOP3XX_IABAR0 = 0x0;
	232	*IOP3XX_IATVR0 = 0x0;
	233	*IOP3XX_IALR0 = 0x0;
	234
	235	/* BAR 1 ( Disabled ) */
	236	*IOP3XX_IAUBAR1 = 0x0;
	237	*IOP3XX_IABAR1 = 0x0;
	238	*IOP3XX_IALR1 = 0x0;
	239
	240	/* BAR 2 (1:1 mapping with Physical RAM) */
	241	/* Set limit and enable */
	242	*IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1;
	243	*IOP3XX_IAUBAR2 = 0x0;
	244
	245	/* Align the inbound bar with the base of memory */
	246	*IOP3XX_IABAR2 = PHYS_OFFSET \|
	247	PCI_BASE_ADDRESS_MEM_TYPE_64 \|
	248	PCI_BASE_ADDRESS_MEM_PREFETCH;
	249
	250	*IOP3XX_IATVR2 = PHYS_OFFSET;
	251
	252	/* Outbound window 0 */
	253	*IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA;
	254	*IOP3XX_OUMWTVR0 = 0;
	255
	256	/* Outbound window 1 */
	257	*IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE;
	258	*IOP3XX_OUMWTVR1 = 0;
	259
	260	/* BAR 3 ( Disabled ) */
	261	*IOP3XX_IAUBAR3 = 0x0;
	262	*IOP3XX_IABAR3 = 0x0;
	263	*IOP3XX_IATVR3 = 0x0;
	264	*IOP3XX_IALR3 = 0x0;
	265
	266	/* Setup the I/O Bar
	267	*/
	268	*IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;;
	269
	270	/* Enable inbound and outbound cycles
	271	*/
	272	*IOP3XX_ATUCMD \|= PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER \|
	273	PCI_COMMAND_PARITY \| PCI_COMMAND_SERR;
	274	*IOP3XX_ATUCR \|= IOP3XX_ATUCR_OUT_EN;
	275	}
	276
	277	void __init iop3xx_atu_disable(void)
	278	{
	279	*IOP3XX_ATUCMD = 0;
	280	*IOP3XX_ATUCR = 0;
	281
	282	/* wait for cycles to quiesce */
	283	while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY \|
	284	IOP3XX_PCSR_IN_Q_BUSY))
	285	cpu_relax();
	286
	287	/* BAR 0 ( Disabled ) */
	288	*IOP3XX_IAUBAR0 = 0x0;
	289	*IOP3XX_IABAR0 = 0x0;
	290	*IOP3XX_IATVR0 = 0x0;
291	*IOP3XX_IALR0 = 0x0;
292
293	/* BAR 1 ( Disabled ) */
294	*IOP3XX_IAUBAR1 = 0x0;
295	*IOP3XX_IABAR1 = 0x0;
296	*IOP3XX_IALR1 = 0x0;
297
298	/* BAR 2 ( Disabled ) */
299	*IOP3XX_IAUBAR2 = 0x0;
300	*IOP3XX_IABAR2 = 0x0;
301	*IOP3XX_IATVR2 = 0x0;
302	*IOP3XX_IALR2 = 0x0;
303
304	/* BAR 3 ( Disabled ) */
305	*IOP3XX_IAUBAR3 = 0x0;
306	*IOP3XX_IABAR3 = 0x0;
307	*IOP3XX_IATVR3 = 0x0;
308	*IOP3XX_IALR3 = 0x0;
309
310	/* Clear the outbound windows */
311	*IOP3XX_OIOWTVR = 0;
312
313	/* Outbound window 0 */
314	*IOP3XX_OMWTVR0 = 0;
315	*IOP3XX_OUMWTVR0 = 0;
316
317	/* Outbound window 1 */
318	*IOP3XX_OMWTVR1 = 0;
319	*IOP3XX_OUMWTVR1 = 0;
320	}
321
322	/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
323	int init_atu;
324
0cb015f9 LB	325	void iop3xx_pci_preinit(void)
0cb015f9 LB	326	{
e90ddd81 DW	327	if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
	328	iop3xx_atu_disable();
	329	iop3xx_atu_setup();
	330	}
	331
0cb015f9 LB	332	DBG("PCI: Intel 803xx PCI init code.\n");
	333	DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
	334	DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
	335	*IOP3XX_OMWTVR0,
	336	*IOP3XX_OIOWTVR);
	337	DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
	338	DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
	339	IOP3XX_IABAR0, IOP3XX_IALR0, *IOP3XX_IATVR0);
	340	DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
	341	DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
	342	IOP3XX_IABAR1, IOP3XX_IALR1);
	343	DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
	344	IOP3XX_ERBAR, IOP3XX_ERLR, *IOP3XX_ERTVR);
	345	DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
	346	IOP3XX_IABAR2, IOP3XX_IALR2, *IOP3XX_IATVR2);
	347	DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
	348	IOP3XX_IABAR3, IOP3XX_IALR3, *IOP3XX_IATVR3);
	349
	350	hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
	351	}
e90ddd81 DW	352
	353	/* allow init_atu to be user overridden */
	354	static int __init iop3xx_init_atu_setup(char *str)
	355	{
	356	init_atu = IOP3XX_INIT_ATU_DEFAULT;
	357	if (str) {
	358	while (*str != '\0') {
	359	switch (*str) {
	360	case 'y':
	361	case 'Y':
	362	init_atu = IOP3XX_INIT_ATU_ENABLE;
	363	break;
	364	case 'n':
	365	case 'N':
	366	init_atu = IOP3XX_INIT_ATU_DISABLE;
	367	break;
	368	case ',':
	369	case '=':
	370	break;
	371	default:
	372	printk(KERN_DEBUG "\"%s\" malformed at "
	373	"character: \'%c\'",
	374	__FUNCTION__,
	375	*str);
	376	*(str + 1) = '\0';
	377	}
	378	str++;
	379	}
	380	}
	381
	382	return 1;
	383	}
	384
	385	__setup("iop3xx_init_atu", iop3xx_init_atu_setup);
	386