[net-next-2.6.git] / arch / arm / mm / proc-v7.S

/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#define TTB_S		(1 << 1)
#define TTB_RGN_NC	(0 << 3)
#define TTB_RGN_OC_WBWA	(1 << 3)
#define TTB_RGN_OC_WT	(2 << 3)
#define TTB_RGN_OC_WB	(3 << 3)
#define TTB_NOS		(1 << 5)
#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
#define TTB_IRGN_WB	((1 << 0) | (1 << 6))

#ifndef CONFIG_SMP
/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
#else
/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
#endif

ENTRY(cpu_v7_proc_init)
	mov	pc, lr
ENDPROC(cpu_v7_proc_init)

ENTRY(cpu_v7_proc_fin)
	mov	pc, lr
ENDPROC(cpu_v7_proc_fin)

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 *
 *	It is assumed that:
 */
	.align	5
ENTRY(cpu_v7_reset)
	mov	pc, r0
ENDPROC(cpu_v7_reset)

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	mov	pc, lr
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
	dcache_line_size r2, r3
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

/*
 *	cpu_v7_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys
 *
 *	- pgd_phys - physical address of new TTB
 *
 *	It is assumed that:
 *	- we are not using split page tables
 */
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
	mov	r2, #0
	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
	orr	r0, r0, #TTB_FLAGS
#ifdef CONFIG_ARM_ERRATA_430973
	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
#endif
	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
	isb
1:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
	isb
	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
	isb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_switch_mm)

/*
 *	cpu_v7_set_pte_ext(ptep, pte)
 *
 *	Set a level 2 translation table entry.
 *
 *	- ptep  - pointer to level 2 translation table entry
 *		  (hardware version is stored at -1024 bytes)
 *	- pte   - PTE value to store
 *	- ext	- value for extended PTE bits
 */
ENTRY(cpu_v7_set_pte_ext)
#ifdef CONFIG_MMU
 ARM(	str	r1, [r0], #-2048	)	@ linux version
 THUMB(	str	r1, [r0]		)	@ linux version
 THUMB(	sub	r0, r0, #2048		)

	bic	r3, r1, #0x000003f0
	bic	r3, r3, #PTE_TYPE_MASK
	orr	r3, r3, r2
	orr	r3, r3, #PTE_EXT_AP0 | 2

	tst	r1, #1 << 4
	orrne	r3, r3, #PTE_EXT_TEX(1)

	tst	r1, #L_PTE_WRITE
	tstne	r1, #L_PTE_DIRTY
	orreq	r3, r3, #PTE_EXT_APX

	tst	r1, #L_PTE_USER
	orrne	r3, r3, #PTE_EXT_AP1
	tstne	r3, #PTE_EXT_APX
	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0

	tst	r1, #L_PTE_EXEC
	orreq	r3, r3, #PTE_EXT_XN

	tst	r1, #L_PTE_YOUNG
	tstne	r1, #L_PTE_PRESENT
	moveq	r3, #0

	str	r3, [r0]
	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
#endif
	mov	pc, lr
ENDPROC(cpu_v7_set_pte_ext)

cpu_v7_name:
	.ascii	"ARMv7 Processor"
	.align

	__INIT

/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	We automatically detect if we have a Harvard cache, and use the
 *	Harvard cache control instructions insead of the unified cache
 *	control instructions.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v7_setup:
#ifdef CONFIG_SMP
	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode and
	orr	r0, r0, #(1 << 6) | (1 << 0)	@ TLB ops broadcasting
	mcr	p15, 0, r0, c1, c0, 1
#endif
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl	v7_flush_dcache_all
	ldmia	r12, {r0-r5, r7, r9, r11, lr}

	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
	bne	2f
	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
	orr	r0, r6, r5, lsr #20-4		@ combine variant and revision

#ifdef CONFIG_ARM_ERRATA_430973
	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
	teq	r0, #0x20			@ only present in r2p0
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
	teq	r0, #0x20			@ only present in r2p0
	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
#endif

2:	mov	r10, #0
#ifdef HARVARD_CACHE
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
#endif
	dsb
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
	orr	r4, r4, #TTB_FLAGS
	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
	mov	r10, #0x1f			@ domains 0, 1 = manager
	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
#endif
	/*
	 * Memory region attributes with SCTLR.TRE=1
	 *
	 *   n = TEX[0],C,B
	 *   TR = PRRR[2n+1:2n]		- memory type
	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
	 *
	 *			n	TR	IR	OR
	 *   UNCACHED		000	00
	 *   BUFFERABLE		001	10	00	00
	 *   WRITETHROUGH	010	10	10	10
	 *   WRITEBACK		011	10	11	11
	 *   reserved		110
	 *   WRITEALLOC		111	10	01	01
	 *   DEV_SHARED		100	01
	 *   DEV_NONSHARED	100	01
	 *   DEV_WC		001	10
	 *   DEV_CACHED		011	10
	 *
	 * Other attributes:
	 *
	 *   DS0 = PRRR[16] = 0		- device shareable property
	 *   DS1 = PRRR[17] = 1		- device shareable property
	 *   NS0 = PRRR[18] = 0		- normal shareable property
	 *   NS1 = PRRR[19] = 1		- normal shareable property
	 *   NOS = PRRR[24+n] = 1	- not outer shareable
	 */
	ldr	r5, =0xff0a81a8			@ PRRR
	ldr	r6, =0x40e040e0			@ NMRR
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
#endif
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
	mov	pc, lr				@ return to head.S:__ret
ENDPROC(__v7_setup)

	/*   AT
	 *  TFR   EV X F   I D LR    S
	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *    1    0 110       0011 1100 .111 1101 < we want
	 */
	.type	v7_crval, #object
v7_crval:
	crval	clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c

__v7_setup_stack:
	.space	4 * 11				@ 11 registers

	.type	v7_processor_functions, #object
ENTRY(v7_processor_functions)
	.word	v7_early_abort
	.word	pabort_ifar
	.word	cpu_v7_proc_init
	.word	cpu_v7_proc_fin
	.word	cpu_v7_reset
	.word	cpu_v7_do_idle
	.word	cpu_v7_dcache_clean_area
	.word	cpu_v7_switch_mm
	.word	cpu_v7_set_pte_ext
	.size	v7_processor_functions, . - v7_processor_functions

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv7"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v7"
	.size	cpu_elf_name, . - cpu_elf_name
	.align

	.section ".proc.info.init", #alloc, #execinstr

	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__v7_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
	.size	__v7_proc_info, . - __v7_proc_info
Commit	Line	Data
bbe88886 CM	1	/*
	2	* linux/arch/arm/mm/proc-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This is the "shell" of the ARMv7 processor support.
	11	*/
991da17e	12	#include <linux/init.h>
bbe88886 CM	13	#include <linux/linkage.h>
	14	#include <asm/assembler.h>
	15	#include <asm/asm-offsets.h>
5ec9407d	16	#include <asm/hwcap.h>
bbe88886 CM	17	#include <asm/pgtable-hwdef.h>
	18	#include <asm/pgtable.h>
	19
	20	#include "proc-macros.S"
	21
bbe88886	22	#define TTB_S (1 << 1)
73b63efa JC	23	#define TTB_RGN_NC (0 << 3)
73b63efa JC	24	#define TTB_RGN_OC_WBWA (1 << 3)
bbe88886 CM	25	#define TTB_RGN_OC_WT (2 << 3)
bbe88886 CM	26	#define TTB_RGN_OC_WB (3 << 3)
ba3c0263 TT	27	#define TTB_NOS (1 << 5)
	28	#define TTB_IRGN_NC ((0 << 0) \| (0 << 6))
	29	#define TTB_IRGN_WBWA ((0 << 0) \| (1 << 6))
	30	#define TTB_IRGN_WT ((1 << 0) \| (0 << 6))
	31	#define TTB_IRGN_WB ((1 << 0) \| (1 << 6))
bbe88886	32
73b63efa	33	#ifndef CONFIG_SMP
ba3c0263 TT	34	/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
ba3c0263 TT	35	#define TTB_FLAGS TTB_IRGN_WB\|TTB_RGN_OC_WB
73b63efa	36	#else
ba3c0263 TT	37	/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
ba3c0263 TT	38	#define TTB_FLAGS TTB_IRGN_WBWA\|TTB_S\|TTB_NOS\|TTB_RGN_OC_WBWA
73b63efa JC	39	#endif
73b63efa JC	40
bbe88886 CM	41	ENTRY(cpu_v7_proc_init)
bbe88886 CM	42	mov pc, lr
93ed3970	43	ENDPROC(cpu_v7_proc_init)
bbe88886 CM	44
	45	ENTRY(cpu_v7_proc_fin)
	46	mov pc, lr
93ed3970	47	ENDPROC(cpu_v7_proc_fin)
bbe88886 CM	48
	49	/*
	50	* cpu_v7_reset(loc)
	51	*
	52	* Perform a soft reset of the system. Put the CPU into the
	53	* same state as it would be if it had been reset, and branch
	54	* to what would be the reset vector.
	55	*
	56	* - loc - location to jump to for soft reset
	57	*
	58	* It is assumed that:
	59	*/
	60	.align 5
	61	ENTRY(cpu_v7_reset)
	62	mov pc, r0
93ed3970	63	ENDPROC(cpu_v7_reset)
bbe88886 CM	64
	65	/*
	66	* cpu_v7_do_idle()
	67	*
	68	* Idle the processor (eg, wait for interrupt).
	69	*
	70	* IRQs are already disabled.
	71	*/
	72	ENTRY(cpu_v7_do_idle)
8553cb67	73	dsb @ WFI may enter a low-power mode
000b5025	74	wfi
bbe88886	75	mov pc, lr
93ed3970	76	ENDPROC(cpu_v7_do_idle)
bbe88886 CM	77
	78	ENTRY(cpu_v7_dcache_clean_area)
	79	#ifndef TLB_CAN_READ_FROM_L1_CACHE
	80	dcache_line_size r2, r3
	81	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	82	add r0, r0, r2
	83	subs r1, r1, r2
	84	bhi 1b
	85	dsb
	86	#endif
	87	mov pc, lr
93ed3970	88	ENDPROC(cpu_v7_dcache_clean_area)
bbe88886 CM	89
	90	/*
	91	* cpu_v7_switch_mm(pgd_phys, tsk)
	92	*
	93	* Set the translation table base pointer to be pgd_phys
	94	*
	95	* - pgd_phys - physical address of new TTB
	96	*
	97	* It is assumed that:
	98	* - we are not using split page tables
	99	*/
	100	ENTRY(cpu_v7_switch_mm)
2eb8c82b	101	#ifdef CONFIG_MMU
bbe88886 CM	102	mov r2, #0
bbe88886 CM	103	ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
73b63efa	104	orr r0, r0, #TTB_FLAGS
7ce236fc CM	105	#ifdef CONFIG_ARM_ERRATA_430973
	106	mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
	107	#endif
bbe88886 CM	108	mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
	109	isb
	110	1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
	111	isb
	112	mcr p15, 0, r1, c13, c0, 1 @ set context ID
	113	isb
2eb8c82b	114	#endif
bbe88886	115	mov pc, lr
93ed3970	116	ENDPROC(cpu_v7_switch_mm)
bbe88886 CM	117
	118	/*
	119	* cpu_v7_set_pte_ext(ptep, pte)
	120	*
	121	* Set a level 2 translation table entry.
	122	*
	123	* - ptep - pointer to level 2 translation table entry
	124	* (hardware version is stored at -1024 bytes)
	125	* - pte - PTE value to store
	126	* - ext - value for extended PTE bits
bbe88886 CM	127	*/
bbe88886 CM	128	ENTRY(cpu_v7_set_pte_ext)
2eb8c82b	129	#ifdef CONFIG_MMU
347c8b70 CM	130	ARM( str r1, [r0], #-2048 ) @ linux version
	131	THUMB( str r1, [r0] ) @ linux version
	132	THUMB( sub r0, r0, #2048 )
bbe88886 CM	133
bbe88886 CM	134	bic r3, r1, #0x000003f0
3f69c0c1	135	bic r3, r3, #PTE_TYPE_MASK
bbe88886 CM	136	orr r3, r3, r2
	137	orr r3, r3, #PTE_EXT_AP0 \| 2
	138
b1cce6b1	139	tst r1, #1 << 4
3f69c0c1 RK	140	orrne r3, r3, #PTE_EXT_TEX(1)
3f69c0c1 RK	141
bbe88886 CM	142	tst r1, #L_PTE_WRITE
	143	tstne r1, #L_PTE_DIRTY
	144	orreq r3, r3, #PTE_EXT_APX
	145
	146	tst r1, #L_PTE_USER
	147	orrne r3, r3, #PTE_EXT_AP1
	148	tstne r3, #PTE_EXT_APX
	149	bicne r3, r3, #PTE_EXT_APX \| PTE_EXT_AP0
	150
bbe88886 CM	151	tst r1, #L_PTE_EXEC
	152	orreq r3, r3, #PTE_EXT_XN
	153
3f69c0c1 RK	154	tst r1, #L_PTE_YOUNG
3f69c0c1 RK	155	tstne r1, #L_PTE_PRESENT
bbe88886 CM	156	moveq r3, #0
	157
	158	str r3, [r0]
	159	mcr p15, 0, r0, c7, c10, 1 @ flush_pte
2eb8c82b	160	#endif
bbe88886	161	mov pc, lr
93ed3970	162	ENDPROC(cpu_v7_set_pte_ext)
bbe88886 CM	163
	164	cpu_v7_name:
	165	.ascii "ARMv7 Processor"
	166	.align
	167
991da17e	168	__INIT
bbe88886 CM	169
	170	/*
	171	* __v7_setup
	172	*
	173	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	174	* on. Return in r0 the new CP15 C1 control register setting.
	175	*
	176	* We automatically detect if we have a Harvard cache, and use the
	177	* Harvard cache control instructions insead of the unified cache
	178	* control instructions.
	179	*
	180	* This should be able to cover all ARMv7 cores.
	181	*
	182	* It is assumed that:
	183	* - cache type register is implemented
	184	*/
	185	__v7_setup:
73b63efa	186	#ifdef CONFIG_SMP
faa7bc51 CM	187	mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode and
faa7bc51 CM	188	orr r0, r0, #(1 << 6) \| (1 << 0) @ TLB ops broadcasting
73b63efa JC	189	mcr p15, 0, r0, c1, c0, 1
73b63efa JC	190	#endif
bbe88886 CM	191	adr r12, __v7_setup_stack @ the local stack
	192	stmia r12, {r0-r5, r7, r9, r11, lr}
	193	bl v7_flush_dcache_all
	194	ldmia r12, {r0-r5, r7, r9, r11, lr}
1946d6ef RK	195
	196	mrc p15, 0, r0, c0, c0, 0 @ read main ID register
	197	and r10, r0, #0xff000000 @ ARM?
	198	teq r10, #0x41000000
	199	bne 2f
	200	and r5, r0, #0x00f00000 @ variant
	201	and r6, r0, #0x0000000f @ revision
	202	orr r0, r6, r5, lsr #20-4 @ combine variant and revision
	203
7ce236fc	204	#ifdef CONFIG_ARM_ERRATA_430973
1946d6ef RK	205	teq r5, #0x00100000 @ only present in r1p*
	206	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	207	orreq r10, r10, #(1 << 6) @ set IBE to 1
	208	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
855c551f CM	209	#endif
855c551f CM	210	#ifdef CONFIG_ARM_ERRATA_458693
1946d6ef RK	211	teq r0, #0x20 @ only present in r2p0
	212	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	213	orreq r10, r10, #(1 << 5) @ set L1NEON to 1
	214	orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
	215	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
0516e464 CM	216	#endif
0516e464 CM	217	#ifdef CONFIG_ARM_ERRATA_460075
1946d6ef RK	218	teq r0, #0x20 @ only present in r2p0
	219	mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
	220	tsteq r10, #1 << 22
	221	orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
	222	mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
7ce236fc	223	#endif
1946d6ef RK	224
1946d6ef RK	225	2: mov r10, #0
bbe88886 CM	226	#ifdef HARVARD_CACHE
	227	mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
	228	#endif
	229	dsb
2eb8c82b	230	#ifdef CONFIG_MMU
bbe88886 CM	231	mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
bbe88886 CM	232	mcr p15, 0, r10, c2, c0, 2 @ TTB control register
73b63efa	233	orr r4, r4, #TTB_FLAGS
bbe88886 CM	234	mcr p15, 0, r4, c2, c0, 1 @ load TTB1
	235	mov r10, #0x1f @ domains 0, 1 = manager
	236	mcr p15, 0, r10, c3, c0, 0 @ load domain access register
2eb8c82b	237	#endif
23d1c515 CM	238	/*
	239	* Memory region attributes with SCTLR.TRE=1
	240	*
	241	* n = TEX[0],C,B
	242	* TR = PRRR[2n+1:2n] - memory type
	243	* IR = NMRR[2n+1:2n] - inner cacheable property
	244	* OR = NMRR[2n+17:2n+16] - outer cacheable property
	245	*
	246	* n TR IR OR
	247	* UNCACHED 000 00
	248	* BUFFERABLE 001 10 00 00
	249	* WRITETHROUGH 010 10 10 10
	250	* WRITEBACK 011 10 11 11
	251	* reserved 110
	252	* WRITEALLOC 111 10 01 01
	253	* DEV_SHARED 100 01
	254	* DEV_NONSHARED 100 01
	255	* DEV_WC 001 10
	256	* DEV_CACHED 011 10
	257	*
	258	* Other attributes:
	259	*
	260	* DS0 = PRRR[16] = 0 - device shareable property
	261	* DS1 = PRRR[17] = 1 - device shareable property
	262	* NS0 = PRRR[18] = 0 - normal shareable property
	263	* NS1 = PRRR[19] = 1 - normal shareable property
	264	* NOS = PRRR[24+n] = 1 - not outer shareable
	265	*/
	266	ldr r5, =0xff0a81a8 @ PRRR
	267	ldr r6, =0x40e040e0 @ NMRR
3f69c0c1 RK	268	mcr p15, 0, r5, c10, c2, 0 @ write PRRR
3f69c0c1 RK	269	mcr p15, 0, r6, c10, c2, 1 @ write NMRR
2eb8c82b CM	270	adr r5, v7_crval
2eb8c82b CM	271	ldmia r5, {r5, r6}
26584853 CM	272	#ifdef CONFIG_CPU_ENDIAN_BE8
	273	orr r6, r6, #1 << 25 @ big-endian page tables
	274	#endif
2eb8c82b CM	275	mrc p15, 0, r0, c1, c0, 0 @ read control register
	276	bic r0, r0, r5 @ clear bits them
	277	orr r0, r0, r6 @ set them
347c8b70	278	THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
bbe88886	279	mov pc, lr @ return to head.S:__ret
93ed3970	280	ENDPROC(__v7_setup)
bbe88886	281
b1cce6b1	282	/* AT
213fb2a8 CM	283	* TFR EV X F I D LR S
213fb2a8 CM	284	* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
b1cce6b1	285	* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
213fb2a8	286	* 1 0 110 0011 1100 .111 1101 < we want
bbe88886	287	*/
2eb8c82b CM	288	.type v7_crval, #object
2eb8c82b CM	289	v7_crval:
213fb2a8	290	crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
bbe88886 CM	291
	292	__v7_setup_stack:
	293	.space 4 * 11 @ 11 registers
	294
	295	.type v7_processor_functions, #object
	296	ENTRY(v7_processor_functions)
	297	.word v7_early_abort
4a1fd556	298	.word pabort_ifar
bbe88886 CM	299	.word cpu_v7_proc_init
	300	.word cpu_v7_proc_fin
	301	.word cpu_v7_reset
	302	.word cpu_v7_do_idle
	303	.word cpu_v7_dcache_clean_area
	304	.word cpu_v7_switch_mm
	305	.word cpu_v7_set_pte_ext
	306	.size v7_processor_functions, . - v7_processor_functions
	307
	308	.type cpu_arch_name, #object
	309	cpu_arch_name:
	310	.asciz "armv7"
	311	.size cpu_arch_name, . - cpu_arch_name
	312
	313	.type cpu_elf_name, #object
	314	cpu_elf_name:
	315	.asciz "v7"
	316	.size cpu_elf_name, . - cpu_elf_name
	317	.align
	318
	319	.section ".proc.info.init", #alloc, #execinstr
	320
	321	/*
	322	* Match any ARMv7 processor core.
	323	*/
	324	.type __v7_proc_info, #object
	325	__v7_proc_info:
	326	.long 0x000f0000 @ Required ID value
	327	.long 0x000f0000 @ Mask for ID
	328	.long PMD_TYPE_SECT \| \
	329	PMD_SECT_BUFFERABLE \| \
	330	PMD_SECT_CACHEABLE \| \
	331	PMD_SECT_AP_WRITE \| \
	332	PMD_SECT_AP_READ
	333	.long PMD_TYPE_SECT \| \
	334	PMD_SECT_XN \| \
	335	PMD_SECT_AP_WRITE \| \
	336	PMD_SECT_AP_READ
	337	b __v7_setup
	338	.long cpu_arch_name
	339	.long cpu_elf_name
	340	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
	341	.long cpu_v7_name
	342	.long v7_processor_functions
2ccdd1e7	343	.long v7wbi_tlb_fns
bbe88886 CM	344	.long v6_user_fns
	345	.long v7_cache_fns
	346	.size __v7_proc_info, . - __v7_proc_info