[net-next-2.6.git] / arch / arm / mm / proc-arm922.S

/*
 *  linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
 *
 *  Copyright (C) 1999,2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  Copyright (C) 2001 Altera Corporation
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm922.
 *
 *  CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	4

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintainence instructions.  (I think this should
 * be 32768).
 */
#define CACHE_DLIMIT	8192


	.text
/*
 * cpu_arm922_proc_init()
 */
ENTRY(cpu_arm922_proc_init)
	mov	pc, lr

/*
 * cpu_arm922_proc_fin()
 */
ENTRY(cpu_arm922_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_arm922_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm922_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm922_do_idle()
 */
	.align	5
ENTRY(cpu_arm922_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr


#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm922_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mov	pc, lr
ENDPROC(arm922_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
ENTRY(arm922_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm922_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 8 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 7 to 0
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
ENTRY(arm922_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	tst	r2, #VM_EXEC
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm922_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm922_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(arm922_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm922_dma_inv_range:
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm922_dma_clean_range:
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm922_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm922_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm922_dma_clean_range
	bcs	arm922_dma_inv_range
	b	arm922_dma_flush_range
ENDPROC(arm922_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm922_dma_unmap_area)
	mov	pc, lr
ENDPROC(arm922_dma_unmap_area)

ENTRY(arm922_cache_fns)
	.long	arm922_flush_icache_all
	.long	arm922_flush_kern_cache_all
	.long	arm922_flush_user_cache_all
	.long	arm922_flush_user_cache_range
	.long	arm922_coherent_kern_range
	.long	arm922_coherent_user_range
	.long	arm922_flush_kern_dcache_area
	.long	arm922_dma_map_area
	.long	arm922_dma_unmap_area
	.long	arm922_dma_flush_range

#endif


ENTRY(cpu_arm922_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm922_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm922_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
@ && Re-written to use Index Ops.
@ && Uses registers r1, r3 and ip

	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 7 to 0
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr

/*
 * cpu_arm922_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm922_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif /* CONFIG_MMU */
	mov	pc, lr

	__CPUINIT

	.type	__arm922_setup, #function
__arm922_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif
	adr	r5, arm922_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
	mov	pc, lr
	.size	__arm922_setup, . - __arm922_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * ..11 0001 ..11 0101
	 * 
	 */
	.type	arm922_crval, #object
arm922_crval:
	crval	clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm922_processor_functions, #object
arm922_processor_functions:
	.word	v4t_early_abort
	.word	legacy_pabort
	.word	cpu_arm922_proc_init
	.word	cpu_arm922_proc_fin
	.word	cpu_arm922_reset
	.word   cpu_arm922_do_idle
	.word	cpu_arm922_dcache_clean_area
	.word	cpu_arm922_switch_mm
	.word	cpu_arm922_set_pte_ext
	.size	arm922_processor_functions, . - arm922_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv4t"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v4"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_arm922_name, #object
cpu_arm922_name:
	.asciz	"ARM922T"
	.size	cpu_arm922_name, . - cpu_arm922_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm922_proc_info,#object
__arm922_proc_info:
	.long	0x41009220
	.long	0xff00fff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm922_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm922_name
	.long	arm922_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	.long	arm922_cache_fns
#else
	.long	v4wt_cache_fns
#endif
	.size	__arm922_proc_info, . - __arm922_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
	3	*
	4	* Copyright (C) 1999,2000 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	6	* Copyright (C) 2001 Altera Corporation
d090ddda	7	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*
	24	* These are the low level assembler for performing cache and TLB
	25	* functions on the arm922.
	26	*
	27	* CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
	28	*/
	29	#include <linux/linkage.h>
1da177e4 LT	30	#include <linux/init.h>
1da177e4 LT	31	#include <asm/assembler.h>
5ec9407d	32	#include <asm/hwcap.h>
74945c86	33	#include <asm/pgtable-hwdef.h>
1da177e4	34	#include <asm/pgtable.h>
1da177e4 LT	35	#include <asm/page.h>
	36	#include <asm/ptrace.h>
	37	#include "proc-macros.S"
	38
	39	/*
	40	* The size of one data cache line.
	41	*/
	42	#define CACHE_DLINESIZE 32
	43
	44	/*
	45	* The number of data cache segments.
	46	*/
	47	#define CACHE_DSEGMENTS 4
	48
	49	/*
	50	* The number of lines in a cache segment.
	51	*/
	52	#define CACHE_DENTRIES 64
	53
	54	/*
	55	* This is the size at which it becomes more efficient to
	56	* clean the whole cache, rather than using the individual
	57	* cache line maintainence instructions. (I think this should
	58	* be 32768).
	59	*/
	60	#define CACHE_DLIMIT 8192
	61
	62
	63	.text
	64	/*
	65	* cpu_arm922_proc_init()
	66	*/
	67	ENTRY(cpu_arm922_proc_init)
	68	mov pc, lr
	69
	70	/*
	71	* cpu_arm922_proc_fin()
	72	*/
	73	ENTRY(cpu_arm922_proc_fin)
1da177e4 LT	74	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	75	bic r0, r0, #0x1000 @ ...i............
	76	bic r0, r0, #0x000e @ ............wca.
	77	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	78	mov pc, lr
1da177e4 LT	79
	80	/*
	81	* cpu_arm922_reset(loc)
	82	*
	83	* Perform a soft reset of the system. Put the CPU into the
	84	* same state as it would be if it had been reset, and branch
	85	* to what would be the reset vector.
	86	*
	87	* loc: location to jump to for soft reset
	88	*/
	89	.align 5
	90	ENTRY(cpu_arm922_reset)
	91	mov ip, #0
	92	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	93	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	94	#ifdef CONFIG_MMU
1da177e4	95	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	96	#endif
1da177e4 LT	97	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	98	bic ip, ip, #0x000f @ ............wcam
	99	bic ip, ip, #0x1100 @ ...i...s........
	100	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	101	mov pc, r0
	102
	103	/*
	104	* cpu_arm922_do_idle()
	105	*/
	106	.align 5
	107	ENTRY(cpu_arm922_do_idle)
	108	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	109	mov pc, lr
	110
	111
	112	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	113
c8c90860 MW	114	/*
	115	* flush_icache_all()
	116	*
	117	* Unconditionally clean and invalidate the entire icache.
	118	*/
	119	ENTRY(arm922_flush_icache_all)
	120	mov r0, #0
	121	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	122	mov pc, lr
	123	ENDPROC(arm922_flush_icache_all)
	124
1da177e4 LT	125	/*
	126	* flush_user_cache_all()
	127	*
	128	* Clean and invalidate all cache entries in a particular
	129	* address space.
	130	*/
	131	ENTRY(arm922_flush_user_cache_all)
	132	/* FALLTHROUGH */
	133
	134	/*
	135	* flush_kern_cache_all()
	136	*
	137	* Clean and invalidate the entire cache.
	138	*/
	139	ENTRY(arm922_flush_kern_cache_all)
	140	mov r2, #VM_EXEC
	141	mov ip, #0
	142	__flush_whole_cache:
	143	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
	144	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	145	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	146	subs r3, r3, #1 << 26
	147	bcs 2b @ entries 63 to 0
	148	subs r1, r1, #1 << 5
	149	bcs 1b @ segments 7 to 0
	150	tst r2, #VM_EXEC
	151	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	152	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	153	mov pc, lr
	154
	155	/*
	156	* flush_user_cache_range(start, end, flags)
	157	*
	158	* Clean and invalidate a range of cache entries in the
	159	* specified address range.
	160	*
	161	* - start - start address (inclusive)
	162	* - end - end address (exclusive)
	163	* - flags - vm_flags describing address space
	164	*/
	165	ENTRY(arm922_flush_user_cache_range)
	166	mov ip, #0
	167	sub r3, r1, r0 @ calculate total size
	168	cmp r3, #CACHE_DLIMIT
	169	bhs __flush_whole_cache
	170
	171	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	172	tst r2, #VM_EXEC
	173	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	174	add r0, r0, #CACHE_DLINESIZE
	175	cmp r0, r1
	176	blo 1b
	177	tst r2, #VM_EXEC
	178	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	179	mov pc, lr
	180
	181	/*
	182	* coherent_kern_range(start, end)
	183	*
	184	* Ensure coherency between the Icache and the Dcache in the
	185	* region described by start, end. If you have non-snooping
	186	* Harvard caches, you need to implement this function.
	187	*
	188	* - start - virtual start address
189	* - end - virtual end address
190	*/
191	ENTRY(arm922_coherent_kern_range)
192	/* FALLTHROUGH */
193
194	/*
195	* coherent_user_range(start, end)
196	*
197	* Ensure coherency between the Icache and the Dcache in the
198	* region described by start, end. If you have non-snooping
199	* Harvard caches, you need to implement this function.
200	*
201	* - start - virtual start address
202	* - end - virtual end address
203	*/
204	ENTRY(arm922_coherent_user_range)
205	bic r0, r0, #CACHE_DLINESIZE - 1
206	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
207	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
208	add r0, r0, #CACHE_DLINESIZE
209	cmp r0, r1
210	blo 1b
211	mcr p15, 0, r0, c7, c10, 4 @ drain WB
212	mov pc, lr
213
214	/*
2c9b9c84	215	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	216	*
	217	* Ensure no D cache aliasing occurs, either with itself or
	218	* the I cache
	219	*
2c9b9c84 RK	220	* - addr - kernel address
2c9b9c84 RK	221	* - size - region size
1da177e4	222	*/
2c9b9c84 RK	223	ENTRY(arm922_flush_kern_dcache_area)
2c9b9c84 RK	224	add r1, r0, r1
1da177e4 LT	225	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	226	add r0, r0, #CACHE_DLINESIZE
	227	cmp r0, r1
	228	blo 1b
	229	mov r0, #0
	230	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	231	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	232	mov pc, lr
	233
	234	/*
	235	* dma_inv_range(start, end)
	236	*
	237	* Invalidate (discard) the specified virtual address range.
	238	* May not write back any entries. If 'start' or 'end'
	239	* are not cache line aligned, those lines must be written
	240	* back.
	241	*
	242	* - start - virtual start address
	243	* - end - virtual end address
	244	*
	245	* (same as v4wb)
	246	*/
702b94bf	247	arm922_dma_inv_range:
1da177e4 LT	248	tst r0, #CACHE_DLINESIZE - 1
	249	bic r0, r0, #CACHE_DLINESIZE - 1
	250	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	251	tst r1, #CACHE_DLINESIZE - 1
	252	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	253	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	254	add r0, r0, #CACHE_DLINESIZE
	255	cmp r0, r1
	256	blo 1b
	257	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	258	mov pc, lr
	259
	260	/*
	261	* dma_clean_range(start, end)
	262	*
	263	* Clean the specified virtual address range.
	264	*
	265	* - start - virtual start address
	266	* - end - virtual end address
	267	*
	268	* (same as v4wb)
	269	*/
702b94bf	270	arm922_dma_clean_range:
1da177e4 LT	271	bic r0, r0, #CACHE_DLINESIZE - 1
	272	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	273	add r0, r0, #CACHE_DLINESIZE
	274	cmp r0, r1
	275	blo 1b
	276	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	277	mov pc, lr
	278
	279	/*
	280	* dma_flush_range(start, end)
	281	*
	282	* Clean and invalidate the specified virtual address range.
	283	*
	284	* - start - virtual start address
	285	* - end - virtual end address
	286	*/
	287	ENTRY(arm922_dma_flush_range)
	288	bic r0, r0, #CACHE_DLINESIZE - 1
	289	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	290	add r0, r0, #CACHE_DLINESIZE
	291	cmp r0, r1
	292	blo 1b
	293	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	294	mov pc, lr
	295
a9c9147e RK	296	/*
	297	* dma_map_area(start, size, dir)
	298	* - start - kernel virtual start address
	299	* - size - size of region
	300	* - dir - DMA direction
	301	*/
	302	ENTRY(arm922_dma_map_area)
	303	add r1, r1, r0
	304	cmp r2, #DMA_TO_DEVICE
	305	beq arm922_dma_clean_range
	306	bcs arm922_dma_inv_range
	307	b arm922_dma_flush_range
	308	ENDPROC(arm922_dma_map_area)
	309
	310	/*
	311	* dma_unmap_area(start, size, dir)
	312	* - start - kernel virtual start address
	313	* - size - size of region
	314	* - dir - DMA direction
	315	*/
	316	ENTRY(arm922_dma_unmap_area)
	317	mov pc, lr
	318	ENDPROC(arm922_dma_unmap_area)
	319
1da177e4	320	ENTRY(arm922_cache_fns)
c8c90860	321	.long arm922_flush_icache_all
1da177e4 LT	322	.long arm922_flush_kern_cache_all
	323	.long arm922_flush_user_cache_all
	324	.long arm922_flush_user_cache_range
	325	.long arm922_coherent_kern_range
	326	.long arm922_coherent_user_range
2c9b9c84	327	.long arm922_flush_kern_dcache_area
a9c9147e RK	328	.long arm922_dma_map_area
a9c9147e RK	329	.long arm922_dma_unmap_area
1da177e4 LT	330	.long arm922_dma_flush_range
	331
	332	#endif
	333
	334
	335	ENTRY(cpu_arm922_dcache_clean_area)
	336	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	337	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	338	add r0, r0, #CACHE_DLINESIZE
	339	subs r1, r1, #CACHE_DLINESIZE
	340	bhi 1b
	341	#endif
	342	mov pc, lr
	343
	344	/* =============================== PageTable ============================== */
	345
	346	/*
	347	* cpu_arm922_switch_mm(pgd)
	348	*
	349	* Set the translation base pointer to be as described by pgd.
	350	*
	351	* pgd: new page tables
	352	*/
	353	.align 5
	354	ENTRY(cpu_arm922_switch_mm)
d090ddda	355	#ifdef CONFIG_MMU
1da177e4 LT	356	mov ip, #0
	357	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	358	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	359	#else
	360	@ && 'Clean & Invalidate whole DCache'
	361	@ && Re-written to use Index Ops.
	362	@ && Uses registers r1, r3 and ip
	363
	364	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
	365	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	366	2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
	367	subs r3, r3, #1 << 26
	368	bcs 2b @ entries 63 to 0
	369	subs r1, r1, #1 << 5
	370	bcs 1b @ segments 7 to 0
	371	#endif
	372	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	373	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	374	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	375	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	376	#endif
1da177e4 LT	377	mov pc, lr
	378
	379	/*
ad1ae2fe	380	* cpu_arm922_set_pte_ext(ptep, pte, ext)
1da177e4 LT	381	*
	382	* Set a PTE and flush it out
	383	*/
	384	.align 5
ad1ae2fe	385	ENTRY(cpu_arm922_set_pte_ext)
d090ddda	386	#ifdef CONFIG_MMU
da091653	387	armv3_set_pte_ext
1da177e4 LT	388	mov r0, r0
	389	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	390	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	391	#endif /* CONFIG_MMU */
1da177e4 LT	392	mov pc, lr
1da177e4 LT	393
5085f3ff	394	__CPUINIT
1da177e4 LT	395
	396	.type __arm922_setup, #function
	397	__arm922_setup:
	398	mov r0, #0
	399	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	400	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	401	#ifdef CONFIG_MMU
1da177e4	402	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	403	#endif
22b19086 RK	404	adr r5, arm922_crval
22b19086 RK	405	ldmia r5, {r5, r6}
1da177e4	406	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	407	bic r0, r0, r5
22b19086	408	orr r0, r0, r6
1da177e4 LT	409	mov pc, lr
	410	.size __arm922_setup, . - __arm922_setup
	411
	412	/*
	413	* R
	414	* .RVI ZFRS BLDP WCAM
	415	* ..11 0001 ..11 0101
	416	*
	417	*/
22b19086 RK	418	.type arm922_crval, #object
	419	arm922_crval:
	420	crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
1da177e4 LT	421
	422	__INITDATA
	423
	424	/*
	425	* Purpose : Function pointers used to access above functions - all calls
	426	* come through these
	427	*/
	428	.type arm922_processor_functions, #object
	429	arm922_processor_functions:
	430	.word v4t_early_abort
4fb28474	431	.word legacy_pabort
1da177e4 LT	432	.word cpu_arm922_proc_init
	433	.word cpu_arm922_proc_fin
	434	.word cpu_arm922_reset
	435	.word cpu_arm922_do_idle
	436	.word cpu_arm922_dcache_clean_area
	437	.word cpu_arm922_switch_mm
ad1ae2fe	438	.word cpu_arm922_set_pte_ext
1da177e4 LT	439	.size arm922_processor_functions, . - arm922_processor_functions
	440
	441	.section ".rodata"
	442
	443	.type cpu_arch_name, #object
	444	cpu_arch_name:
	445	.asciz "armv4t"
	446	.size cpu_arch_name, . - cpu_arch_name
	447
	448	.type cpu_elf_name, #object
	449	cpu_elf_name:
	450	.asciz "v4"
	451	.size cpu_elf_name, . - cpu_elf_name
	452
	453	.type cpu_arm922_name, #object
	454	cpu_arm922_name:
264edb35	455	.asciz "ARM922T"
1da177e4 LT	456	.size cpu_arm922_name, . - cpu_arm922_name
	457
	458	.align
	459
02b7dd12	460	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	461
	462	.type __arm922_proc_info,#object
	463	__arm922_proc_info:
	464	.long 0x41009220
	465	.long 0xff00fff0
	466	.long PMD_TYPE_SECT \| \
	467	PMD_SECT_BUFFERABLE \| \
	468	PMD_SECT_CACHEABLE \| \
	469	PMD_BIT4 \| \
	470	PMD_SECT_AP_WRITE \| \
	471	PMD_SECT_AP_READ
8799ee9f RK	472	.long PMD_TYPE_SECT \| \
	473	PMD_BIT4 \| \
	474	PMD_SECT_AP_WRITE \| \
	475	PMD_SECT_AP_READ
1da177e4 LT	476	b __arm922_setup
	477	.long cpu_arch_name
	478	.long cpu_elf_name
	479	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	480	.long cpu_arm922_name
	481	.long arm922_processor_functions
	482	.long v4wbi_tlb_fns
	483	.long v4wb_user_fns
	484	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	485	.long arm922_cache_fns
	486	#else
	487	.long v4wt_cache_fns
	488	#endif
	489	.size __arm922_proc_info, . - __arm922_proc_info