[net-next-2.6.git] / arch / arm / mm / proc-arm1026.S

/*
 *  linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
 *
 *  Copyright (C) 2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the ARM1026EJ-S.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define MAX_AREA_SIZE	32768

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	16

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintainence instructions.
 */
#define CACHE_DLIMIT	32768

	.text
/*
 * cpu_arm1026_proc_init()
 */
ENTRY(cpu_arm1026_proc_init)
	mov	pc, lr

/*
 * cpu_arm1026_proc_fin()
 */
ENTRY(cpu_arm1026_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000 		@ ...i............
	bic	r0, r0, #0x000e 		@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_arm1026_reset(loc)
 *
 * Perform a soft reset of the system.	Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm1026_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f 		@ ............wcam
	bic	ip, ip, #0x1100 		@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm1026_do_idle()
 */
	.align	5
ENTRY(cpu_arm1026_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr

/* ================================= CACHE ================================ */

	.align	5

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm1026_flush_icache_all)
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
#endif
	mov	pc, lr
ENDPROC(arm1026_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
ENTRY(arm1026_flush_user_cache_all)
	/* FALLTHROUGH */
/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm1026_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifndef CONFIG_CPU_DCACHE_DISABLE
1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate
	bne	1b
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags for this space
 */
ENTRY(arm1026_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

#ifndef CONFIG_CPU_DCACHE_DISABLE
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1026_coherent_kern_range)
	/* FALLTHROUGH */
/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1026_coherent_user_range)
	mov	ip, #0
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(arm1026_flush_kern_dcache_area)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1026_dma_inv_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1026_dma_clean_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1026_dma_flush_range)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1026_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm1026_dma_clean_range
	bcs	arm1026_dma_inv_range
	b	arm1026_dma_flush_range
ENDPROC(arm1026_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1026_dma_unmap_area)
	mov	pc, lr
ENDPROC(arm1026_dma_unmap_area)

ENTRY(arm1026_cache_fns)
	.long	arm1026_flush_icache_all
	.long	arm1026_flush_kern_cache_all
	.long	arm1026_flush_user_cache_all
	.long	arm1026_flush_user_cache_range
	.long	arm1026_coherent_kern_range
	.long	arm1026_coherent_user_range
	.long	arm1026_flush_kern_dcache_area
	.long	arm1026_dma_map_area
	.long	arm1026_dma_unmap_area
	.long	arm1026_dma_flush_range

	.align	5
ENTRY(cpu_arm1026_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mov	ip, #0
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm1026_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm1026_switch_mm)
#ifdef CONFIG_MMU
	mov	r1, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate
	bne	1b
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
#endif
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr
        
/*
 * cpu_arm1026_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm1026_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
#endif /* CONFIG_MMU */
	mov	pc, lr


	__CPUINIT

	.type	__arm1026_setup, #function
__arm1026_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
	mcr	p15, 0, r4, c2, c0		@ load page table pointer
#endif
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #4				@ explicitly disable writeback
	mcr	p15, 7, r0, c15, c0, 0
#endif
	adr	r5, arm1026_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm1026_setup, . - __arm1026_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 1001 ..11 0101
	 * 
	 */
	.type	arm1026_crval, #object
arm1026_crval:
	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm1026_processor_functions, #object
arm1026_processor_functions:
	.word	v5t_early_abort
	.word	legacy_pabort
	.word	cpu_arm1026_proc_init
	.word	cpu_arm1026_proc_fin
	.word	cpu_arm1026_reset
	.word	cpu_arm1026_do_idle
	.word	cpu_arm1026_dcache_clean_area
	.word	cpu_arm1026_switch_mm
	.word	cpu_arm1026_set_pte_ext
	.size	arm1026_processor_functions, . - arm1026_processor_functions

	.section .rodata

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv5tej"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v5"
	.size	cpu_elf_name, . - cpu_elf_name
	.align

	.type	cpu_arm1026_name, #object
cpu_arm1026_name:
	.asciz	"ARM1026EJ-S"
	.size	cpu_arm1026_name, . - cpu_arm1026_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm1026_proc_info,#object
__arm1026_proc_info:
	.long	0x4106a260			@ ARM 1026EJ-S (v5TEJ)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm1026_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
	.long	cpu_arm1026_name
	.long	arm1026_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm1026_cache_fns
	.size	__arm1026_proc_info, . - __arm1026_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
	3	*
	4	* Copyright (C) 2000 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	6	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*
	14	* These are the low level assembler for performing cache and TLB
	15	* functions on the ARM1026EJ-S.
	16	*/
	17	#include <linux/linkage.h>
1da177e4 LT	18	#include <linux/init.h>
1da177e4 LT	19	#include <asm/assembler.h>
e6ae744d	20	#include <asm/asm-offsets.h>
5ec9407d	21	#include <asm/hwcap.h>
74945c86	22	#include <asm/pgtable-hwdef.h>
1da177e4	23	#include <asm/pgtable.h>
1da177e4 LT	24	#include <asm/ptrace.h>
1da177e4 LT	25
00eb0f6b RK	26	#include "proc-macros.S"
00eb0f6b RK	27
1da177e4 LT	28	/*
	29	* This is the maximum size of an area which will be invalidated
	30	* using the single invalidate entry instructions. Anything larger
	31	* than this, and we go for the whole cache.
	32	*
	33	* This value should be chosen such that we choose the cheapest
	34	* alternative.
	35	*/
	36	#define MAX_AREA_SIZE 32768
	37
	38	/*
	39	* The size of one data cache line.
	40	*/
	41	#define CACHE_DLINESIZE 32
	42
	43	/*
	44	* The number of data cache segments.
	45	*/
	46	#define CACHE_DSEGMENTS 16
	47
	48	/*
	49	* The number of lines in a cache segment.
	50	*/
	51	#define CACHE_DENTRIES 64
	52
	53	/*
	54	* This is the size at which it becomes more efficient to
	55	* clean the whole cache, rather than using the individual
	56	* cache line maintainence instructions.
	57	*/
	58	#define CACHE_DLIMIT 32768
	59
	60	.text
	61	/*
	62	* cpu_arm1026_proc_init()
	63	*/
	64	ENTRY(cpu_arm1026_proc_init)
	65	mov pc, lr
	66
	67	/*
	68	* cpu_arm1026_proc_fin()
	69	*/
	70	ENTRY(cpu_arm1026_proc_fin)
1da177e4 LT	71	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	72	bic r0, r0, #0x1000 @ ...i............
	73	bic r0, r0, #0x000e @ ............wca.
	74	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	75	mov pc, lr
1da177e4 LT	76
	77	/*
	78	* cpu_arm1026_reset(loc)
	79	*
	80	* Perform a soft reset of the system. Put the CPU into the
	81	* same state as it would be if it had been reset, and branch
	82	* to what would be the reset vector.
	83	*
	84	* loc: location to jump to for soft reset
	85	*/
	86	.align 5
	87	ENTRY(cpu_arm1026_reset)
	88	mov ip, #0
	89	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	90	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	91	#ifdef CONFIG_MMU
1da177e4	92	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	93	#endif
1da177e4 LT	94	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	95	bic ip, ip, #0x000f @ ............wcam
	96	bic ip, ip, #0x1100 @ ...i...s........
	97	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	98	mov pc, r0
	99
	100	/*
	101	* cpu_arm1026_do_idle()
	102	*/
	103	.align 5
	104	ENTRY(cpu_arm1026_do_idle)
	105	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	106	mov pc, lr
	107
	108	/* ================================= CACHE ================================ */
	109
	110	.align 5
c8c90860 MW	111
	112	/*
	113	* flush_icache_all()
	114	*
	115	* Unconditionally clean and invalidate the entire icache.
	116	*/
	117	ENTRY(arm1026_flush_icache_all)
	118	#ifndef CONFIG_CPU_ICACHE_DISABLE
	119	mov r0, #0
	120	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	121	#endif
	122	mov pc, lr
	123	ENDPROC(arm1026_flush_icache_all)
	124
1da177e4 LT	125	/*
	126	* flush_user_cache_all()
	127	*
	128	* Invalidate all cache entries in a particular address
	129	* space.
	130	*/
	131	ENTRY(arm1026_flush_user_cache_all)
	132	/* FALLTHROUGH */
	133	/*
	134	* flush_kern_cache_all()
	135	*
	136	* Clean and invalidate the entire cache.
	137	*/
	138	ENTRY(arm1026_flush_kern_cache_all)
	139	mov r2, #VM_EXEC
	140	mov ip, #0
	141	__flush_whole_cache:
	142	#ifndef CONFIG_CPU_DCACHE_DISABLE
	143	1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
	144	bne 1b
	145	#endif
	146	tst r2, #VM_EXEC
	147	#ifndef CONFIG_CPU_ICACHE_DISABLE
	148	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	149	#endif
	150	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	151	mov pc, lr
	152
	153	/*
	154	* flush_user_cache_range(start, end, flags)
	155	*
	156	* Invalidate a range of cache entries in the specified
	157	* address space.
	158	*
	159	* - start - start address (inclusive)
	160	* - end - end address (exclusive)
	161	* - flags - vm_flags for this space
	162	*/
	163	ENTRY(arm1026_flush_user_cache_range)
	164	mov ip, #0
	165	sub r3, r1, r0 @ calculate total size
	166	cmp r3, #CACHE_DLIMIT
	167	bhs __flush_whole_cache
	168
	169	#ifndef CONFIG_CPU_DCACHE_DISABLE
	170	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	171	add r0, r0, #CACHE_DLINESIZE
	172	cmp r0, r1
	173	blo 1b
	174	#endif
	175	tst r2, #VM_EXEC
	176	#ifndef CONFIG_CPU_ICACHE_DISABLE
	177	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	178	#endif
	179	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	180	mov pc, lr
	181
	182	/*
	183	* coherent_kern_range(start, end)
	184	*
	185	* Ensure coherency between the Icache and the Dcache in the
	186	* region described by start. If you have non-snooping
	187	* Harvard caches, you need to implement this function.
	188	*
189	* - start - virtual start address
190	* - end - virtual end address
191	*/
192	ENTRY(arm1026_coherent_kern_range)
193	/* FALLTHROUGH */
194	/*
195	* coherent_user_range(start, end)
196	*
197	* Ensure coherency between the Icache and the Dcache in the
198	* region described by start. If you have non-snooping
199	* Harvard caches, you need to implement this function.
200	*
201	* - start - virtual start address
202	* - end - virtual end address
203	*/
204	ENTRY(arm1026_coherent_user_range)
205	mov ip, #0
206	bic r0, r0, #CACHE_DLINESIZE - 1
207	1:
208	#ifndef CONFIG_CPU_DCACHE_DISABLE
209	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
210	#endif
211	#ifndef CONFIG_CPU_ICACHE_DISABLE
212	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
213	#endif
214	add r0, r0, #CACHE_DLINESIZE
215	cmp r0, r1
216	blo 1b
217	mcr p15, 0, ip, c7, c10, 4 @ drain WB
218	mov pc, lr
219
220	/*
2c9b9c84	221	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	222	*
	223	* Ensure no D cache aliasing occurs, either with itself or
	224	* the I cache
	225	*
2c9b9c84 RK	226	* - addr - kernel address
2c9b9c84 RK	227	* - size - region size
1da177e4	228	*/
2c9b9c84	229	ENTRY(arm1026_flush_kern_dcache_area)
1da177e4 LT	230	mov ip, #0
1da177e4 LT	231	#ifndef CONFIG_CPU_DCACHE_DISABLE
2c9b9c84	232	add r1, r0, r1
1da177e4 LT	233	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	234	add r0, r0, #CACHE_DLINESIZE
	235	cmp r0, r1
	236	blo 1b
	237	#endif
	238	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	239	mov pc, lr
	240
	241	/*
	242	* dma_inv_range(start, end)
	243	*
	244	* Invalidate (discard) the specified virtual address range.
	245	* May not write back any entries. If 'start' or 'end'
	246	* are not cache line aligned, those lines must be written
	247	* back.
	248	*
	249	* - start - virtual start address
	250	* - end - virtual end address
	251	*
	252	* (same as v4wb)
	253	*/
702b94bf	254	arm1026_dma_inv_range:
1da177e4 LT	255	mov ip, #0
	256	#ifndef CONFIG_CPU_DCACHE_DISABLE
	257	tst r0, #CACHE_DLINESIZE - 1
	258	bic r0, r0, #CACHE_DLINESIZE - 1
	259	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	260	tst r1, #CACHE_DLINESIZE - 1
	261	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	262	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	263	add r0, r0, #CACHE_DLINESIZE
	264	cmp r0, r1
	265	blo 1b
	266	#endif
	267	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	268	mov pc, lr
	269
	270	/*
	271	* dma_clean_range(start, end)
	272	*
	273	* Clean the specified virtual address range.
	274	*
	275	* - start - virtual start address
	276	* - end - virtual end address
	277	*
	278	* (same as v4wb)
	279	*/
702b94bf	280	arm1026_dma_clean_range:
1da177e4 LT	281	mov ip, #0
	282	#ifndef CONFIG_CPU_DCACHE_DISABLE
	283	bic r0, r0, #CACHE_DLINESIZE - 1
	284	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	285	add r0, r0, #CACHE_DLINESIZE
	286	cmp r0, r1
	287	blo 1b
	288	#endif
	289	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	290	mov pc, lr
	291
	292	/*
	293	* dma_flush_range(start, end)
	294	*
	295	* Clean and invalidate the specified virtual address range.
	296	*
	297	* - start - virtual start address
	298	* - end - virtual end address
	299	*/
	300	ENTRY(arm1026_dma_flush_range)
	301	mov ip, #0
	302	#ifndef CONFIG_CPU_DCACHE_DISABLE
	303	bic r0, r0, #CACHE_DLINESIZE - 1
	304	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	305	add r0, r0, #CACHE_DLINESIZE
	306	cmp r0, r1
	307	blo 1b
	308	#endif
	309	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	310	mov pc, lr
	311
a9c9147e RK	312	/*
	313	* dma_map_area(start, size, dir)
	314	* - start - kernel virtual start address
	315	* - size - size of region
	316	* - dir - DMA direction
	317	*/
	318	ENTRY(arm1026_dma_map_area)
	319	add r1, r1, r0
	320	cmp r2, #DMA_TO_DEVICE
	321	beq arm1026_dma_clean_range
	322	bcs arm1026_dma_inv_range
	323	b arm1026_dma_flush_range
	324	ENDPROC(arm1026_dma_map_area)
	325
	326	/*
	327	* dma_unmap_area(start, size, dir)
	328	* - start - kernel virtual start address
	329	* - size - size of region
	330	* - dir - DMA direction
	331	*/
	332	ENTRY(arm1026_dma_unmap_area)
	333	mov pc, lr
	334	ENDPROC(arm1026_dma_unmap_area)
	335
1da177e4	336	ENTRY(arm1026_cache_fns)
c8c90860	337	.long arm1026_flush_icache_all
1da177e4 LT	338	.long arm1026_flush_kern_cache_all
	339	.long arm1026_flush_user_cache_all
	340	.long arm1026_flush_user_cache_range
	341	.long arm1026_coherent_kern_range
	342	.long arm1026_coherent_user_range
2c9b9c84	343	.long arm1026_flush_kern_dcache_area
a9c9147e RK	344	.long arm1026_dma_map_area
a9c9147e RK	345	.long arm1026_dma_unmap_area
1da177e4 LT	346	.long arm1026_dma_flush_range
	347
	348	.align 5
	349	ENTRY(cpu_arm1026_dcache_clean_area)
	350	#ifndef CONFIG_CPU_DCACHE_DISABLE
	351	mov ip, #0
	352	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	353	add r0, r0, #CACHE_DLINESIZE
	354	subs r1, r1, #CACHE_DLINESIZE
	355	bhi 1b
	356	#endif
	357	mov pc, lr
	358
	359	/* =============================== PageTable ============================== */
	360
	361	/*
	362	* cpu_arm1026_switch_mm(pgd)
	363	*
	364	* Set the translation base pointer to be as described by pgd.
	365	*
	366	* pgd: new page tables
	367	*/
	368	.align 5
	369	ENTRY(cpu_arm1026_switch_mm)
d090ddda	370	#ifdef CONFIG_MMU
1da177e4 LT	371	mov r1, #0
	372	#ifndef CONFIG_CPU_DCACHE_DISABLE
	373	1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
	374	bne 1b
	375	#endif
	376	#ifndef CONFIG_CPU_ICACHE_DISABLE
	377	mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
	378	#endif
	379	mcr p15, 0, r1, c7, c10, 4 @ drain WB
	380	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	381	mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	382	#endif
1da177e4 LT	383	mov pc, lr
	384
	385	/*
ad1ae2fe	386	* cpu_arm1026_set_pte_ext(ptep, pte, ext)
1da177e4 LT	387	*
	388	* Set a PTE and flush it out
	389	*/
	390	.align 5
ad1ae2fe	391	ENTRY(cpu_arm1026_set_pte_ext)
d090ddda	392	#ifdef CONFIG_MMU
da091653	393	armv3_set_pte_ext
1da177e4 LT	394	mov r0, r0
	395	#ifndef CONFIG_CPU_DCACHE_DISABLE
	396	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	397	#endif
d090ddda	398	#endif /* CONFIG_MMU */
1da177e4 LT	399	mov pc, lr
	400
	401
5085f3ff	402	__CPUINIT
1da177e4 LT	403
	404	.type __arm1026_setup, #function
	405	__arm1026_setup:
	406	mov r0, #0
	407	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	408	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	409	#ifdef CONFIG_MMU
1da177e4 LT	410	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
1da177e4 LT	411	mcr p15, 0, r4, c2, c0 @ load page table pointer
d090ddda	412	#endif
1da177e4 LT	413	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	414	mov r0, #4 @ explicitly disable writeback
	415	mcr p15, 7, r0, c15, c0, 0
	416	#endif
22b19086 RK	417	adr r5, arm1026_crval
22b19086 RK	418	ldmia r5, {r5, r6}
1da177e4	419	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	420	bic r0, r0, r5
22b19086	421	orr r0, r0, r6
1da177e4 LT	422	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	423	orr r0, r0, #0x4000 @ .R.. .... .... ....
	424	#endif
	425	mov pc, lr
	426	.size __arm1026_setup, . - __arm1026_setup
	427
	428	/*
	429	* R
	430	* .RVI ZFRS BLDP WCAM
	431	* .011 1001 ..11 0101
	432	*
	433	*/
22b19086 RK	434	.type arm1026_crval, #object
	435	arm1026_crval:
	436	crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
1da177e4 LT	437
	438	__INITDATA
	439
	440	/*
	441	* Purpose : Function pointers used to access above functions - all calls
	442	* come through these
	443	*/
	444	.type arm1026_processor_functions, #object
	445	arm1026_processor_functions:
	446	.word v5t_early_abort
4fb28474	447	.word legacy_pabort
1da177e4 LT	448	.word cpu_arm1026_proc_init
	449	.word cpu_arm1026_proc_fin
	450	.word cpu_arm1026_reset
	451	.word cpu_arm1026_do_idle
	452	.word cpu_arm1026_dcache_clean_area
	453	.word cpu_arm1026_switch_mm
ad1ae2fe	454	.word cpu_arm1026_set_pte_ext
1da177e4 LT	455	.size arm1026_processor_functions, . - arm1026_processor_functions
	456
	457	.section .rodata
	458
	459	.type cpu_arch_name, #object
	460	cpu_arch_name:
	461	.asciz "armv5tej"
	462	.size cpu_arch_name, . - cpu_arch_name
	463
	464	.type cpu_elf_name, #object
	465	cpu_elf_name:
	466	.asciz "v5"
	467	.size cpu_elf_name, . - cpu_elf_name
	468	.align
	469
	470	.type cpu_arm1026_name, #object
	471	cpu_arm1026_name:
264edb35	472	.asciz "ARM1026EJ-S"
1da177e4 LT	473	.size cpu_arm1026_name, . - cpu_arm1026_name
	474
	475	.align
	476
02b7dd12	477	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	478
	479	.type __arm1026_proc_info,#object
	480	__arm1026_proc_info:
	481	.long 0x4106a260 @ ARM 1026EJ-S (v5TEJ)
	482	.long 0xff0ffff0
8799ee9f RK	483	.long PMD_TYPE_SECT \| \
	484	PMD_BIT4 \| \
	485	PMD_SECT_AP_WRITE \| \
	486	PMD_SECT_AP_READ
1da177e4 LT	487	.long PMD_TYPE_SECT \| \
	488	PMD_BIT4 \| \
	489	PMD_SECT_AP_WRITE \| \
	490	PMD_SECT_AP_READ
	491	b __arm1026_setup
	492	.long cpu_arch_name
	493	.long cpu_elf_name
	494	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_JAVA
	495	.long cpu_arm1026_name
	496	.long arm1026_processor_functions
	497	.long v4wbi_tlb_fns
	498	.long v4wb_user_fns
	499	.long arm1026_cache_fns
	500	.size __arm1026_proc_info, . - __arm1026_proc_info