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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/bootmem.h> | |
15 | #include <linux/mman.h> | |
16 | #include <linux/nodemask.h> | |
17 | ||
18 | #include <asm/mach-types.h> | |
19 | #include <asm/setup.h> | |
20 | #include <asm/sizes.h> | |
21 | #include <asm/tlb.h> | |
22 | ||
23 | #include <asm/mach/arch.h> | |
24 | #include <asm/mach/map.h> | |
25 | ||
26 | #include "mm.h" | |
27 | ||
28 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); | |
29 | ||
6ae5a6ef | 30 | extern void _stext, _etext, __data_start, _end; |
d111e8f9 RK |
31 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
32 | ||
33 | /* | |
34 | * empty_zero_page is a special page that is used for | |
35 | * zero-initialized data and COW. | |
36 | */ | |
37 | struct page *empty_zero_page; | |
3653f3ab | 38 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
39 | |
40 | /* | |
41 | * The pmd table for the upper-most set of pages. | |
42 | */ | |
43 | pmd_t *top_pmd; | |
44 | ||
ae8f1541 RK |
45 | #define CPOLICY_UNCACHED 0 |
46 | #define CPOLICY_BUFFERED 1 | |
47 | #define CPOLICY_WRITETHROUGH 2 | |
48 | #define CPOLICY_WRITEBACK 3 | |
49 | #define CPOLICY_WRITEALLOC 4 | |
50 | ||
51 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
52 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 53 | pgprot_t pgprot_user; |
ae8f1541 RK |
54 | pgprot_t pgprot_kernel; |
55 | ||
44b18693 | 56 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
57 | EXPORT_SYMBOL(pgprot_kernel); |
58 | ||
59 | struct cachepolicy { | |
60 | const char policy[16]; | |
61 | unsigned int cr_mask; | |
62 | unsigned int pmd; | |
63 | unsigned int pte; | |
64 | }; | |
65 | ||
66 | static struct cachepolicy cache_policies[] __initdata = { | |
67 | { | |
68 | .policy = "uncached", | |
69 | .cr_mask = CR_W|CR_C, | |
70 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 71 | .pte = L_PTE_MT_UNCACHED, |
ae8f1541 RK |
72 | }, { |
73 | .policy = "buffered", | |
74 | .cr_mask = CR_C, | |
75 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 76 | .pte = L_PTE_MT_BUFFERABLE, |
ae8f1541 RK |
77 | }, { |
78 | .policy = "writethrough", | |
79 | .cr_mask = 0, | |
80 | .pmd = PMD_SECT_WT, | |
bb30f36f | 81 | .pte = L_PTE_MT_WRITETHROUGH, |
ae8f1541 RK |
82 | }, { |
83 | .policy = "writeback", | |
84 | .cr_mask = 0, | |
85 | .pmd = PMD_SECT_WB, | |
bb30f36f | 86 | .pte = L_PTE_MT_WRITEBACK, |
ae8f1541 RK |
87 | }, { |
88 | .policy = "writealloc", | |
89 | .cr_mask = 0, | |
90 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 91 | .pte = L_PTE_MT_WRITEALLOC, |
ae8f1541 RK |
92 | } |
93 | }; | |
94 | ||
95 | /* | |
6cbdc8c5 | 96 | * These are useful for identifying cache coherency |
ae8f1541 RK |
97 | * problems by allowing the cache or the cache and |
98 | * writebuffer to be turned off. (Note: the write | |
99 | * buffer should not be on and the cache off). | |
100 | */ | |
101 | static void __init early_cachepolicy(char **p) | |
102 | { | |
103 | int i; | |
104 | ||
105 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
106 | int len = strlen(cache_policies[i].policy); | |
107 | ||
108 | if (memcmp(*p, cache_policies[i].policy, len) == 0) { | |
109 | cachepolicy = i; | |
110 | cr_alignment &= ~cache_policies[i].cr_mask; | |
111 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
112 | *p += len; | |
113 | break; | |
114 | } | |
115 | } | |
116 | if (i == ARRAY_SIZE(cache_policies)) | |
117 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
11179d8c CM |
118 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
119 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
120 | cachepolicy = CPOLICY_WRITEBACK; | |
121 | } | |
ae8f1541 RK |
122 | flush_cache_all(); |
123 | set_cr(cr_alignment); | |
124 | } | |
125 | __early_param("cachepolicy=", early_cachepolicy); | |
126 | ||
127 | static void __init early_nocache(char **__unused) | |
128 | { | |
129 | char *p = "buffered"; | |
130 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
131 | early_cachepolicy(&p); | |
132 | } | |
133 | __early_param("nocache", early_nocache); | |
134 | ||
135 | static void __init early_nowrite(char **__unused) | |
136 | { | |
137 | char *p = "uncached"; | |
138 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
139 | early_cachepolicy(&p); | |
140 | } | |
141 | __early_param("nowb", early_nowrite); | |
142 | ||
143 | static void __init early_ecc(char **p) | |
144 | { | |
145 | if (memcmp(*p, "on", 2) == 0) { | |
146 | ecc_mask = PMD_PROTECTION; | |
147 | *p += 2; | |
148 | } else if (memcmp(*p, "off", 3) == 0) { | |
149 | ecc_mask = 0; | |
150 | *p += 3; | |
151 | } | |
152 | } | |
153 | __early_param("ecc=", early_ecc); | |
154 | ||
155 | static int __init noalign_setup(char *__unused) | |
156 | { | |
157 | cr_alignment &= ~CR_A; | |
158 | cr_no_alignment &= ~CR_A; | |
159 | set_cr(cr_alignment); | |
160 | return 1; | |
161 | } | |
162 | __setup("noalign", noalign_setup); | |
163 | ||
255d1f86 RK |
164 | #ifndef CONFIG_SMP |
165 | void adjust_cr(unsigned long mask, unsigned long set) | |
166 | { | |
167 | unsigned long flags; | |
168 | ||
169 | mask &= ~CR_A; | |
170 | ||
171 | set &= mask; | |
172 | ||
173 | local_irq_save(flags); | |
174 | ||
175 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
176 | cr_alignment = (cr_alignment & ~mask) | set; | |
177 | ||
178 | set_cr((get_cr() & ~mask) | set); | |
179 | ||
180 | local_irq_restore(flags); | |
181 | } | |
182 | #endif | |
183 | ||
0af92bef RK |
184 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE |
185 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE | |
186 | ||
b29e9f5e | 187 | static struct mem_type mem_types[] = { |
0af92bef | 188 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
189 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
190 | L_PTE_SHARED, | |
0af92bef RK |
191 | .prot_l1 = PMD_TYPE_TABLE, |
192 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED, | |
193 | .domain = DOMAIN_IO, | |
194 | }, | |
195 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 196 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef RK |
197 | .prot_l1 = PMD_TYPE_TABLE, |
198 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2), | |
199 | .domain = DOMAIN_IO, | |
200 | }, | |
201 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 202 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
203 | .prot_l1 = PMD_TYPE_TABLE, |
204 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
205 | .domain = DOMAIN_IO, | |
206 | }, | |
207 | [MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */ | |
bb30f36f | 208 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_IXP2000, |
0af92bef RK |
209 | .prot_l1 = PMD_TYPE_TABLE, |
210 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE | | |
211 | PMD_SECT_TEX(1), | |
212 | .domain = DOMAIN_IO, | |
ae8f1541 | 213 | }, |
1ad77a87 | 214 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 215 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
1ad77a87 | 216 | .prot_l1 = PMD_TYPE_TABLE, |
bb30f36f | 217 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE, |
1ad77a87 LB |
218 | .domain = DOMAIN_IO, |
219 | }, | |
ae8f1541 | 220 | [MT_CACHECLEAN] = { |
9ef79635 | 221 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
222 | .domain = DOMAIN_KERNEL, |
223 | }, | |
224 | [MT_MINICLEAN] = { | |
9ef79635 | 225 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
226 | .domain = DOMAIN_KERNEL, |
227 | }, | |
228 | [MT_LOW_VECTORS] = { | |
229 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
230 | L_PTE_EXEC, | |
231 | .prot_l1 = PMD_TYPE_TABLE, | |
232 | .domain = DOMAIN_USER, | |
233 | }, | |
234 | [MT_HIGH_VECTORS] = { | |
235 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
236 | L_PTE_USER | L_PTE_EXEC, | |
237 | .prot_l1 = PMD_TYPE_TABLE, | |
238 | .domain = DOMAIN_USER, | |
239 | }, | |
240 | [MT_MEMORY] = { | |
9ef79635 | 241 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
242 | .domain = DOMAIN_KERNEL, |
243 | }, | |
244 | [MT_ROM] = { | |
9ef79635 | 245 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
246 | .domain = DOMAIN_KERNEL, |
247 | }, | |
ae8f1541 RK |
248 | }; |
249 | ||
b29e9f5e RK |
250 | const struct mem_type *get_mem_type(unsigned int type) |
251 | { | |
252 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
253 | } | |
254 | ||
ae8f1541 RK |
255 | /* |
256 | * Adjust the PMD section entries according to the CPU in use. | |
257 | */ | |
258 | static void __init build_mem_type_table(void) | |
259 | { | |
260 | struct cachepolicy *cp; | |
261 | unsigned int cr = get_cr(); | |
bb30f36f | 262 | unsigned int user_pgprot, kern_pgprot, vecs_pgprot; |
ae8f1541 RK |
263 | int cpu_arch = cpu_architecture(); |
264 | int i; | |
265 | ||
11179d8c | 266 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 267 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
268 | if (cachepolicy > CPOLICY_BUFFERED) |
269 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 270 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
271 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
272 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 273 | #endif |
11179d8c | 274 | } |
ae8f1541 RK |
275 | if (cpu_arch < CPU_ARCH_ARMv5) { |
276 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
277 | cachepolicy = CPOLICY_WRITEBACK; | |
278 | ecc_mask = 0; | |
279 | } | |
bb30f36f RK |
280 | #ifdef CONFIG_SMP |
281 | cachepolicy = CPOLICY_WRITEALLOC; | |
282 | #endif | |
ae8f1541 | 283 | |
1ad77a87 LB |
284 | /* |
285 | * On non-Xscale3 ARMv5-and-older systems, use CB=01 | |
286 | * (Uncached/Buffered) for ioremap_wc() mappings. On XScale3 | |
287 | * and ARMv6+, use TEXCB=00100 mappings (Inner/Outer Uncacheable | |
288 | * in xsc3 parlance, Uncached Normal in ARMv6 parlance). | |
289 | */ | |
290 | if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) { | |
1ad77a87 | 291 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); |
bb30f36f | 292 | mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE; |
1ad77a87 LB |
293 | } |
294 | ||
ae8f1541 | 295 | /* |
9ef79635 RK |
296 | * ARMv5 and lower, bit 4 must be set for page tables. |
297 | * (was: cache "update-able on write" bit on ARM610) | |
298 | * However, Xscale cores require this bit to be cleared. | |
ae8f1541 | 299 | */ |
9ef79635 RK |
300 | if (cpu_is_xscale()) { |
301 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 | 302 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
303 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
304 | } | |
305 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
306 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
307 | if (mem_types[i].prot_l1) |
308 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
309 | if (mem_types[i].prot_sect) |
310 | mem_types[i].prot_sect |= PMD_BIT4; | |
311 | } | |
312 | } | |
ae8f1541 RK |
313 | |
314 | cp = &cache_policies[cachepolicy]; | |
bb30f36f RK |
315 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
316 | ||
317 | #ifndef CONFIG_SMP | |
318 | /* | |
319 | * Only use write-through for non-SMP systems | |
320 | */ | |
321 | if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) | |
322 | vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; | |
323 | #endif | |
ae8f1541 RK |
324 | |
325 | /* | |
326 | * Enable CPU-specific coherency if supported. | |
327 | * (Only available on XSC3 at the moment.) | |
328 | */ | |
329 | if (arch_is_coherent()) { | |
330 | if (cpu_is_xsc3()) { | |
331 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | |
0e5fdca7 | 332 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; |
ae8f1541 RK |
333 | } |
334 | } | |
335 | ||
336 | /* | |
337 | * ARMv6 and above have extended page tables. | |
338 | */ | |
339 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
ae8f1541 RK |
340 | /* |
341 | * Mark cache clean areas and XIP ROM read only | |
342 | * from SVC mode and no access from userspace. | |
343 | */ | |
344 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
345 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
346 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
347 | ||
348 | /* | |
349 | * Mark the device area as "shared device" | |
350 | */ | |
ae8f1541 RK |
351 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; |
352 | ||
ae8f1541 RK |
353 | #ifdef CONFIG_SMP |
354 | /* | |
355 | * Mark memory with the "shared" attribute for SMP systems | |
356 | */ | |
357 | user_pgprot |= L_PTE_SHARED; | |
358 | kern_pgprot |= L_PTE_SHARED; | |
bb30f36f | 359 | vecs_pgprot |= L_PTE_SHARED; |
ae8f1541 RK |
360 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
361 | #endif | |
362 | } | |
363 | ||
364 | for (i = 0; i < 16; i++) { | |
365 | unsigned long v = pgprot_val(protection_map[i]); | |
bb30f36f | 366 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
367 | } |
368 | ||
bb30f36f RK |
369 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
370 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 371 | |
bb30f36f | 372 | if (cpu_arch < CPU_ARCH_ARMv5) |
ae8f1541 | 373 | mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1); |
ae8f1541 | 374 | |
44b18693 | 375 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 RK |
376 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
377 | L_PTE_DIRTY | L_PTE_WRITE | | |
378 | L_PTE_EXEC | kern_pgprot); | |
379 | ||
380 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
381 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
382 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; | |
383 | mem_types[MT_ROM].prot_sect |= cp->pmd; | |
384 | ||
385 | switch (cp->pmd) { | |
386 | case PMD_SECT_WT: | |
387 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
388 | break; | |
389 | case PMD_SECT_WB: | |
390 | case PMD_SECT_WBWA: | |
391 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
392 | break; | |
393 | } | |
394 | printk("Memory policy: ECC %sabled, Data cache %s\n", | |
395 | ecc_mask ? "en" : "dis", cp->policy); | |
2497f0a8 RK |
396 | |
397 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
398 | struct mem_type *t = &mem_types[i]; | |
399 | if (t->prot_l1) | |
400 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
401 | if (t->prot_sect) | |
402 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
403 | } | |
ae8f1541 RK |
404 | } |
405 | ||
406 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) | |
407 | ||
24e6c699 RK |
408 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
409 | unsigned long end, unsigned long pfn, | |
410 | const struct mem_type *type) | |
ae8f1541 | 411 | { |
24e6c699 | 412 | pte_t *pte; |
ae8f1541 | 413 | |
24e6c699 RK |
414 | if (pmd_none(*pmd)) { |
415 | pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); | |
416 | __pmd_populate(pmd, __pa(pte) | type->prot_l1); | |
417 | } | |
ae8f1541 | 418 | |
24e6c699 RK |
419 | pte = pte_offset_kernel(pmd, addr); |
420 | do { | |
c172cc92 RK |
421 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), |
422 | type->prot_pte_ext); | |
24e6c699 RK |
423 | pfn++; |
424 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
425 | } |
426 | ||
24e6c699 RK |
427 | static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, |
428 | unsigned long end, unsigned long phys, | |
429 | const struct mem_type *type) | |
ae8f1541 | 430 | { |
24e6c699 | 431 | pmd_t *pmd = pmd_offset(pgd, addr); |
ae8f1541 | 432 | |
24e6c699 RK |
433 | /* |
434 | * Try a section mapping - end, addr and phys must all be aligned | |
435 | * to a section boundary. Note that PMDs refer to the individual | |
436 | * L1 entries, whereas PGDs refer to a group of L1 entries making | |
437 | * up one logical pointer to an L2 table. | |
438 | */ | |
439 | if (((addr | end | phys) & ~SECTION_MASK) == 0) { | |
440 | pmd_t *p = pmd; | |
ae8f1541 | 441 | |
24e6c699 RK |
442 | if (addr & SECTION_SIZE) |
443 | pmd++; | |
444 | ||
445 | do { | |
446 | *pmd = __pmd(phys | type->prot_sect); | |
447 | phys += SECTION_SIZE; | |
448 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
ae8f1541 | 449 | |
24e6c699 RK |
450 | flush_pmd_entry(p); |
451 | } else { | |
452 | /* | |
453 | * No need to loop; pte's aren't interested in the | |
454 | * individual L1 entries. | |
455 | */ | |
456 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); | |
457 | } | |
ae8f1541 RK |
458 | } |
459 | ||
4a56c1e4 RK |
460 | static void __init create_36bit_mapping(struct map_desc *md, |
461 | const struct mem_type *type) | |
462 | { | |
463 | unsigned long phys, addr, length, end; | |
464 | pgd_t *pgd; | |
465 | ||
466 | addr = md->virtual; | |
467 | phys = (unsigned long)__pfn_to_phys(md->pfn); | |
468 | length = PAGE_ALIGN(md->length); | |
469 | ||
470 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
471 | printk(KERN_ERR "MM: CPU does not support supersection " | |
472 | "mapping for 0x%08llx at 0x%08lx\n", | |
473 | __pfn_to_phys((u64)md->pfn), addr); | |
474 | return; | |
475 | } | |
476 | ||
477 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
478 | * Since domain assignments can in fact be arbitrary, the | |
479 | * 'domain == 0' check below is required to insure that ARMv6 | |
480 | * supersections are only allocated for domain 0 regardless | |
481 | * of the actual domain assignments in use. | |
482 | */ | |
483 | if (type->domain) { | |
484 | printk(KERN_ERR "MM: invalid domain in supersection " | |
485 | "mapping for 0x%08llx at 0x%08lx\n", | |
486 | __pfn_to_phys((u64)md->pfn), addr); | |
487 | return; | |
488 | } | |
489 | ||
490 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
491 | printk(KERN_ERR "MM: cannot create mapping for " | |
492 | "0x%08llx at 0x%08lx invalid alignment\n", | |
493 | __pfn_to_phys((u64)md->pfn), addr); | |
494 | return; | |
495 | } | |
496 | ||
497 | /* | |
498 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
499 | * (See ARMv6 spec). | |
500 | */ | |
501 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
502 | ||
503 | pgd = pgd_offset_k(addr); | |
504 | end = addr + length; | |
505 | do { | |
506 | pmd_t *pmd = pmd_offset(pgd, addr); | |
507 | int i; | |
508 | ||
509 | for (i = 0; i < 16; i++) | |
510 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
511 | ||
512 | addr += SUPERSECTION_SIZE; | |
513 | phys += SUPERSECTION_SIZE; | |
514 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
515 | } while (addr != end); | |
516 | } | |
517 | ||
ae8f1541 RK |
518 | /* |
519 | * Create the page directory entries and any necessary | |
520 | * page tables for the mapping specified by `md'. We | |
521 | * are able to cope here with varying sizes and address | |
522 | * offsets, and we take full advantage of sections and | |
523 | * supersections. | |
524 | */ | |
525 | void __init create_mapping(struct map_desc *md) | |
526 | { | |
24e6c699 | 527 | unsigned long phys, addr, length, end; |
d5c98176 | 528 | const struct mem_type *type; |
24e6c699 | 529 | pgd_t *pgd; |
ae8f1541 RK |
530 | |
531 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
532 | printk(KERN_WARNING "BUG: not creating mapping for " | |
533 | "0x%08llx at 0x%08lx in user region\n", | |
534 | __pfn_to_phys((u64)md->pfn), md->virtual); | |
535 | return; | |
536 | } | |
537 | ||
538 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
539 | md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { | |
540 | printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " | |
541 | "overlaps vmalloc space\n", | |
542 | __pfn_to_phys((u64)md->pfn), md->virtual); | |
543 | } | |
544 | ||
d5c98176 | 545 | type = &mem_types[md->type]; |
ae8f1541 RK |
546 | |
547 | /* | |
548 | * Catch 36-bit addresses | |
549 | */ | |
4a56c1e4 RK |
550 | if (md->pfn >= 0x100000) { |
551 | create_36bit_mapping(md, type); | |
552 | return; | |
ae8f1541 RK |
553 | } |
554 | ||
7b9c7b4d | 555 | addr = md->virtual & PAGE_MASK; |
24e6c699 | 556 | phys = (unsigned long)__pfn_to_phys(md->pfn); |
7b9c7b4d | 557 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 558 | |
24e6c699 | 559 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
ae8f1541 RK |
560 | printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " |
561 | "be mapped using pages, ignoring.\n", | |
24e6c699 | 562 | __pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
563 | return; |
564 | } | |
565 | ||
24e6c699 RK |
566 | pgd = pgd_offset_k(addr); |
567 | end = addr + length; | |
568 | do { | |
569 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 570 | |
24e6c699 | 571 | alloc_init_section(pgd, addr, next, phys, type); |
ae8f1541 | 572 | |
24e6c699 RK |
573 | phys += next - addr; |
574 | addr = next; | |
575 | } while (pgd++, addr != end); | |
ae8f1541 RK |
576 | } |
577 | ||
578 | /* | |
579 | * Create the architecture specific mappings | |
580 | */ | |
581 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
582 | { | |
583 | int i; | |
584 | ||
585 | for (i = 0; i < nr; i++) | |
586 | create_mapping(io_desc + i); | |
587 | } | |
588 | ||
60296c71 LB |
589 | static int __init check_membank_valid(struct membank *mb) |
590 | { | |
591 | /* | |
592 | * Check whether this memory region has non-zero size. | |
593 | */ | |
594 | if (mb->size == 0) | |
595 | return 0; | |
596 | ||
597 | /* | |
598 | * Check whether this memory region would entirely overlap | |
599 | * the vmalloc area. | |
600 | */ | |
601 | if (phys_to_virt(mb->start) >= VMALLOC_MIN) { | |
602 | printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " | |
603 | "(vmalloc region overlap).\n", | |
604 | mb->start, mb->start + mb->size - 1); | |
605 | return 0; | |
606 | } | |
607 | ||
608 | /* | |
609 | * Check whether this memory region would partially overlap | |
610 | * the vmalloc area. | |
611 | */ | |
612 | if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) || | |
613 | phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) { | |
614 | unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start); | |
615 | ||
616 | printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " | |
617 | "to -%.8lx (vmalloc region overlap).\n", | |
618 | mb->start, mb->start + mb->size - 1, | |
619 | mb->start + newsize - 1); | |
620 | mb->size = newsize; | |
621 | } | |
622 | ||
623 | return 1; | |
624 | } | |
625 | ||
626 | static void __init sanity_check_meminfo(struct meminfo *mi) | |
627 | { | |
628 | int i; | |
629 | int j; | |
630 | ||
631 | for (i = 0, j = 0; i < mi->nr_banks; i++) { | |
632 | if (check_membank_valid(&mi->bank[i])) | |
633 | mi->bank[j++] = mi->bank[i]; | |
634 | } | |
635 | mi->nr_banks = j; | |
636 | } | |
637 | ||
d111e8f9 RK |
638 | static inline void prepare_page_table(struct meminfo *mi) |
639 | { | |
640 | unsigned long addr; | |
641 | ||
642 | /* | |
643 | * Clear out all the mappings below the kernel image. | |
644 | */ | |
645 | for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE) | |
646 | pmd_clear(pmd_off_k(addr)); | |
647 | ||
648 | #ifdef CONFIG_XIP_KERNEL | |
649 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
650 | addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK; | |
651 | #endif | |
652 | for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) | |
653 | pmd_clear(pmd_off_k(addr)); | |
654 | ||
655 | /* | |
656 | * Clear out all the kernel space mappings, except for the first | |
657 | * memory bank, up to the end of the vmalloc region. | |
658 | */ | |
659 | for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size); | |
660 | addr < VMALLOC_END; addr += PGDIR_SIZE) | |
661 | pmd_clear(pmd_off_k(addr)); | |
662 | } | |
663 | ||
664 | /* | |
665 | * Reserve the various regions of node 0 | |
666 | */ | |
667 | void __init reserve_node_zero(pg_data_t *pgdat) | |
668 | { | |
669 | unsigned long res_size = 0; | |
670 | ||
671 | /* | |
672 | * Register the kernel text and data with bootmem. | |
673 | * Note that this can only be in node 0. | |
674 | */ | |
675 | #ifdef CONFIG_XIP_KERNEL | |
72a7fe39 BW |
676 | reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start, |
677 | BOOTMEM_DEFAULT); | |
d111e8f9 | 678 | #else |
72a7fe39 BW |
679 | reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext, |
680 | BOOTMEM_DEFAULT); | |
d111e8f9 RK |
681 | #endif |
682 | ||
683 | /* | |
684 | * Reserve the page tables. These are already in use, | |
685 | * and can only be in node 0. | |
686 | */ | |
687 | reserve_bootmem_node(pgdat, __pa(swapper_pg_dir), | |
72a7fe39 | 688 | PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT); |
d111e8f9 RK |
689 | |
690 | /* | |
691 | * Hmm... This should go elsewhere, but we really really need to | |
692 | * stop things allocating the low memory; ideally we need a better | |
693 | * implementation of GFP_DMA which does not assume that DMA-able | |
694 | * memory starts at zero. | |
695 | */ | |
696 | if (machine_is_integrator() || machine_is_cintegrator()) | |
697 | res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; | |
698 | ||
699 | /* | |
700 | * These should likewise go elsewhere. They pre-reserve the | |
701 | * screen memory region at the start of main system memory. | |
702 | */ | |
703 | if (machine_is_edb7211()) | |
704 | res_size = 0x00020000; | |
705 | if (machine_is_p720t()) | |
706 | res_size = 0x00014000; | |
707 | ||
bbf6f280 BD |
708 | /* H1940 and RX3715 need to reserve this for suspend */ |
709 | ||
710 | if (machine_is_h1940() || machine_is_rx3715()) { | |
72a7fe39 BW |
711 | reserve_bootmem_node(pgdat, 0x30003000, 0x1000, |
712 | BOOTMEM_DEFAULT); | |
713 | reserve_bootmem_node(pgdat, 0x30081000, 0x1000, | |
714 | BOOTMEM_DEFAULT); | |
9073341c BD |
715 | } |
716 | ||
d111e8f9 RK |
717 | #ifdef CONFIG_SA1111 |
718 | /* | |
719 | * Because of the SA1111 DMA bug, we want to preserve our | |
720 | * precious DMA-able memory... | |
721 | */ | |
722 | res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; | |
723 | #endif | |
724 | if (res_size) | |
72a7fe39 BW |
725 | reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size, |
726 | BOOTMEM_DEFAULT); | |
d111e8f9 RK |
727 | } |
728 | ||
729 | /* | |
730 | * Set up device the mappings. Since we clear out the page tables for all | |
731 | * mappings above VMALLOC_END, we will remove any debug device mappings. | |
732 | * This means you have to be careful how you debug this function, or any | |
733 | * called function. This means you can't use any function or debugging | |
734 | * method which may touch any device, otherwise the kernel _will_ crash. | |
735 | */ | |
736 | static void __init devicemaps_init(struct machine_desc *mdesc) | |
737 | { | |
738 | struct map_desc map; | |
739 | unsigned long addr; | |
740 | void *vectors; | |
741 | ||
742 | /* | |
743 | * Allocate the vector page early. | |
744 | */ | |
745 | vectors = alloc_bootmem_low_pages(PAGE_SIZE); | |
746 | BUG_ON(!vectors); | |
747 | ||
748 | for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) | |
749 | pmd_clear(pmd_off_k(addr)); | |
750 | ||
751 | /* | |
752 | * Map the kernel if it is XIP. | |
753 | * It is always first in the modulearea. | |
754 | */ | |
755 | #ifdef CONFIG_XIP_KERNEL | |
756 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
757 | map.virtual = MODULE_START; | |
758 | map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; | |
759 | map.type = MT_ROM; | |
760 | create_mapping(&map); | |
761 | #endif | |
762 | ||
763 | /* | |
764 | * Map the cache flushing regions. | |
765 | */ | |
766 | #ifdef FLUSH_BASE | |
767 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
768 | map.virtual = FLUSH_BASE; | |
769 | map.length = SZ_1M; | |
770 | map.type = MT_CACHECLEAN; | |
771 | create_mapping(&map); | |
772 | #endif | |
773 | #ifdef FLUSH_BASE_MINICACHE | |
774 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
775 | map.virtual = FLUSH_BASE_MINICACHE; | |
776 | map.length = SZ_1M; | |
777 | map.type = MT_MINICLEAN; | |
778 | create_mapping(&map); | |
779 | #endif | |
780 | ||
781 | /* | |
782 | * Create a mapping for the machine vectors at the high-vectors | |
783 | * location (0xffff0000). If we aren't using high-vectors, also | |
784 | * create a mapping at the low-vectors virtual address. | |
785 | */ | |
786 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); | |
787 | map.virtual = 0xffff0000; | |
788 | map.length = PAGE_SIZE; | |
789 | map.type = MT_HIGH_VECTORS; | |
790 | create_mapping(&map); | |
791 | ||
792 | if (!vectors_high()) { | |
793 | map.virtual = 0; | |
794 | map.type = MT_LOW_VECTORS; | |
795 | create_mapping(&map); | |
796 | } | |
797 | ||
798 | /* | |
799 | * Ask the machine support to map in the statically mapped devices. | |
800 | */ | |
801 | if (mdesc->map_io) | |
802 | mdesc->map_io(); | |
803 | ||
804 | /* | |
805 | * Finally flush the caches and tlb to ensure that we're in a | |
806 | * consistent state wrt the writebuffer. This also ensures that | |
807 | * any write-allocated cache lines in the vector page are written | |
808 | * back. After this point, we can start to touch devices again. | |
809 | */ | |
810 | local_flush_tlb_all(); | |
811 | flush_cache_all(); | |
812 | } | |
813 | ||
814 | /* | |
815 | * paging_init() sets up the page tables, initialises the zone memory | |
816 | * maps, and sets up the zero page, bad page and bad page tables. | |
817 | */ | |
818 | void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc) | |
819 | { | |
820 | void *zero_page; | |
821 | ||
822 | build_mem_type_table(); | |
60296c71 | 823 | sanity_check_meminfo(mi); |
d111e8f9 RK |
824 | prepare_page_table(mi); |
825 | bootmem_init(mi); | |
826 | devicemaps_init(mdesc); | |
827 | ||
828 | top_pmd = pmd_off_k(0xffff0000); | |
829 | ||
830 | /* | |
831 | * allocate the zero page. Note that we count on this going ok. | |
832 | */ | |
833 | zero_page = alloc_bootmem_low_pages(PAGE_SIZE); | |
834 | memzero(zero_page, PAGE_SIZE); | |
835 | empty_zero_page = virt_to_page(zero_page); | |
836 | flush_dcache_page(empty_zero_page); | |
837 | } | |
ae8f1541 RK |
838 | |
839 | /* | |
840 | * In order to soft-boot, we need to insert a 1:1 mapping in place of | |
841 | * the user-mode pages. This will then ensure that we have predictable | |
842 | * results when turning the mmu off | |
843 | */ | |
844 | void setup_mm_for_reboot(char mode) | |
845 | { | |
846 | unsigned long base_pmdval; | |
847 | pgd_t *pgd; | |
848 | int i; | |
849 | ||
850 | if (current->mm && current->mm->pgd) | |
851 | pgd = current->mm->pgd; | |
852 | else | |
853 | pgd = init_mm.pgd; | |
854 | ||
855 | base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; | |
856 | if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) | |
857 | base_pmdval |= PMD_BIT4; | |
858 | ||
859 | for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { | |
860 | unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; | |
861 | pmd_t *pmd; | |
862 | ||
863 | pmd = pmd_off(pgd, i << PGDIR_SHIFT); | |
864 | pmd[0] = __pmd(pmdval); | |
865 | pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); | |
866 | flush_pmd_entry(pmd); | |
867 | } | |
868 | } |