[net-next-2.6.git] / arch / arm / mm / fault-armv.c

/*
 *  linux/arch/arm/mm/fault-armv.c
 *
 *  Copyright (C) 1995  Linus Torvalds
 *  Modifications for ARM processor (c) 1995-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bitops.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/pagemap.h>
#include <linux/gfp.h>

#include <asm/bugs.h>
#include <asm/cacheflush.h>
#include <asm/cachetype.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>

#include "mm.h"

static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;

#if __LINUX_ARM_ARCH__ < 6
/*
 * We take the easy way out of this problem - we make the
 * PTE uncacheable.  However, we leave the write buffer on.
 *
 * Note that the pte lock held when calling update_mmu_cache must also
 * guard the pte (somewhere else in the same mm) that we modify here.
 * Therefore those configurations which might call adjust_pte (those
 * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
 */
static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
	unsigned long pfn, pte_t *ptep)
{
	pte_t entry = *ptep;
	int ret;

	/*
	 * If this page is present, it's actually being shared.
	 */
	ret = pte_present(entry);

	/*
	 * If this page isn't present, or is already setup to
	 * fault (ie, is old), we can safely ignore any issues.
	 */
	if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
		flush_cache_page(vma, address, pfn);
		outer_flush_range((pfn << PAGE_SHIFT),
				  (pfn << PAGE_SHIFT) + PAGE_SIZE);
		pte_val(entry) &= ~L_PTE_MT_MASK;
		pte_val(entry) |= shared_pte_mask;
		set_pte_at(vma->vm_mm, address, ptep, entry);
		flush_tlb_page(vma, address);
	}

	return ret;
}

#if USE_SPLIT_PTLOCKS
/*
 * If we are using split PTE locks, then we need to take the page
 * lock here.  Otherwise we are using shared mm->page_table_lock
 * which is already locked, thus cannot take it.
 */
static inline void do_pte_lock(spinlock_t *ptl)
{
	/*
	 * Use nested version here to indicate that we are already
	 * holding one similar spinlock.
	 */
	spin_lock_nested(ptl, SINGLE_DEPTH_NESTING);
}

static inline void do_pte_unlock(spinlock_t *ptl)
{
	spin_unlock(ptl);
}
#else /* !USE_SPLIT_PTLOCKS */
static inline void do_pte_lock(spinlock_t *ptl) {}
static inline void do_pte_unlock(spinlock_t *ptl) {}
#endif /* USE_SPLIT_PTLOCKS */

static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
	unsigned long pfn)
{
	spinlock_t *ptl;
	pgd_t *pgd;
	pmd_t *pmd;
	pte_t *pte;
	int ret;

	pgd = pgd_offset(vma->vm_mm, address);
	if (pgd_none_or_clear_bad(pgd))
		return 0;

	pmd = pmd_offset(pgd, address);
	if (pmd_none_or_clear_bad(pmd))
		return 0;

	/*
	 * This is called while another page table is mapped, so we
	 * must use the nested version.  This also means we need to
	 * open-code the spin-locking.
	 */
	ptl = pte_lockptr(vma->vm_mm, pmd);
	pte = pte_offset_map(pmd, address);
	do_pte_lock(ptl);

	ret = do_adjust_pte(vma, address, pfn, pte);

	do_pte_unlock(ptl);
	pte_unmap(pte);

	return ret;
}

static void
make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
	unsigned long addr, pte_t *ptep, unsigned long pfn)
{
	struct mm_struct *mm = vma->vm_mm;
	struct vm_area_struct *mpnt;
	struct prio_tree_iter iter;
	unsigned long offset;
	pgoff_t pgoff;
	int aliases = 0;

	pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);

	/*
	 * If we have any shared mappings that are in the same mm
	 * space, then we need to handle them specially to maintain
	 * cache coherency.
	 */
	flush_dcache_mmap_lock(mapping);
	vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
		/*
		 * If this VMA is not in our MM, we can ignore it.
		 * Note that we intentionally mask out the VMA
		 * that we are fixing up.
		 */
		if (mpnt->vm_mm != mm || mpnt == vma)
			continue;
		if (!(mpnt->vm_flags & VM_MAYSHARE))
			continue;
		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
		aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn);
	}
	flush_dcache_mmap_unlock(mapping);
	if (aliases)
		do_adjust_pte(vma, addr, pfn, ptep);
}

/*
 * Take care of architecture specific things when placing a new PTE into
 * a page table, or changing an existing PTE.  Basically, there are two
 * things that we need to take care of:
 *
 *  1. If PG_dcache_clean is not set for the page, we need to ensure
 *     that any cache entries for the kernels virtual memory
 *     range are written back to the page.
 *  2. If we have multiple shared mappings of the same space in
 *     an object, we need to deal with the cache aliasing issues.
 *
 * Note that the pte lock will be held.
 */
void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
	pte_t *ptep)
{
	unsigned long pfn = pte_pfn(*ptep);
	struct address_space *mapping;
	struct page *page;

	if (!pfn_valid(pfn))
		return;

	/*
	 * The zero page is never written to, so never has any dirty
	 * cache lines, and therefore never needs to be flushed.
	 */
	page = pfn_to_page(pfn);
	if (page == ZERO_PAGE(0))
		return;

	mapping = page_mapping(page);
	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
		__flush_dcache_page(mapping, page);
	if (mapping) {
		if (cache_is_vivt())
			make_coherent(mapping, vma, addr, ptep, pfn);
		else if (vma->vm_flags & VM_EXEC)
			__flush_icache_all();
	}
}
#endif	/* __LINUX_ARM_ARCH__ < 6 */

/*
 * Check whether the write buffer has physical address aliasing
 * issues.  If it has, we need to avoid them for the case where
 * we have several shared mappings of the same object in user
 * space.
 */
static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
{
	register unsigned long zero = 0, one = 1, val;

	local_irq_disable();
	mb();
	*p1 = one;
	mb();
	*p2 = zero;
	mb();
	val = *p1;
	mb();
	local_irq_enable();
	return val != zero;
}

void __init check_writebuffer_bugs(void)
{
	struct page *page;
	const char *reason;
	unsigned long v = 1;

	printk(KERN_INFO "CPU: Testing write buffer coherency: ");

	page = alloc_page(GFP_KERNEL);
	if (page) {
		unsigned long *p1, *p2;
		pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
					L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);

		p1 = vmap(&page, 1, VM_IOREMAP, prot);
		p2 = vmap(&page, 1, VM_IOREMAP, prot);

		if (p1 && p2) {
			v = check_writebuffer(p1, p2);
			reason = "enabling work-around";
		} else {
			reason = "unable to map memory\n";
		}

		vunmap(p1);
		vunmap(p2);
		put_page(page);
	} else {
		reason = "unable to grab page\n";
	}

	if (v) {
		printk("failed, %s\n", reason);
		shared_pte_mask = L_PTE_MT_UNCACHED;
	} else {
		printk("ok\n");
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/fault-armv.c
	3	*
	4	* Copyright (C) 1995 Linus Torvalds
	5	* Modifications for ARM processor (c) 1995-2002 Russell King
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/module.h>
	12	#include <linux/sched.h>
	13	#include <linux/kernel.h>
	14	#include <linux/mm.h>
	15	#include <linux/bitops.h>
	16	#include <linux/vmalloc.h>
	17	#include <linux/init.h>
	18	#include <linux/pagemap.h>
5a0e3ad6	19	#include <linux/gfp.h>
1da177e4	20
09d9bae0	21	#include <asm/bugs.h>
1da177e4	22	#include <asm/cacheflush.h>
46097c7d	23	#include <asm/cachetype.h>
1da177e4 LT	24	#include <asm/pgtable.h>
	25	#include <asm/tlbflush.h>
	26
7b0a1003 RK	27	#include "mm.h"
7b0a1003 RK	28
bb30f36f	29	static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
1da177e4	30
6012191a	31	#if __LINUX_ARM_ARCH__ < 6
1da177e4 LT	32	/*
	33	* We take the easy way out of this problem - we make the
	34	* PTE uncacheable. However, we leave the write buffer on.
69b04754 HD	35	*
	36	* Note that the pte lock held when calling update_mmu_cache must also
	37	* guard the pte (somewhere else in the same mm) that we modify here.
	38	* Therefore those configurations which might call adjust_pte (those
	39	* without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
1da177e4	40	*/
c26c20b8	41	static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
ed42acae	42	unsigned long pfn, pte_t *ptep)
1da177e4	43	{
c26c20b8	44	pte_t entry = *ptep;
53cdb27a	45	int ret;
1da177e4	46
53cdb27a RK	47	/*
	48	* If this page is present, it's actually being shared.
	49	*/
	50	ret = pte_present(entry);
	51
1da177e4 LT	52	/*
	53	* If this page isn't present, or is already setup to
	54	* fault (ie, is old), we can safely ignore any issues.
	55	*/
bb30f36f	56	if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
08e445bd NP	57	flush_cache_page(vma, address, pfn);
	58	outer_flush_range((pfn << PAGE_SHIFT),
	59	(pfn << PAGE_SHIFT) + PAGE_SIZE);
bb30f36f RK	60	pte_val(entry) &= ~L_PTE_MT_MASK;
bb30f36f RK	61	pte_val(entry) \|= shared_pte_mask;
c26c20b8	62	set_pte_at(vma->vm_mm, address, ptep, entry);
1da177e4	63	flush_tlb_page(vma, address);
1da177e4	64	}
c26c20b8 RK	65
	66	return ret;
	67	}
	68
4e54d93d MW	69	#if USE_SPLIT_PTLOCKS
	70	/*
	71	* If we are using split PTE locks, then we need to take the page
	72	* lock here. Otherwise we are using shared mm->page_table_lock
	73	* which is already locked, thus cannot take it.
	74	*/
	75	static inline void do_pte_lock(spinlock_t *ptl)
	76	{
	77	/*
	78	* Use nested version here to indicate that we are already
	79	* holding one similar spinlock.
	80	*/
	81	spin_lock_nested(ptl, SINGLE_DEPTH_NESTING);
	82	}
	83
	84	static inline void do_pte_unlock(spinlock_t *ptl)
	85	{
	86	spin_unlock(ptl);
	87	}
	88	#else /* !USE_SPLIT_PTLOCKS */
	89	static inline void do_pte_lock(spinlock_t *ptl) {}
	90	static inline void do_pte_unlock(spinlock_t *ptl) {}
	91	#endif /* USE_SPLIT_PTLOCKS */
	92
ed42acae RK	93	static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
ed42acae RK	94	unsigned long pfn)
c26c20b8	95	{
56dd4709	96	spinlock_t *ptl;
c26c20b8 RK	97	pgd_t *pgd;
	98	pmd_t *pmd;
	99	pte_t *pte;
	100	int ret;
	101
	102	pgd = pgd_offset(vma->vm_mm, address);
f8a85f11 RK	103	if (pgd_none_or_clear_bad(pgd))
f8a85f11 RK	104	return 0;
c26c20b8 RK	105
c26c20b8 RK	106	pmd = pmd_offset(pgd, address);
f8a85f11 RK	107	if (pmd_none_or_clear_bad(pmd))
f8a85f11 RK	108	return 0;
c26c20b8	109
56dd4709 RK	110	/*
	111	* This is called while another page table is mapped, so we
	112	* must use the nested version. This also means we need to
	113	* open-code the spin-locking.
	114	*/
	115	ptl = pte_lockptr(vma->vm_mm, pmd);
ece0e2b6	116	pte = pte_offset_map(pmd, address);
4e54d93d	117	do_pte_lock(ptl);
c26c20b8	118
ed42acae	119	ret = do_adjust_pte(vma, address, pfn, pte);
c26c20b8	120
4e54d93d	121	do_pte_unlock(ptl);
ece0e2b6	122	pte_unmap(pte);
c26c20b8	123
1da177e4	124	return ret;
1da177e4 LT	125	}
	126
	127	static void
ae140202 RK	128	make_coherent(struct address_space mapping, struct vm_area_struct vma,
ae140202 RK	129	unsigned long addr, pte_t *ptep, unsigned long pfn)
1da177e4	130	{
1da177e4 LT	131	struct mm_struct *mm = vma->vm_mm;
	132	struct vm_area_struct *mpnt;
	133	struct prio_tree_iter iter;
	134	unsigned long offset;
	135	pgoff_t pgoff;
	136	int aliases = 0;
	137
1da177e4 LT	138	pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
	139
	140	/*
	141	* If we have any shared mappings that are in the same mm
	142	* space, then we need to handle them specially to maintain
	143	* cache coherency.
	144	*/
	145	flush_dcache_mmap_lock(mapping);
	146	vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
	147	/*
	148	* If this VMA is not in our MM, we can ignore it.
	149	* Note that we intentionally mask out the VMA
	150	* that we are fixing up.
	151	*/
	152	if (mpnt->vm_mm != mm \|\| mpnt == vma)
	153	continue;
	154	if (!(mpnt->vm_flags & VM_MAYSHARE))
	155	continue;
	156	offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
ed42acae	157	aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn);
1da177e4 LT	158	}
	159	flush_dcache_mmap_unlock(mapping);
	160	if (aliases)
ae140202	161	do_adjust_pte(vma, addr, pfn, ptep);
1da177e4 LT	162	}
	163
	164	/*
	165	* Take care of architecture specific things when placing a new PTE into
	166	* a page table, or changing an existing PTE. Basically, there are two
	167	* things that we need to take care of:
	168	*
c0177800	169	* 1. If PG_dcache_clean is not set for the page, we need to ensure
1da177e4 LT	170	* that any cache entries for the kernels virtual memory
	171	* range are written back to the page.
	172	* 2. If we have multiple shared mappings of the same space in
	173	* an object, we need to deal with the cache aliasing issues.
	174	*
69b04754	175	* Note that the pte lock will be held.
1da177e4	176	*/
4b3073e1 RK	177	void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
4b3073e1 RK	178	pte_t *ptep)
1da177e4	179	{
4b3073e1	180	unsigned long pfn = pte_pfn(*ptep);
8830f04a	181	struct address_space *mapping;
1da177e4 LT	182	struct page *page;
	183
	184	if (!pfn_valid(pfn))
	185	return;
8830f04a	186
421fe93c RK	187	/*
	188	* The zero page is never written to, so never has any dirty
	189	* cache lines, and therefore never needs to be flushed.
	190	*/
1da177e4	191	page = pfn_to_page(pfn);
421fe93c RK	192	if (page == ZERO_PAGE(0))
	193	return;
	194
8830f04a	195	mapping = page_mapping(page);
c0177800	196	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
787b2faa	197	__flush_dcache_page(mapping, page);
787b2faa	198	if (mapping) {
1da177e4	199	if (cache_is_vivt())
ae140202	200	make_coherent(mapping, vma, addr, ptep, pfn);
826cbdaf CM	201	else if (vma->vm_flags & VM_EXEC)
826cbdaf CM	202	__flush_icache_all();
1da177e4 LT	203	}
1da177e4 LT	204	}
6012191a	205	#endif /* __LINUX_ARM_ARCH__ < 6 */
1da177e4 LT	206
	207	/*
	208	* Check whether the write buffer has physical address aliasing
	209	* issues. If it has, we need to avoid them for the case where
	210	* we have several shared mappings of the same object in user
	211	* space.
	212	*/
	213	static int __init check_writebuffer(unsigned long p1, unsigned long p2)
	214	{
	215	register unsigned long zero = 0, one = 1, val;
	216
	217	local_irq_disable();
	218	mb();
	219	*p1 = one;
	220	mb();
	221	*p2 = zero;
	222	mb();
	223	val = *p1;
	224	mb();
	225	local_irq_enable();
	226	return val != zero;
	227	}
	228
	229	void __init check_writebuffer_bugs(void)
	230	{
	231	struct page *page;
	232	const char *reason;
	233	unsigned long v = 1;
	234
	235	printk(KERN_INFO "CPU: Testing write buffer coherency: ");
	236
	237	page = alloc_page(GFP_KERNEL);
	238	if (page) {
	239	unsigned long p1, p2;
52e8bfd8 RK	240	pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
52e8bfd8 RK	241	L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);
1da177e4 LT	242
	243	p1 = vmap(&page, 1, VM_IOREMAP, prot);
	244	p2 = vmap(&page, 1, VM_IOREMAP, prot);
	245
	246	if (p1 && p2) {
	247	v = check_writebuffer(p1, p2);
	248	reason = "enabling work-around";
	249	} else {
	250	reason = "unable to map memory\n";
	251	}
	252
	253	vunmap(p1);
	254	vunmap(p2);
	255	put_page(page);
	256	} else {
	257	reason = "unable to grab page\n";
	258	}
	259
	260	if (v) {
	261	printk("failed, %s\n", reason);
bb30f36f	262	shared_pte_mask = L_PTE_MT_UNCACHED;
1da177e4 LT	263	} else {
	264	printk("ok\n");
	265	}
	266	}