[net-next-2.6.git] / arch / arm / mm / cache-v7.S

/*
 *  linux/arch/arm/mm/cache-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *  Copyright (C) 2005 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>

#include "proc-macros.S"

/*
 *	v7_flush_dcache_all()
 *
 *	Flush the whole D-cache.
 *
 *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
 *
 *	- mm    - mm_struct describing address space
 */
ENTRY(v7_flush_dcache_all)
	dmb					@ ensure ordering with previous memory accesses
	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
	ands	r3, r0, #0x7000000		@ extract loc from clidr
	mov	r3, r3, lsr #23			@ left align loc bit field
	beq	finished			@ if loc is 0, then no need to clean
	mov	r10, #0				@ start clean at cache level 0
loop1:
	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
	and	r1, r1, #7			@ mask of the bits for current cache only
	cmp	r1, #2				@ see what cache we have at this level
	blt	skip				@ skip if no cache, or just i-cache
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	isb					@ isb to sych the new cssr&csidr
	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
	and	r2, r1, #7			@ extract the length of the cache lines
	add	r2, r2, #4			@ add 4 (line length offset)
	ldr	r4, =0x3ff
	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
	clz	r5, r4				@ find bit position of way size increment
	ldr	r7, =0x7fff
	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
loop2:
	mov	r9, r4				@ create working copy of max way size
loop3:
 ARM(	orr	r11, r10, r9, lsl r5	)	@ factor way and cache number into r11
 THUMB(	lsl	r6, r9, r5		)
 THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
 ARM(	orr	r11, r11, r7, lsl r2	)	@ factor index number into r11
 THUMB(	lsl	r6, r7, r2		)
 THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
	subs	r9, r9, #1			@ decrement the way
	bge	loop3
	subs	r7, r7, #1			@ decrement the index
	bge	loop2
skip:
	add	r10, r10, #2			@ increment cache number
	cmp	r3, r10
	bgt	loop1
finished:
	mov	r10, #0				@ swith back to cache level 0
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	dsb
	isb
	mov	pc, lr
ENDPROC(v7_flush_dcache_all)

/*
 *	v7_flush_cache_all()
 *
 *	Flush the entire cache system.
 *  The data cache flush is now achieved using atomic clean / invalidates
 *  working outwards from L1 cache. This is done using Set/Way based cache
 *  maintainance instructions.
 *  The instruction cache can still be invalidated back to the point of
 *  unification in a single instruction.
 *
 */
ENTRY(v7_flush_kern_cache_all)
 ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
 THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
	bl	v7_flush_dcache_all
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
 THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
	mov	pc, lr
ENDPROC(v7_flush_kern_cache_all)

/*
 *	v7_flush_cache_all()
 *
 *	Flush all TLB entries in a particular address space
 *
 *	- mm    - mm_struct describing address space
 */
ENTRY(v7_flush_user_cache_all)
	/*FALLTHROUGH*/

/*
 *	v7_flush_cache_range(start, end, flags)
 *
 *	Flush a range of TLB entries in the specified address space.
 *
 *	- start - start address (may not be aligned)
 *	- end   - end address (exclusive, may not be aligned)
 *	- flags	- vm_area_struct flags describing address space
 *
 *	It is assumed that:
 *	- we have a VIPT cache.
 */
ENTRY(v7_flush_user_cache_range)
	mov	pc, lr
ENDPROC(v7_flush_user_cache_all)
ENDPROC(v7_flush_user_cache_range)

/*
 *	v7_coherent_kern_range(start,end)
 *
 *	Ensure that the I and D caches are coherent within specified
 *	region.  This is typically used when code has been written to
 *	a memory region, and will be executed.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 *
 *	It is assumed that:
 *	- the Icache does not read data from the write buffer
 */
ENTRY(v7_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	v7_coherent_user_range(start,end)
 *
 *	Ensure that the I and D caches are coherent within specified
 *	region.  This is typically used when code has been written to
 *	a memory region, and will be executed.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 *
 *	It is assumed that:
 *	- the Icache does not read data from the write buffer
 */
ENTRY(v7_coherent_user_range)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	bic	r0, r0, r3
1:	mcr	p15, 0, r0, c7, c11, 1		@ clean D line to the point of unification
	dsb
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
	dsb
	isb
	mov	pc, lr
ENDPROC(v7_coherent_kern_range)
ENDPROC(v7_coherent_user_range)

/*
 *	v7_flush_kern_dcache_page(kaddr)
 *
 *	Ensure that the data held in the page kaddr is written back
 *	to the page in question.
 *
 *	- kaddr   - kernel address (guaranteed to be page aligned)
 */
ENTRY(v7_flush_kern_dcache_page)
	dcache_line_size r2, r3
	add	r1, r0, #PAGE_SZ
1:
	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line / unified line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_flush_kern_dcache_page)

/*
 *	v7_dma_inv_range(start,end)
 *
 *	Invalidate the data cache within the specified region; we will
 *	be performing a DMA operation in this region and we want to
 *	purge old data in the cache.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v7_dma_inv_range)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	tst	r0, r3
	bic	r0, r0, r3
	mcrne	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line

	tst	r1, r3
	bic	r1, r1, r3
	mcrne	p15, 0, r1, c7, c14, 1		@ clean & invalidate D / U line
1:
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_dma_inv_range)

/*
 *	v7_dma_clean_range(start,end)
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v7_dma_clean_range)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	bic	r0, r0, r3
1:
	mcr	p15, 0, r0, c7, c10, 1		@ clean D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_dma_clean_range)

/*
 *	v7_dma_flush_range(start,end)
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v7_dma_flush_range)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	bic	r0, r0, r3
1:
	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_dma_flush_range)

	__INITDATA

	.type	v7_cache_fns, #object
ENTRY(v7_cache_fns)
	.long	v7_flush_kern_cache_all
	.long	v7_flush_user_cache_all
	.long	v7_flush_user_cache_range
	.long	v7_coherent_kern_range
	.long	v7_coherent_user_range
	.long	v7_flush_kern_dcache_page
	.long	v7_dma_inv_range
	.long	v7_dma_clean_range
	.long	v7_dma_flush_range
	.size	v7_cache_fns, . - v7_cache_fns
Commit	Line	Data
bbe88886 CM	1	/*
	2	* linux/arch/arm/mm/cache-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	* Copyright (C) 2005 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This is the "shell" of the ARMv7 processor support.
	12	*/
	13	#include <linux/linkage.h>
	14	#include <linux/init.h>
	15	#include <asm/assembler.h>
	16
	17	#include "proc-macros.S"
	18
	19	/*
	20	* v7_flush_dcache_all()
	21	*
	22	* Flush the whole D-cache.
	23	*
347c8b70	24	* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
bbe88886 CM	25	*
	26	* - mm - mm_struct describing address space
	27	*/
	28	ENTRY(v7_flush_dcache_all)
c30c2f99	29	dmb @ ensure ordering with previous memory accesses
bbe88886 CM	30	mrc p15, 1, r0, c0, c0, 1 @ read clidr
	31	ands r3, r0, #0x7000000 @ extract loc from clidr
	32	mov r3, r3, lsr #23 @ left align loc bit field
	33	beq finished @ if loc is 0, then no need to clean
	34	mov r10, #0 @ start clean at cache level 0
	35	loop1:
	36	add r2, r10, r10, lsr #1 @ work out 3x current cache level
	37	mov r1, r0, lsr r2 @ extract cache type bits from clidr
	38	and r1, r1, #7 @ mask of the bits for current cache only
	39	cmp r1, #2 @ see what cache we have at this level
	40	blt skip @ skip if no cache, or just i-cache
	41	mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
	42	isb @ isb to sych the new cssr&csidr
	43	mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
	44	and r2, r1, #7 @ extract the length of the cache lines
	45	add r2, r2, #4 @ add 4 (line length offset)
	46	ldr r4, =0x3ff
	47	ands r4, r4, r1, lsr #3 @ find maximum number on the way size
	48	clz r5, r4 @ find bit position of way size increment
	49	ldr r7, =0x7fff
	50	ands r7, r7, r1, lsr #13 @ extract max number of the index size
	51	loop2:
	52	mov r9, r4 @ create working copy of max way size
	53	loop3:
347c8b70 CM	54	ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
	55	THUMB( lsl r6, r9, r5 )
	56	THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
	57	ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
	58	THUMB( lsl r6, r7, r2 )
	59	THUMB( orr r11, r11, r6 ) @ factor index number into r11
bbe88886 CM	60	mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
	61	subs r9, r9, #1 @ decrement the way
	62	bge loop3
	63	subs r7, r7, #1 @ decrement the index
	64	bge loop2
	65	skip:
	66	add r10, r10, #2 @ increment cache number
	67	cmp r3, r10
	68	bgt loop1
	69	finished:
	70	mov r10, #0 @ swith back to cache level 0
	71	mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
c30c2f99	72	dsb
bbe88886 CM	73	isb
bbe88886 CM	74	mov pc, lr
93ed3970	75	ENDPROC(v7_flush_dcache_all)
bbe88886 CM	76
	77	/*
	78	* v7_flush_cache_all()
	79	*
	80	* Flush the entire cache system.
	81	* The data cache flush is now achieved using atomic clean / invalidates
	82	* working outwards from L1 cache. This is done using Set/Way based cache
	83	* maintainance instructions.
	84	* The instruction cache can still be invalidated back to the point of
	85	* unification in a single instruction.
	86	*
	87	*/
	88	ENTRY(v7_flush_kern_cache_all)
347c8b70 CM	89	ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
347c8b70 CM	90	THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
bbe88886 CM	91	bl v7_flush_dcache_all
	92	mov r0, #0
	93	mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
347c8b70 CM	94	ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
347c8b70 CM	95	THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
bbe88886	96	mov pc, lr
93ed3970	97	ENDPROC(v7_flush_kern_cache_all)
bbe88886 CM	98
	99	/*
	100	* v7_flush_cache_all()
	101	*
	102	* Flush all TLB entries in a particular address space
	103	*
	104	* - mm - mm_struct describing address space
	105	*/
	106	ENTRY(v7_flush_user_cache_all)
	107	/FALLTHROUGH/
	108
	109	/*
	110	* v7_flush_cache_range(start, end, flags)
	111	*
	112	* Flush a range of TLB entries in the specified address space.
	113	*
	114	* - start - start address (may not be aligned)
	115	* - end - end address (exclusive, may not be aligned)
	116	* - flags - vm_area_struct flags describing address space
	117	*
	118	* It is assumed that:
	119	* - we have a VIPT cache.
	120	*/
	121	ENTRY(v7_flush_user_cache_range)
	122	mov pc, lr
93ed3970 CM	123	ENDPROC(v7_flush_user_cache_all)
93ed3970 CM	124	ENDPROC(v7_flush_user_cache_range)
bbe88886 CM	125
	126	/*
	127	* v7_coherent_kern_range(start,end)
	128	*
	129	* Ensure that the I and D caches are coherent within specified
	130	* region. This is typically used when code has been written to
	131	* a memory region, and will be executed.
	132	*
	133	* - start - virtual start address of region
	134	* - end - virtual end address of region
	135	*
	136	* It is assumed that:
	137	* - the Icache does not read data from the write buffer
	138	*/
	139	ENTRY(v7_coherent_kern_range)
	140	/* FALLTHROUGH */
	141
	142	/*
	143	* v7_coherent_user_range(start,end)
	144	*
	145	* Ensure that the I and D caches are coherent within specified
	146	* region. This is typically used when code has been written to
	147	* a memory region, and will be executed.
	148	*
	149	* - start - virtual start address of region
	150	* - end - virtual end address of region
	151	*
	152	* It is assumed that:
	153	* - the Icache does not read data from the write buffer
	154	*/
	155	ENTRY(v7_coherent_user_range)
	156	dcache_line_size r2, r3
	157	sub r3, r2, #1
	158	bic r0, r0, r3
	159	1: mcr p15, 0, r0, c7, c11, 1 @ clean D line to the point of unification
	160	dsb
	161	mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
	162	add r0, r0, r2
	163	cmp r0, r1
	164	blo 1b
	165	mov r0, #0
	166	mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
	167	dsb
	168	isb
	169	mov pc, lr
93ed3970 CM	170	ENDPROC(v7_coherent_kern_range)
93ed3970 CM	171	ENDPROC(v7_coherent_user_range)
bbe88886 CM	172
	173	/*
	174	* v7_flush_kern_dcache_page(kaddr)
	175	*
	176	* Ensure that the data held in the page kaddr is written back
	177	* to the page in question.
	178	*
	179	* - kaddr - kernel address (guaranteed to be page aligned)
	180	*/
	181	ENTRY(v7_flush_kern_dcache_page)
	182	dcache_line_size r2, r3
	183	add r1, r0, #PAGE_SZ
	184	1:
	185	mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
	186	add r0, r0, r2
	187	cmp r0, r1
	188	blo 1b
	189	dsb
	190	mov pc, lr
93ed3970	191	ENDPROC(v7_flush_kern_dcache_page)
bbe88886 CM	192
	193	/*
	194	* v7_dma_inv_range(start,end)
	195	*
	196	* Invalidate the data cache within the specified region; we will
	197	* be performing a DMA operation in this region and we want to
	198	* purge old data in the cache.
	199	*
	200	* - start - virtual start address of region
	201	* - end - virtual end address of region
	202	*/
	203	ENTRY(v7_dma_inv_range)
	204	dcache_line_size r2, r3
	205	sub r3, r2, #1
	206	tst r0, r3
	207	bic r0, r0, r3
	208	mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
	209
	210	tst r1, r3
	211	bic r1, r1, r3
	212	mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
	213	1:
	214	mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
	215	add r0, r0, r2
	216	cmp r0, r1
	217	blo 1b
	218	dsb
	219	mov pc, lr
93ed3970	220	ENDPROC(v7_dma_inv_range)
bbe88886 CM	221
	222	/*
	223	* v7_dma_clean_range(start,end)
	224	* - start - virtual start address of region
	225	* - end - virtual end address of region
	226	*/
	227	ENTRY(v7_dma_clean_range)
	228	dcache_line_size r2, r3
	229	sub r3, r2, #1
	230	bic r0, r0, r3
	231	1:
	232	mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
	233	add r0, r0, r2
	234	cmp r0, r1
	235	blo 1b
	236	dsb
	237	mov pc, lr
93ed3970	238	ENDPROC(v7_dma_clean_range)
bbe88886 CM	239
	240	/*
	241	* v7_dma_flush_range(start,end)
	242	* - start - virtual start address of region
	243	* - end - virtual end address of region
	244	*/
	245	ENTRY(v7_dma_flush_range)
	246	dcache_line_size r2, r3
	247	sub r3, r2, #1
	248	bic r0, r0, r3
	249	1:
	250	mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
	251	add r0, r0, r2
	252	cmp r0, r1
	253	blo 1b
	254	dsb
	255	mov pc, lr
93ed3970	256	ENDPROC(v7_dma_flush_range)
bbe88886 CM	257
	258	__INITDATA
	259
	260	.type v7_cache_fns, #object
	261	ENTRY(v7_cache_fns)
	262	.long v7_flush_kern_cache_all
	263	.long v7_flush_user_cache_all
	264	.long v7_flush_user_cache_range
	265	.long v7_coherent_kern_range
	266	.long v7_coherent_user_range
	267	.long v7_flush_kern_dcache_page
	268	.long v7_dma_inv_range
	269	.long v7_dma_clean_range
	270	.long v7_dma_flush_range
	271	.size v7_cache_fns, . - v7_cache_fns