[net-next-2.6.git] / arch / arm / mm / Kconfig

comment "Processor Type"

config CPU_32
	bool
	default y

# Select CPU types depending on the architecture selected.  This selects
# which CPUs we support in the kernel image, and the compiler instruction
# optimiser behaviour.

# ARM610
config CPU_ARM610
	bool "Support ARM610 processor"
	depends on ARCH_RPC
	select CPU_32v3
	select CPU_CACHE_V3
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V3 if MMU
	select CPU_TLB_V3 if MMU
	help
	  The ARM610 is the successor to the ARM3 processor
	  and was produced by VLSI Technology Inc.

	  Say Y if you want support for the ARM610 processor.
	  Otherwise, say N.

# ARM7TDMI
config CPU_ARM7TDMI
	bool "Support ARM7TDMI processor"
	depends on !MMU
	select CPU_32v4T
	select CPU_ABRT_LV4T
	select CPU_CACHE_V4
	help
	  A 32-bit RISC microprocessor based on the ARM7 processor core
	  which has no memory control unit and cache.

	  Say Y if you want support for the ARM7TDMI processor.
	  Otherwise, say N.

# ARM710
config CPU_ARM710
	bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
	default y if ARCH_CLPS7500
	select CPU_32v3
	select CPU_CACHE_V3
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V3 if MMU
	select CPU_TLB_V3 if MMU
	help
	  A 32-bit RISC microprocessor based on the ARM7 processor core
	  designed by Advanced RISC Machines Ltd. The ARM710 is the
	  successor to the ARM610 processor. It was released in
	  July 1994 by VLSI Technology Inc.

	  Say Y if you want support for the ARM710 processor.
	  Otherwise, say N.

# ARM720T
config CPU_ARM720T
	bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
	default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
	select CPU_32v4T
	select CPU_ABRT_LV4T
	select CPU_CACHE_V4
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WT if MMU
	select CPU_TLB_V4WT if MMU
	help
	  A 32-bit RISC processor with 8kByte Cache, Write Buffer and
	  MMU built around an ARM7TDMI core.

	  Say Y if you want support for the ARM720T processor.
	  Otherwise, say N.

# ARM740T
config CPU_ARM740T
	bool "Support ARM740T processor" if ARCH_INTEGRATOR
	depends on !MMU
	select CPU_32v4T
	select CPU_ABRT_LV4T
	select CPU_CACHE_V3	# although the core is v4t
	select CPU_CP15_MPU
	help
	  A 32-bit RISC processor with 8KB cache or 4KB variants,
	  write buffer and MPU(Protection Unit) built around
	  an ARM7TDMI core.

	  Say Y if you want support for the ARM740T processor.
	  Otherwise, say N.

# ARM9TDMI
config CPU_ARM9TDMI
	bool "Support ARM9TDMI processor"
	depends on !MMU
	select CPU_32v4T
	select CPU_ABRT_NOMMU
	select CPU_CACHE_V4
	help
	  A 32-bit RISC microprocessor based on the ARM9 processor core
	  which has no memory control unit and cache.

	  Say Y if you want support for the ARM9TDMI processor.
	  Otherwise, say N.

# ARM920T
config CPU_ARM920T
	bool "Support ARM920T processor"
	depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
	default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
	select CPU_32v4T
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WB if MMU
	select CPU_TLB_V4WBI if MMU
	help
	  The ARM920T is licensed to be produced by numerous vendors,
	  and is used in the Maverick EP9312 and the Samsung S3C2410.

	  More information on the Maverick EP9312 at
	  <http://linuxdevices.com/products/PD2382866068.html>.

	  Say Y if you want support for the ARM920T processor.
	  Otherwise, say N.

# ARM922T
config CPU_ARM922T
	bool "Support ARM922T processor" if ARCH_INTEGRATOR
	depends on ARCH_LH7A40X || ARCH_INTEGRATOR
	default y if ARCH_LH7A40X
	select CPU_32v4T
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WB if MMU
	select CPU_TLB_V4WBI if MMU
	help
	  The ARM922T is a version of the ARM920T, but with smaller
	  instruction and data caches. It is used in Altera's
	  Excalibur XA device family.

	  Say Y if you want support for the ARM922T processor.
	  Otherwise, say N.

# ARM925T
config CPU_ARM925T
 	bool "Support ARM925T processor" if ARCH_OMAP1
 	depends on ARCH_OMAP15XX
 	default y if ARCH_OMAP15XX
	select CPU_32v4T
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WB if MMU
	select CPU_TLB_V4WBI if MMU
 	help
 	  The ARM925T is a mix between the ARM920T and ARM926T, but with
	  different instruction and data caches. It is used in TI's OMAP
 	  device family.

 	  Say Y if you want support for the ARM925T processor.
 	  Otherwise, say N.

# ARM926T
config CPU_ARM926T
	bool "Support ARM926T processor"
	depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
	default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
	select CPU_32v5
	select CPU_ABRT_EV5TJ
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WB if MMU
	select CPU_TLB_V4WBI if MMU
	help
	  This is a variant of the ARM920.  It has slightly different
	  instruction sequences for cache and TLB operations.  Curiously,
	  there is no documentation on it at the ARM corporate website.

	  Say Y if you want support for the ARM926T processor.
	  Otherwise, say N.

# ARM940T
config CPU_ARM940T
	bool "Support ARM940T processor" if ARCH_INTEGRATOR
	depends on !MMU
	select CPU_32v4T
	select CPU_ABRT_NOMMU
	select CPU_CACHE_VIVT
	select CPU_CP15_MPU
	help
	  ARM940T is a member of the ARM9TDMI family of general-
	  purpose microprocessors with MPU and separate 4KB
	  instruction and 4KB data cases, each with a 4-word line
	  length.

	  Say Y if you want support for the ARM940T processor.
	  Otherwise, say N.

# ARM946E-S
config CPU_ARM946E
	bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
	depends on !MMU
	select CPU_32v5
	select CPU_ABRT_NOMMU
	select CPU_CACHE_VIVT
	select CPU_CP15_MPU
	help
	  ARM946E-S is a member of the ARM9E-S family of high-
	  performance, 32-bit system-on-chip processor solutions.
	  The TCM and ARMv5TE 32-bit instruction set is supported.

	  Say Y if you want support for the ARM946E-S processor.
	  Otherwise, say N.

# ARM1020 - needs validating
config CPU_ARM1020
	bool "Support ARM1020T (rev 0) processor"
	depends on ARCH_INTEGRATOR
	select CPU_32v5
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WB if MMU
	select CPU_TLB_V4WBI if MMU
	help
	  The ARM1020 is the 32K cached version of the ARM10 processor,
	  with an addition of a floating-point unit.

	  Say Y if you want support for the ARM1020 processor.
	  Otherwise, say N.

# ARM1020E - needs validating
config CPU_ARM1020E
	bool "Support ARM1020E processor"
	depends on ARCH_INTEGRATOR
	select CPU_32v5
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WB if MMU
	select CPU_TLB_V4WBI if MMU
	depends on n

# ARM1022E
config CPU_ARM1022
	bool "Support ARM1022E processor"
	depends on ARCH_INTEGRATOR
	select CPU_32v5
	select CPU_ABRT_EV4T
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WB if MMU # can probably do better
	select CPU_TLB_V4WBI if MMU
	help
	  The ARM1022E is an implementation of the ARMv5TE architecture
	  based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
	  embedded trace macrocell, and a floating-point unit.

	  Say Y if you want support for the ARM1022E processor.
	  Otherwise, say N.

# ARM1026EJ-S
config CPU_ARM1026
	bool "Support ARM1026EJ-S processor"
	depends on ARCH_INTEGRATOR
	select CPU_32v5
	select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WB if MMU # can probably do better
	select CPU_TLB_V4WBI if MMU
	help
	  The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
	  based upon the ARM10 integer core.

	  Say Y if you want support for the ARM1026EJ-S processor.
	  Otherwise, say N.

# SA110
config CPU_SA110
	bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
	default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
	select CPU_32v3 if ARCH_RPC
	select CPU_32v4 if !ARCH_RPC
	select CPU_ABRT_EV4
	select CPU_CACHE_V4WB
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_COPY_V4WB if MMU
	select CPU_TLB_V4WB if MMU
	help
	  The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
	  is available at five speeds ranging from 100 MHz to 233 MHz.
	  More information is available at
	  <http://developer.intel.com/design/strong/sa110.htm>.

	  Say Y if you want support for the SA-110 processor.
	  Otherwise, say N.

# SA1100
config CPU_SA1100
	bool
	depends on ARCH_SA1100
	default y
	select CPU_32v4
	select CPU_ABRT_EV4
	select CPU_CACHE_V4WB
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_TLB_V4WB if MMU

# XScale
config CPU_XSCALE
	bool
	depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
	default y
	select CPU_32v5
	select CPU_ABRT_EV5T
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_TLB_V4WBI if MMU

# XScale Core Version 3
config CPU_XSC3
	bool
	depends on ARCH_IXP23XX || ARCH_IOP13XX
	default y
	select CPU_32v5
	select CPU_ABRT_EV5T
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_TLB_V4WBI if MMU
	select IO_36

# ARMv6
config CPU_V6
	bool "Support ARM V6 processor"
	depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
	select CPU_32v6
	select CPU_ABRT_EV6
	select CPU_CACHE_V6
	select CPU_CACHE_VIPT
	select CPU_CP15_MMU
	select CPU_COPY_V6 if MMU
	select CPU_TLB_V6 if MMU

# ARMv6k
config CPU_32v6K
	bool "Support ARM V6K processor extensions" if !SMP
	depends on CPU_V6
	default y if SMP
	help
	  Say Y here if your ARMv6 processor supports the 'K' extension.
	  This enables the kernel to use some instructions not present
	  on previous processors, and as such a kernel build with this
	  enabled will not boot on processors with do not support these
	  instructions.

# ARMv7
config CPU_V7
	bool "Support ARM V7 processor"
	depends on ARCH_INTEGRATOR
	select CPU_32v6K
	select CPU_32v7
	select CPU_ABRT_EV7
	select CPU_CACHE_V7
	select CPU_CACHE_VIPT
	select CPU_CP15_MMU
	select CPU_COPY_V6 if MMU
	select CPU_TLB_V6 if MMU

# Figure out what processor architecture version we should be using.
# This defines the compiler instruction set which depends on the machine type.
config CPU_32v3
	bool
	select TLS_REG_EMUL if SMP || !MMU
	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP

config CPU_32v4
	bool
	select TLS_REG_EMUL if SMP || !MMU
	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP

config CPU_32v4T
	bool
	select TLS_REG_EMUL if SMP || !MMU
	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP

config CPU_32v5
	bool
	select TLS_REG_EMUL if SMP || !MMU
	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP

config CPU_32v6
	bool

config CPU_32v7
	bool

# The abort model
config CPU_ABRT_NOMMU
	bool

config CPU_ABRT_EV4
	bool

config CPU_ABRT_EV4T
	bool

config CPU_ABRT_LV4T
	bool

config CPU_ABRT_EV5T
	bool

config CPU_ABRT_EV5TJ
	bool

config CPU_ABRT_EV6
	bool

config CPU_ABRT_EV7
	bool

# The cache model
config CPU_CACHE_V3
	bool

config CPU_CACHE_V4
	bool

config CPU_CACHE_V4WT
	bool

config CPU_CACHE_V4WB
	bool

config CPU_CACHE_V6
	bool

config CPU_CACHE_V7
	bool

config CPU_CACHE_VIVT
	bool

config CPU_CACHE_VIPT
	bool

if MMU
# The copy-page model
config CPU_COPY_V3
	bool

config CPU_COPY_V4WT
	bool

config CPU_COPY_V4WB
	bool

config CPU_COPY_V6
	bool

# This selects the TLB model
config CPU_TLB_V3
	bool
	help
	  ARM Architecture Version 3 TLB.

config CPU_TLB_V4WT
	bool
	help
	  ARM Architecture Version 4 TLB with writethrough cache.

config CPU_TLB_V4WB
	bool
	help
	  ARM Architecture Version 4 TLB with writeback cache.

config CPU_TLB_V4WBI
	bool
	help
	  ARM Architecture Version 4 TLB with writeback cache and invalidate
	  instruction cache entry.

config CPU_TLB_V6
	bool

endif

config CPU_CP15
	bool
	help
	  Processor has the CP15 register.

config CPU_CP15_MMU
	bool
	select CPU_CP15
	help
	  Processor has the CP15 register, which has MMU related registers.

config CPU_CP15_MPU
	bool
	select CPU_CP15
	help
	  Processor has the CP15 register, which has MPU related registers.

#
# CPU supports 36-bit I/O
#
config IO_36
	bool

comment "Processor Features"

config ARM_THUMB
	bool "Support Thumb user binaries"
	depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7
	default y
	help
	  Say Y if you want to include kernel support for running user space
	  Thumb binaries.

	  The Thumb instruction set is a compressed form of the standard ARM
	  instruction set resulting in smaller binaries at the expense of
	  slightly less efficient code.

	  If you don't know what this all is, saying Y is a safe choice.

config CPU_BIG_ENDIAN
	bool "Build big-endian kernel"
	depends on ARCH_SUPPORTS_BIG_ENDIAN
	help
	  Say Y if you plan on running a kernel in big-endian mode.
	  Note that your board must be properly built and your board
	  port must properly enable any big-endian related features
	  of your chipset/board/processor.

config CPU_HIGH_VECTOR
	depends on !MMU && CPU_CP15 && !CPU_ARM740T
	bool "Select the High exception vector"
	default n
	help
	  Say Y here to select high exception vector(0xFFFF0000~).
	  The exception vector can be vary depending on the platform
	  design in nommu mode. If your platform needs to select
	  high exception vector, say Y.
	  Otherwise or if you are unsure, say N, and the low exception
	  vector (0x00000000~) will be used.

config CPU_ICACHE_DISABLE
	bool "Disable I-Cache (I-bit)"
	depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
	help
	  Say Y here to disable the processor instruction cache. Unless
	  you have a reason not to or are unsure, say N.

config CPU_DCACHE_DISABLE
	bool "Disable D-Cache (C-bit)"
	depends on CPU_CP15
	help
	  Say Y here to disable the processor data cache. Unless
	  you have a reason not to or are unsure, say N.

config CPU_DCACHE_SIZE
	hex
	depends on CPU_ARM740T || CPU_ARM946E
	default 0x00001000 if CPU_ARM740T
	default 0x00002000 # default size for ARM946E-S
	help
	  Some cores are synthesizable to have various sized cache. For
	  ARM946E-S case, it can vary from 0KB to 1MB.
	  To support such cache operations, it is efficient to know the size
	  before compile time.
	  If your SoC is configured to have a different size, define the value
	  here with proper conditions.

config CPU_DCACHE_WRITETHROUGH
	bool "Force write through D-cache"
	depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
	default y if CPU_ARM925T
	help
	  Say Y here to use the data cache in writethrough mode. Unless you
	  specifically require this or are unsure, say N.

config CPU_CACHE_ROUND_ROBIN
	bool "Round robin I and D cache replacement algorithm"
	depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
	help
	  Say Y here to use the predictable round-robin cache replacement
	  policy.  Unless you specifically require this or are unsure, say N.

config CPU_L2CACHE_DISABLE
	bool "Disable level 2 cache"
	depends on CPU_V7
	help
	  Say Y here to disable the level 2 cache.  If unsure, say N.

config CPU_BPREDICT_DISABLE
	bool "Disable branch prediction"
	depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
	help
	  Say Y here to disable branch prediction.  If unsure, say N.

config TLS_REG_EMUL
	bool
	help
	  An SMP system using a pre-ARMv6 processor (there are apparently
	  a few prototypes like that in existence) and therefore access to
	  that required register must be emulated.

config HAS_TLS_REG
	bool
	depends on !TLS_REG_EMUL
	default y if SMP || CPU_32v7
	help
	  This selects support for the CP15 thread register.
	  It is defined to be available on some ARMv6 processors (including
	  all SMP capable ARMv6's) or later processors.  User space may
	  assume directly accessing that register and always obtain the
	  expected value only on ARMv7 and above.

config NEEDS_SYSCALL_FOR_CMPXCHG
	bool
	help
	  SMP on a pre-ARMv6 processor?  Well OK then.
	  Forget about fast user space cmpxchg support.
	  It is just not possible.

config OUTER_CACHE
	bool
	default n

config CACHE_L2X0
	bool
	select OUTER_CACHE
Commit	Line	Data
1da177e4 LT	1	comment "Processor Type"
	2
	3	config CPU_32
	4	bool
	5	default y
	6
	7	# Select CPU types depending on the architecture selected. This selects
	8	# which CPUs we support in the kernel image, and the compiler instruction
	9	# optimiser behaviour.
	10
	11	# ARM610
	12	config CPU_ARM610
	13	bool "Support ARM610 processor"
	14	depends on ARCH_RPC
	15	select CPU_32v3
	16	select CPU_CACHE_V3
	17	select CPU_CACHE_VIVT
fefdaa06	18	select CPU_CP15_MMU
f9c21a6e HC	19	select CPU_COPY_V3 if MMU
f9c21a6e HC	20	select CPU_TLB_V3 if MMU
1da177e4 LT	21	help
	22	The ARM610 is the successor to the ARM3 processor
	23	and was produced by VLSI Technology Inc.
	24
	25	Say Y if you want support for the ARM610 processor.
	26	Otherwise, say N.
	27
07e0da78 HC	28	# ARM7TDMI
	29	config CPU_ARM7TDMI
	30	bool "Support ARM7TDMI processor"
6b237a35	31	depends on !MMU
07e0da78 HC	32	select CPU_32v4T
	33	select CPU_ABRT_LV4T
	34	select CPU_CACHE_V4
	35	help
	36	A 32-bit RISC microprocessor based on the ARM7 processor core
	37	which has no memory control unit and cache.
	38
	39	Say Y if you want support for the ARM7TDMI processor.
	40	Otherwise, say N.
	41
1da177e4 LT	42	# ARM710
	43	config CPU_ARM710
	44	bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
	45	default y if ARCH_CLPS7500
	46	select CPU_32v3
	47	select CPU_CACHE_V3
	48	select CPU_CACHE_VIVT
fefdaa06	49	select CPU_CP15_MMU
f9c21a6e HC	50	select CPU_COPY_V3 if MMU
f9c21a6e HC	51	select CPU_TLB_V3 if MMU
1da177e4 LT	52	help
	53	A 32-bit RISC microprocessor based on the ARM7 processor core
	54	designed by Advanced RISC Machines Ltd. The ARM710 is the
	55	successor to the ARM610 processor. It was released in
	56	July 1994 by VLSI Technology Inc.
	57
	58	Say Y if you want support for the ARM710 processor.
	59	Otherwise, say N.
	60
	61	# ARM720T
	62	config CPU_ARM720T
	63	bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
	64	default y if ARCH_CLPS711X \|\| ARCH_L7200 \|\| ARCH_CDB89712 \|\| ARCH_H720X
260e98ed	65	select CPU_32v4T
1da177e4 LT	66	select CPU_ABRT_LV4T
	67	select CPU_CACHE_V4
	68	select CPU_CACHE_VIVT
fefdaa06	69	select CPU_CP15_MMU
f9c21a6e HC	70	select CPU_COPY_V4WT if MMU
f9c21a6e HC	71	select CPU_TLB_V4WT if MMU
1da177e4 LT	72	help
	73	A 32-bit RISC processor with 8kByte Cache, Write Buffer and
	74	MMU built around an ARM7TDMI core.
	75
	76	Say Y if you want support for the ARM720T processor.
	77	Otherwise, say N.
	78
b731c311 HC	79	# ARM740T
	80	config CPU_ARM740T
	81	bool "Support ARM740T processor" if ARCH_INTEGRATOR
6b237a35	82	depends on !MMU
b731c311 HC	83	select CPU_32v4T
	84	select CPU_ABRT_LV4T
	85	select CPU_CACHE_V3 # although the core is v4t
	86	select CPU_CP15_MPU
	87	help
	88	A 32-bit RISC processor with 8KB cache or 4KB variants,
	89	write buffer and MPU(Protection Unit) built around
	90	an ARM7TDMI core.
	91
	92	Say Y if you want support for the ARM740T processor.
	93	Otherwise, say N.
	94
43f5f014 HC	95	# ARM9TDMI
	96	config CPU_ARM9TDMI
	97	bool "Support ARM9TDMI processor"
6b237a35	98	depends on !MMU
43f5f014	99	select CPU_32v4T
0f45d7f3	100	select CPU_ABRT_NOMMU
43f5f014 HC	101	select CPU_CACHE_V4
	102	help
	103	A 32-bit RISC microprocessor based on the ARM9 processor core
	104	which has no memory control unit and cache.
	105
	106	Say Y if you want support for the ARM9TDMI processor.
	107	Otherwise, say N.
	108
1da177e4 LT	109	# ARM920T
1da177e4 LT	110	config CPU_ARM920T
3434d9d9 BD	111	bool "Support ARM920T processor"
	112	depends on ARCH_EP93XX \|\| ARCH_INTEGRATOR \|\| CPU_S3C2410 \|\| CPU_S3C2440 \|\| CPU_S3C2442 \|\| ARCH_IMX \|\| ARCH_AAEC2000 \|\| ARCH_AT91RM9200
	113	default y if CPU_S3C2410 \|\| CPU_S3C2440 \|\| CPU_S3C2442 \|\| ARCH_AT91RM9200
260e98ed	114	select CPU_32v4T
1da177e4 LT	115	select CPU_ABRT_EV4T
	116	select CPU_CACHE_V4WT
	117	select CPU_CACHE_VIVT
fefdaa06	118	select CPU_CP15_MMU
f9c21a6e HC	119	select CPU_COPY_V4WB if MMU
f9c21a6e HC	120	select CPU_TLB_V4WBI if MMU
1da177e4 LT	121	help
	122	The ARM920T is licensed to be produced by numerous vendors,
	123	and is used in the Maverick EP9312 and the Samsung S3C2410.
	124
	125	More information on the Maverick EP9312 at
	126	<http://linuxdevices.com/products/PD2382866068.html>.
	127
	128	Say Y if you want support for the ARM920T processor.
	129	Otherwise, say N.
	130
	131	# ARM922T
	132	config CPU_ARM922T
	133	bool "Support ARM922T processor" if ARCH_INTEGRATOR
0fec53a2 RK	134	depends on ARCH_LH7A40X \|\| ARCH_INTEGRATOR
0fec53a2 RK	135	default y if ARCH_LH7A40X
260e98ed	136	select CPU_32v4T
1da177e4 LT	137	select CPU_ABRT_EV4T
	138	select CPU_CACHE_V4WT
	139	select CPU_CACHE_VIVT
fefdaa06	140	select CPU_CP15_MMU
f9c21a6e HC	141	select CPU_COPY_V4WB if MMU
f9c21a6e HC	142	select CPU_TLB_V4WBI if MMU
1da177e4 LT	143	help
	144	The ARM922T is a version of the ARM920T, but with smaller
	145	instruction and data caches. It is used in Altera's
	146	Excalibur XA device family.
	147
	148	Say Y if you want support for the ARM922T processor.
	149	Otherwise, say N.
	150
	151	# ARM925T
	152	config CPU_ARM925T
b288f75f	153	bool "Support ARM925T processor" if ARCH_OMAP1
3179a019 TL	154	depends on ARCH_OMAP15XX
3179a019 TL	155	default y if ARCH_OMAP15XX
260e98ed	156	select CPU_32v4T
1da177e4 LT	157	select CPU_ABRT_EV4T
	158	select CPU_CACHE_V4WT
	159	select CPU_CACHE_VIVT
fefdaa06	160	select CPU_CP15_MMU
f9c21a6e HC	161	select CPU_COPY_V4WB if MMU
f9c21a6e HC	162	select CPU_TLB_V4WBI if MMU
1da177e4 LT	163	help
	164	The ARM925T is a mix between the ARM920T and ARM926T, but with
	165	different instruction and data caches. It is used in TI's OMAP
	166	device family.
	167
	168	Say Y if you want support for the ARM925T processor.
	169	Otherwise, say N.
	170
	171	# ARM926T
	172	config CPU_ARM926T
8ad68bbf	173	bool "Support ARM926T processor"
877d7720 AV	174	depends on ARCH_INTEGRATOR \|\| ARCH_VERSATILE_PB \|\| MACH_VERSATILE_AB \|\| ARCH_OMAP730 \|\| ARCH_OMAP16XX \|\| MACH_REALVIEW_EB \|\| ARCH_PNX4008 \|\| ARCH_NETX \|\| CPU_S3C2412 \|\| ARCH_AT91SAM9260 \|\| ARCH_AT91SAM9261 \|\| ARCH_AT91SAM9263 \|\| ARCH_AT91SAM9RL \|\| ARCH_NS9XXX \|\| ARCH_DAVINCI
877d7720 AV	175	default y if ARCH_VERSATILE_PB \|\| MACH_VERSATILE_AB \|\| ARCH_OMAP730 \|\| ARCH_OMAP16XX \|\| ARCH_PNX4008 \|\| ARCH_NETX \|\| CPU_S3C2412 \|\| ARCH_AT91SAM9260 \|\| ARCH_AT91SAM9261 \|\| ARCH_AT91SAM9263 \|\| ARCH_AT91SAM9RL \|\| ARCH_NS9XXX \|\| ARCH_DAVINCI
1da177e4 LT	176	select CPU_32v5
	177	select CPU_ABRT_EV5TJ
	178	select CPU_CACHE_VIVT
fefdaa06	179	select CPU_CP15_MMU
f9c21a6e HC	180	select CPU_COPY_V4WB if MMU
f9c21a6e HC	181	select CPU_TLB_V4WBI if MMU
1da177e4 LT	182	help
	183	This is a variant of the ARM920. It has slightly different
	184	instruction sequences for cache and TLB operations. Curiously,
	185	there is no documentation on it at the ARM corporate website.
	186
	187	Say Y if you want support for the ARM926T processor.
	188	Otherwise, say N.
	189
d60674eb HC	190	# ARM940T
	191	config CPU_ARM940T
	192	bool "Support ARM940T processor" if ARCH_INTEGRATOR
6b237a35	193	depends on !MMU
d60674eb	194	select CPU_32v4T
0f45d7f3	195	select CPU_ABRT_NOMMU
d60674eb HC	196	select CPU_CACHE_VIVT
	197	select CPU_CP15_MPU
	198	help
	199	ARM940T is a member of the ARM9TDMI family of general-
3cb2fccc	200	purpose microprocessors with MPU and separate 4KB
d60674eb HC	201	instruction and 4KB data cases, each with a 4-word line
	202	length.
	203
	204	Say Y if you want support for the ARM940T processor.
	205	Otherwise, say N.
	206
f37f46eb HC	207	# ARM946E-S
	208	config CPU_ARM946E
	209	bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
6b237a35	210	depends on !MMU
f37f46eb	211	select CPU_32v5
0f45d7f3	212	select CPU_ABRT_NOMMU
f37f46eb HC	213	select CPU_CACHE_VIVT
	214	select CPU_CP15_MPU
	215	help
	216	ARM946E-S is a member of the ARM9E-S family of high-
	217	performance, 32-bit system-on-chip processor solutions.
	218	The TCM and ARMv5TE 32-bit instruction set is supported.
	219
	220	Say Y if you want support for the ARM946E-S processor.
	221	Otherwise, say N.
	222
1da177e4 LT	223	# ARM1020 - needs validating
	224	config CPU_ARM1020
	225	bool "Support ARM1020T (rev 0) processor"
	226	depends on ARCH_INTEGRATOR
	227	select CPU_32v5
	228	select CPU_ABRT_EV4T
	229	select CPU_CACHE_V4WT
	230	select CPU_CACHE_VIVT
fefdaa06	231	select CPU_CP15_MMU
f9c21a6e HC	232	select CPU_COPY_V4WB if MMU
f9c21a6e HC	233	select CPU_TLB_V4WBI if MMU
1da177e4 LT	234	help
	235	The ARM1020 is the 32K cached version of the ARM10 processor,
	236	with an addition of a floating-point unit.
	237
	238	Say Y if you want support for the ARM1020 processor.
	239	Otherwise, say N.
	240
	241	# ARM1020E - needs validating
	242	config CPU_ARM1020E
	243	bool "Support ARM1020E processor"
	244	depends on ARCH_INTEGRATOR
	245	select CPU_32v5
	246	select CPU_ABRT_EV4T
	247	select CPU_CACHE_V4WT
	248	select CPU_CACHE_VIVT
fefdaa06	249	select CPU_CP15_MMU
f9c21a6e HC	250	select CPU_COPY_V4WB if MMU
f9c21a6e HC	251	select CPU_TLB_V4WBI if MMU
1da177e4 LT	252	depends on n
	253
	254	# ARM1022E
	255	config CPU_ARM1022
	256	bool "Support ARM1022E processor"
	257	depends on ARCH_INTEGRATOR
	258	select CPU_32v5
	259	select CPU_ABRT_EV4T
	260	select CPU_CACHE_VIVT
fefdaa06	261	select CPU_CP15_MMU
f9c21a6e HC	262	select CPU_COPY_V4WB if MMU # can probably do better
f9c21a6e HC	263	select CPU_TLB_V4WBI if MMU
1da177e4 LT	264	help
	265	The ARM1022E is an implementation of the ARMv5TE architecture
	266	based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
	267	embedded trace macrocell, and a floating-point unit.
	268
	269	Say Y if you want support for the ARM1022E processor.
	270	Otherwise, say N.
	271
	272	# ARM1026EJ-S
	273	config CPU_ARM1026
	274	bool "Support ARM1026EJ-S processor"
	275	depends on ARCH_INTEGRATOR
	276	select CPU_32v5
	277	select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
	278	select CPU_CACHE_VIVT
fefdaa06	279	select CPU_CP15_MMU
f9c21a6e HC	280	select CPU_COPY_V4WB if MMU # can probably do better
f9c21a6e HC	281	select CPU_TLB_V4WBI if MMU
1da177e4 LT	282	help
	283	The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
	284	based upon the ARM10 integer core.
	285
	286	Say Y if you want support for the ARM1026EJ-S processor.
	287	Otherwise, say N.
	288
	289	# SA110
	290	config CPU_SA110
	291	bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
	292	default y if ARCH_EBSA110 \|\| FOOTBRIDGE \|\| ARCH_TBOX \|\| ARCH_SHARK \|\| ARCH_NEXUSPCI
	293	select CPU_32v3 if ARCH_RPC
	294	select CPU_32v4 if !ARCH_RPC
	295	select CPU_ABRT_EV4
	296	select CPU_CACHE_V4WB
	297	select CPU_CACHE_VIVT
fefdaa06	298	select CPU_CP15_MMU
f9c21a6e HC	299	select CPU_COPY_V4WB if MMU
f9c21a6e HC	300	select CPU_TLB_V4WB if MMU
1da177e4 LT	301	help
	302	The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
	303	is available at five speeds ranging from 100 MHz to 233 MHz.
	304	More information is available at
	305	<http://developer.intel.com/design/strong/sa110.htm>.
	306
	307	Say Y if you want support for the SA-110 processor.
	308	Otherwise, say N.
	309
	310	# SA1100
	311	config CPU_SA1100
	312	bool
	313	depends on ARCH_SA1100
	314	default y
	315	select CPU_32v4
	316	select CPU_ABRT_EV4
	317	select CPU_CACHE_V4WB
	318	select CPU_CACHE_VIVT
fefdaa06	319	select CPU_CP15_MMU
f9c21a6e	320	select CPU_TLB_V4WB if MMU
1da177e4 LT	321
	322	# XScale
	323	config CPU_XSCALE
	324	bool
3f7e5815	325	depends on ARCH_IOP32X \|\| ARCH_IOP33X \|\| ARCH_PXA \|\| ARCH_IXP4XX \|\| ARCH_IXP2000
1da177e4 LT	326	default y
	327	select CPU_32v5
	328	select CPU_ABRT_EV5T
	329	select CPU_CACHE_VIVT
fefdaa06	330	select CPU_CP15_MMU
f9c21a6e	331	select CPU_TLB_V4WBI if MMU
1da177e4	332
23bdf86a LB	333	# XScale Core Version 3
	334	config CPU_XSC3
	335	bool
285f5fa7	336	depends on ARCH_IXP23XX \|\| ARCH_IOP13XX
23bdf86a LB	337	default y
	338	select CPU_32v5
	339	select CPU_ABRT_EV5T
	340	select CPU_CACHE_VIVT
fefdaa06	341	select CPU_CP15_MMU
f9c21a6e	342	select CPU_TLB_V4WBI if MMU
23bdf86a LB	343	select IO_36
23bdf86a LB	344
1da177e4 LT	345	# ARMv6
	346	config CPU_V6
	347	bool "Support ARM V6 processor"
1dbae815	348	depends on ARCH_INTEGRATOR \|\| MACH_REALVIEW_EB \|\| ARCH_OMAP2
1da177e4 LT	349	select CPU_32v6
	350	select CPU_ABRT_EV6
	351	select CPU_CACHE_V6
	352	select CPU_CACHE_VIPT
fefdaa06	353	select CPU_CP15_MMU
f9c21a6e HC	354	select CPU_COPY_V6 if MMU
f9c21a6e HC	355	select CPU_TLB_V6 if MMU
1da177e4	356
4a5f79e7 RK	357	# ARMv6k
	358	config CPU_32v6K
	359	bool "Support ARM V6K processor extensions" if !SMP
	360	depends on CPU_V6
	361	default y if SMP
	362	help
	363	Say Y here if your ARMv6 processor supports the 'K' extension.
	364	This enables the kernel to use some instructions not present
	365	on previous processors, and as such a kernel build with this
	366	enabled will not boot on processors with do not support these
	367	instructions.
	368
23688e99 CM	369	# ARMv7
	370	config CPU_V7
	371	bool "Support ARM V7 processor"
	372	depends on ARCH_INTEGRATOR
	373	select CPU_32v6K
	374	select CPU_32v7
	375	select CPU_ABRT_EV7
	376	select CPU_CACHE_V7
	377	select CPU_CACHE_VIPT
	378	select CPU_CP15_MMU
	379	select CPU_COPY_V6 if MMU
	380	select CPU_TLB_V6 if MMU
	381
1da177e4 LT	382	# Figure out what processor architecture version we should be using.
	383	# This defines the compiler instruction set which depends on the machine type.
	384	config CPU_32v3
	385	bool
60b6cf68	386	select TLS_REG_EMUL if SMP \|\| !MMU
48fa14f7	387	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
1da177e4 LT	388
	389	config CPU_32v4
	390	bool
60b6cf68	391	select TLS_REG_EMUL if SMP \|\| !MMU
48fa14f7	392	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
1da177e4	393
260e98ed LB	394	config CPU_32v4T
	395	bool
	396	select TLS_REG_EMUL if SMP \|\| !MMU
	397	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
	398
1da177e4 LT	399	config CPU_32v5
1da177e4 LT	400	bool
60b6cf68	401	select TLS_REG_EMUL if SMP \|\| !MMU
48fa14f7	402	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
1da177e4 LT	403
	404	config CPU_32v6
	405	bool
	406
23688e99 CM	407	config CPU_32v7
	408	bool
	409
1da177e4	410	# The abort model
0f45d7f3 HC	411	config CPU_ABRT_NOMMU
	412	bool
	413
1da177e4 LT	414	config CPU_ABRT_EV4
	415	bool
	416
	417	config CPU_ABRT_EV4T
	418	bool
	419
	420	config CPU_ABRT_LV4T
	421	bool
	422
	423	config CPU_ABRT_EV5T
	424	bool
	425
	426	config CPU_ABRT_EV5TJ
	427	bool
	428
	429	config CPU_ABRT_EV6
	430	bool
	431
23688e99 CM	432	config CPU_ABRT_EV7
	433	bool
	434
1da177e4 LT	435	# The cache model
	436	config CPU_CACHE_V3
	437	bool
	438
	439	config CPU_CACHE_V4
	440	bool
	441
	442	config CPU_CACHE_V4WT
	443	bool
	444
	445	config CPU_CACHE_V4WB
	446	bool
	447
	448	config CPU_CACHE_V6
	449	bool
	450
23688e99 CM	451	config CPU_CACHE_V7
	452	bool
	453
1da177e4 LT	454	config CPU_CACHE_VIVT
	455	bool
	456
	457	config CPU_CACHE_VIPT
	458	bool
	459
f9c21a6e	460	if MMU
1da177e4 LT	461	# The copy-page model
	462	config CPU_COPY_V3
	463	bool
	464
	465	config CPU_COPY_V4WT
	466	bool
	467
	468	config CPU_COPY_V4WB
	469	bool
	470
	471	config CPU_COPY_V6
	472	bool
	473
	474	# This selects the TLB model
	475	config CPU_TLB_V3
	476	bool
	477	help
	478	ARM Architecture Version 3 TLB.
	479
	480	config CPU_TLB_V4WT
	481	bool
	482	help
	483	ARM Architecture Version 4 TLB with writethrough cache.
	484
	485	config CPU_TLB_V4WB
	486	bool
	487	help
	488	ARM Architecture Version 4 TLB with writeback cache.
	489
	490	config CPU_TLB_V4WBI
	491	bool
	492	help
	493	ARM Architecture Version 4 TLB with writeback cache and invalidate
	494	instruction cache entry.
	495
	496	config CPU_TLB_V6
	497	bool
	498
f9c21a6e HC	499	endif
f9c21a6e HC	500
fefdaa06 HC	501	config CPU_CP15
	502	bool
	503	help
	504	Processor has the CP15 register.
	505
	506	config CPU_CP15_MMU
	507	bool
	508	select CPU_CP15
	509	help
	510	Processor has the CP15 register, which has MMU related registers.
	511
	512	config CPU_CP15_MPU
	513	bool
	514	select CPU_CP15
	515	help
	516	Processor has the CP15 register, which has MPU related registers.
	517
23bdf86a LB	518	#
	519	# CPU supports 36-bit I/O
	520	#
	521	config IO_36
	522	bool
	523
1da177e4 LT	524	comment "Processor Features"
	525
	526	config ARM_THUMB
	527	bool "Support Thumb user binaries"
23688e99	528	depends on CPU_ARM720T \|\| CPU_ARM740T \|\| CPU_ARM920T \|\| CPU_ARM922T \|\| CPU_ARM925T \|\| CPU_ARM926T \|\| CPU_ARM940T \|\| CPU_ARM946E \|\| CPU_ARM1020 \|\| CPU_ARM1020E \|\| CPU_ARM1022 \|\| CPU_ARM1026 \|\| CPU_XSCALE \|\| CPU_XSC3 \|\| CPU_V6 \|\| CPU_V7
1da177e4 LT	529	default y
	530	help
	531	Say Y if you want to include kernel support for running user space
	532	Thumb binaries.
	533
	534	The Thumb instruction set is a compressed form of the standard ARM
	535	instruction set resulting in smaller binaries at the expense of
	536	slightly less efficient code.
	537
	538	If you don't know what this all is, saying Y is a safe choice.
	539
	540	config CPU_BIG_ENDIAN
	541	bool "Build big-endian kernel"
	542	depends on ARCH_SUPPORTS_BIG_ENDIAN
	543	help
	544	Say Y if you plan on running a kernel in big-endian mode.
	545	Note that your board must be properly built and your board
	546	port must properly enable any big-endian related features
	547	of your chipset/board/processor.
	548
6afd6fae	549	config CPU_HIGH_VECTOR
6340aa61	550	depends on !MMU && CPU_CP15 && !CPU_ARM740T
6afd6fae HC	551	bool "Select the High exception vector"
	552	default n
	553	help
	554	Say Y here to select high exception vector(0xFFFF0000~).
	555	The exception vector can be vary depending on the platform
	556	design in nommu mode. If your platform needs to select
	557	high exception vector, say Y.
	558	Otherwise or if you are unsure, say N, and the low exception
	559	vector (0x00000000~) will be used.
	560
1da177e4	561	config CPU_ICACHE_DISABLE
f12d0d7c HC	562	bool "Disable I-Cache (I-bit)"
f12d0d7c HC	563	depends on CPU_CP15 && !(CPU_ARM610 \|\| CPU_ARM710 \|\| CPU_ARM720T \|\| CPU_ARM740T \|\| CPU_XSCALE \|\| CPU_XSC3)
1da177e4 LT	564	help
	565	Say Y here to disable the processor instruction cache. Unless
	566	you have a reason not to or are unsure, say N.
	567
	568	config CPU_DCACHE_DISABLE
f12d0d7c HC	569	bool "Disable D-Cache (C-bit)"
f12d0d7c HC	570	depends on CPU_CP15
1da177e4 LT	571	help
	572	Say Y here to disable the processor data cache. Unless
	573	you have a reason not to or are unsure, say N.
	574
f37f46eb HC	575	config CPU_DCACHE_SIZE
	576	hex
	577	depends on CPU_ARM740T \|\| CPU_ARM946E
	578	default 0x00001000 if CPU_ARM740T
	579	default 0x00002000 # default size for ARM946E-S
	580	help
	581	Some cores are synthesizable to have various sized cache. For
	582	ARM946E-S case, it can vary from 0KB to 1MB.
	583	To support such cache operations, it is efficient to know the size
	584	before compile time.
	585	If your SoC is configured to have a different size, define the value
	586	here with proper conditions.
	587
1da177e4 LT	588	config CPU_DCACHE_WRITETHROUGH
1da177e4 LT	589	bool "Force write through D-cache"
f37f46eb	590	depends on (CPU_ARM740T \|\| CPU_ARM920T \|\| CPU_ARM922T \|\| CPU_ARM925T \|\| CPU_ARM926T \|\| CPU_ARM940T \|\| CPU_ARM946E \|\| CPU_ARM1020 \|\| CPU_V6) && !CPU_DCACHE_DISABLE
1da177e4 LT	591	default y if CPU_ARM925T
	592	help
	593	Say Y here to use the data cache in writethrough mode. Unless you
	594	specifically require this or are unsure, say N.
	595
	596	config CPU_CACHE_ROUND_ROBIN
	597	bool "Round robin I and D cache replacement algorithm"
f37f46eb	598	depends on (CPU_ARM926T \|\| CPU_ARM946E \|\| CPU_ARM1020) && (!CPU_ICACHE_DISABLE \|\| !CPU_DCACHE_DISABLE)
1da177e4 LT	599	help
	600	Say Y here to use the predictable round-robin cache replacement
	601	policy. Unless you specifically require this or are unsure, say N.
	602
23688e99 CM	603	config CPU_L2CACHE_DISABLE
	604	bool "Disable level 2 cache"
	605	depends on CPU_V7
	606	help
	607	Say Y here to disable the level 2 cache. If unsure, say N.
	608
1da177e4 LT	609	config CPU_BPREDICT_DISABLE
1da177e4 LT	610	bool "Disable branch prediction"
23688e99	611	depends on CPU_ARM1020 \|\| CPU_V6 \|\| CPU_XSC3 \|\| CPU_V7
1da177e4 LT	612	help
1da177e4 LT	613	Say Y here to disable branch prediction. If unsure, say N.
2d2669b6	614
4b0e07a5 NP	615	config TLS_REG_EMUL
4b0e07a5 NP	616	bool
4b0e07a5	617	help
70489c88 NP	618	An SMP system using a pre-ARMv6 processor (there are apparently
	619	a few prototypes like that in existence) and therefore access to
	620	that required register must be emulated.
4b0e07a5	621
2d2669b6 NP	622	config HAS_TLS_REG
2d2669b6 NP	623	bool
70489c88 NP	624	depends on !TLS_REG_EMUL
70489c88 NP	625	default y if SMP \|\| CPU_32v7
2d2669b6 NP	626	help
2d2669b6 NP	627	This selects support for the CP15 thread register.
70489c88 NP	628	It is defined to be available on some ARMv6 processors (including
	629	all SMP capable ARMv6's) or later processors. User space may
	630	assume directly accessing that register and always obtain the
	631	expected value only on ARMv7 and above.
2d2669b6	632
dcef1f63 NP	633	config NEEDS_SYSCALL_FOR_CMPXCHG
dcef1f63 NP	634	bool
dcef1f63 NP	635	help
	636	SMP on a pre-ARMv6 processor? Well OK then.
	637	Forget about fast user space cmpxchg support.
	638	It is just not possible.
	639
953233dc CM	640	config OUTER_CACHE
	641	bool
	642	default n
382266ad CM	643
	644	config CACHE_L2X0
	645	bool
	646	select OUTER_CACHE