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Commit | Line | Data |
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1da177e4 LT |
1 | comment "Processor Type" |
2 | ||
3 | config CPU_32 | |
4 | bool | |
5 | default y | |
6 | ||
7 | # Select CPU types depending on the architecture selected. This selects | |
8 | # which CPUs we support in the kernel image, and the compiler instruction | |
9 | # optimiser behaviour. | |
10 | ||
11 | # ARM610 | |
12 | config CPU_ARM610 | |
13 | bool "Support ARM610 processor" | |
14 | depends on ARCH_RPC | |
15 | select CPU_32v3 | |
16 | select CPU_CACHE_V3 | |
17 | select CPU_CACHE_VIVT | |
fefdaa06 | 18 | select CPU_CP15_MMU |
f9c21a6e HC |
19 | select CPU_COPY_V3 if MMU |
20 | select CPU_TLB_V3 if MMU | |
48d7927b | 21 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
22 | help |
23 | The ARM610 is the successor to the ARM3 processor | |
24 | and was produced by VLSI Technology Inc. | |
25 | ||
26 | Say Y if you want support for the ARM610 processor. | |
27 | Otherwise, say N. | |
28 | ||
07e0da78 HC |
29 | # ARM7TDMI |
30 | config CPU_ARM7TDMI | |
31 | bool "Support ARM7TDMI processor" | |
6b237a35 | 32 | depends on !MMU |
07e0da78 HC |
33 | select CPU_32v4T |
34 | select CPU_ABRT_LV4T | |
4a1fd556 | 35 | select CPU_PABRT_NOIFAR |
07e0da78 HC |
36 | select CPU_CACHE_V4 |
37 | help | |
38 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
39 | which has no memory control unit and cache. | |
40 | ||
41 | Say Y if you want support for the ARM7TDMI processor. | |
42 | Otherwise, say N. | |
43 | ||
1da177e4 LT |
44 | # ARM710 |
45 | config CPU_ARM710 | |
46 | bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC | |
47 | default y if ARCH_CLPS7500 | |
48 | select CPU_32v3 | |
49 | select CPU_CACHE_V3 | |
50 | select CPU_CACHE_VIVT | |
fefdaa06 | 51 | select CPU_CP15_MMU |
f9c21a6e HC |
52 | select CPU_COPY_V3 if MMU |
53 | select CPU_TLB_V3 if MMU | |
48d7927b | 54 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
55 | help |
56 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
57 | designed by Advanced RISC Machines Ltd. The ARM710 is the | |
58 | successor to the ARM610 processor. It was released in | |
59 | July 1994 by VLSI Technology Inc. | |
60 | ||
61 | Say Y if you want support for the ARM710 processor. | |
62 | Otherwise, say N. | |
63 | ||
64 | # ARM720T | |
65 | config CPU_ARM720T | |
66 | bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR | |
67 | default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X | |
260e98ed | 68 | select CPU_32v4T |
1da177e4 | 69 | select CPU_ABRT_LV4T |
48d7927b | 70 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
71 | select CPU_CACHE_V4 |
72 | select CPU_CACHE_VIVT | |
fefdaa06 | 73 | select CPU_CP15_MMU |
f9c21a6e HC |
74 | select CPU_COPY_V4WT if MMU |
75 | select CPU_TLB_V4WT if MMU | |
1da177e4 LT |
76 | help |
77 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and | |
78 | MMU built around an ARM7TDMI core. | |
79 | ||
80 | Say Y if you want support for the ARM720T processor. | |
81 | Otherwise, say N. | |
82 | ||
b731c311 HC |
83 | # ARM740T |
84 | config CPU_ARM740T | |
85 | bool "Support ARM740T processor" if ARCH_INTEGRATOR | |
6b237a35 | 86 | depends on !MMU |
b731c311 HC |
87 | select CPU_32v4T |
88 | select CPU_ABRT_LV4T | |
4a1fd556 | 89 | select CPU_PABRT_NOIFAR |
b731c311 HC |
90 | select CPU_CACHE_V3 # although the core is v4t |
91 | select CPU_CP15_MPU | |
92 | help | |
93 | A 32-bit RISC processor with 8KB cache or 4KB variants, | |
94 | write buffer and MPU(Protection Unit) built around | |
95 | an ARM7TDMI core. | |
96 | ||
97 | Say Y if you want support for the ARM740T processor. | |
98 | Otherwise, say N. | |
99 | ||
43f5f014 HC |
100 | # ARM9TDMI |
101 | config CPU_ARM9TDMI | |
102 | bool "Support ARM9TDMI processor" | |
6b237a35 | 103 | depends on !MMU |
43f5f014 | 104 | select CPU_32v4T |
0f45d7f3 | 105 | select CPU_ABRT_NOMMU |
4a1fd556 | 106 | select CPU_PABRT_NOIFAR |
43f5f014 HC |
107 | select CPU_CACHE_V4 |
108 | help | |
109 | A 32-bit RISC microprocessor based on the ARM9 processor core | |
110 | which has no memory control unit and cache. | |
111 | ||
112 | Say Y if you want support for the ARM9TDMI processor. | |
113 | Otherwise, say N. | |
114 | ||
1da177e4 LT |
115 | # ARM920T |
116 | config CPU_ARM920T | |
3434d9d9 BD |
117 | bool "Support ARM920T processor" |
118 | depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 | |
119 | default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 | |
260e98ed | 120 | select CPU_32v4T |
1da177e4 | 121 | select CPU_ABRT_EV4T |
48d7927b | 122 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
123 | select CPU_CACHE_V4WT |
124 | select CPU_CACHE_VIVT | |
fefdaa06 | 125 | select CPU_CP15_MMU |
f9c21a6e HC |
126 | select CPU_COPY_V4WB if MMU |
127 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
128 | help |
129 | The ARM920T is licensed to be produced by numerous vendors, | |
130 | and is used in the Maverick EP9312 and the Samsung S3C2410. | |
131 | ||
132 | More information on the Maverick EP9312 at | |
133 | <http://linuxdevices.com/products/PD2382866068.html>. | |
134 | ||
135 | Say Y if you want support for the ARM920T processor. | |
136 | Otherwise, say N. | |
137 | ||
138 | # ARM922T | |
139 | config CPU_ARM922T | |
140 | bool "Support ARM922T processor" if ARCH_INTEGRATOR | |
c53c9cf6 AV |
141 | depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695 |
142 | default y if ARCH_LH7A40X || ARCH_KS8695 | |
260e98ed | 143 | select CPU_32v4T |
1da177e4 | 144 | select CPU_ABRT_EV4T |
48d7927b | 145 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
146 | select CPU_CACHE_V4WT |
147 | select CPU_CACHE_VIVT | |
fefdaa06 | 148 | select CPU_CP15_MMU |
f9c21a6e HC |
149 | select CPU_COPY_V4WB if MMU |
150 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
151 | help |
152 | The ARM922T is a version of the ARM920T, but with smaller | |
153 | instruction and data caches. It is used in Altera's | |
c53c9cf6 | 154 | Excalibur XA device family and Micrel's KS8695 Centaur. |
1da177e4 LT |
155 | |
156 | Say Y if you want support for the ARM922T processor. | |
157 | Otherwise, say N. | |
158 | ||
159 | # ARM925T | |
160 | config CPU_ARM925T | |
b288f75f | 161 | bool "Support ARM925T processor" if ARCH_OMAP1 |
3179a019 TL |
162 | depends on ARCH_OMAP15XX |
163 | default y if ARCH_OMAP15XX | |
260e98ed | 164 | select CPU_32v4T |
1da177e4 | 165 | select CPU_ABRT_EV4T |
48d7927b | 166 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
167 | select CPU_CACHE_V4WT |
168 | select CPU_CACHE_VIVT | |
fefdaa06 | 169 | select CPU_CP15_MMU |
f9c21a6e HC |
170 | select CPU_COPY_V4WB if MMU |
171 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
172 | help |
173 | The ARM925T is a mix between the ARM920T and ARM926T, but with | |
174 | different instruction and data caches. It is used in TI's OMAP | |
175 | device family. | |
176 | ||
177 | Say Y if you want support for the ARM925T processor. | |
178 | Otherwise, say N. | |
179 | ||
180 | # ARM926T | |
181 | config CPU_ARM926T | |
8ad68bbf | 182 | bool "Support ARM926T processor" |
f0006314 RK |
183 | depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \ |
184 | MACH_VERSATILE_AB || ARCH_OMAP730 || \ | |
185 | ARCH_OMAP16XX || MACH_REALVIEW_EB || \ | |
186 | ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ | |
187 | ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \ | |
188 | ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \ | |
189 | ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \ | |
221d62c1 | 190 | ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2 |
f0006314 RK |
191 | default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \ |
192 | ARCH_OMAP730 || ARCH_OMAP16XX || \ | |
193 | ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ | |
194 | ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \ | |
195 | ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \ | |
196 | ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \ | |
197 | ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2 | |
1da177e4 LT |
198 | select CPU_32v5 |
199 | select CPU_ABRT_EV5TJ | |
48d7927b | 200 | select CPU_PABRT_NOIFAR |
1da177e4 | 201 | select CPU_CACHE_VIVT |
fefdaa06 | 202 | select CPU_CP15_MMU |
f9c21a6e HC |
203 | select CPU_COPY_V4WB if MMU |
204 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
205 | help |
206 | This is a variant of the ARM920. It has slightly different | |
207 | instruction sequences for cache and TLB operations. Curiously, | |
208 | there is no documentation on it at the ARM corporate website. | |
209 | ||
210 | Say Y if you want support for the ARM926T processor. | |
211 | Otherwise, say N. | |
212 | ||
d60674eb HC |
213 | # ARM940T |
214 | config CPU_ARM940T | |
215 | bool "Support ARM940T processor" if ARCH_INTEGRATOR | |
6b237a35 | 216 | depends on !MMU |
d60674eb | 217 | select CPU_32v4T |
0f45d7f3 | 218 | select CPU_ABRT_NOMMU |
4a1fd556 | 219 | select CPU_PABRT_NOIFAR |
d60674eb HC |
220 | select CPU_CACHE_VIVT |
221 | select CPU_CP15_MPU | |
222 | help | |
223 | ARM940T is a member of the ARM9TDMI family of general- | |
3cb2fccc | 224 | purpose microprocessors with MPU and separate 4KB |
d60674eb HC |
225 | instruction and 4KB data cases, each with a 4-word line |
226 | length. | |
227 | ||
228 | Say Y if you want support for the ARM940T processor. | |
229 | Otherwise, say N. | |
230 | ||
f37f46eb HC |
231 | # ARM946E-S |
232 | config CPU_ARM946E | |
233 | bool "Support ARM946E-S processor" if ARCH_INTEGRATOR | |
6b237a35 | 234 | depends on !MMU |
f37f46eb | 235 | select CPU_32v5 |
0f45d7f3 | 236 | select CPU_ABRT_NOMMU |
4a1fd556 | 237 | select CPU_PABRT_NOIFAR |
f37f46eb HC |
238 | select CPU_CACHE_VIVT |
239 | select CPU_CP15_MPU | |
240 | help | |
241 | ARM946E-S is a member of the ARM9E-S family of high- | |
242 | performance, 32-bit system-on-chip processor solutions. | |
243 | The TCM and ARMv5TE 32-bit instruction set is supported. | |
244 | ||
245 | Say Y if you want support for the ARM946E-S processor. | |
246 | Otherwise, say N. | |
247 | ||
1da177e4 LT |
248 | # ARM1020 - needs validating |
249 | config CPU_ARM1020 | |
250 | bool "Support ARM1020T (rev 0) processor" | |
251 | depends on ARCH_INTEGRATOR | |
252 | select CPU_32v5 | |
253 | select CPU_ABRT_EV4T | |
48d7927b | 254 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
255 | select CPU_CACHE_V4WT |
256 | select CPU_CACHE_VIVT | |
fefdaa06 | 257 | select CPU_CP15_MMU |
f9c21a6e HC |
258 | select CPU_COPY_V4WB if MMU |
259 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
260 | help |
261 | The ARM1020 is the 32K cached version of the ARM10 processor, | |
262 | with an addition of a floating-point unit. | |
263 | ||
264 | Say Y if you want support for the ARM1020 processor. | |
265 | Otherwise, say N. | |
266 | ||
267 | # ARM1020E - needs validating | |
268 | config CPU_ARM1020E | |
269 | bool "Support ARM1020E processor" | |
270 | depends on ARCH_INTEGRATOR | |
271 | select CPU_32v5 | |
272 | select CPU_ABRT_EV4T | |
48d7927b | 273 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
274 | select CPU_CACHE_V4WT |
275 | select CPU_CACHE_VIVT | |
fefdaa06 | 276 | select CPU_CP15_MMU |
f9c21a6e HC |
277 | select CPU_COPY_V4WB if MMU |
278 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
279 | depends on n |
280 | ||
281 | # ARM1022E | |
282 | config CPU_ARM1022 | |
283 | bool "Support ARM1022E processor" | |
284 | depends on ARCH_INTEGRATOR | |
285 | select CPU_32v5 | |
286 | select CPU_ABRT_EV4T | |
48d7927b | 287 | select CPU_PABRT_NOIFAR |
1da177e4 | 288 | select CPU_CACHE_VIVT |
fefdaa06 | 289 | select CPU_CP15_MMU |
f9c21a6e HC |
290 | select CPU_COPY_V4WB if MMU # can probably do better |
291 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
292 | help |
293 | The ARM1022E is an implementation of the ARMv5TE architecture | |
294 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, | |
295 | embedded trace macrocell, and a floating-point unit. | |
296 | ||
297 | Say Y if you want support for the ARM1022E processor. | |
298 | Otherwise, say N. | |
299 | ||
300 | # ARM1026EJ-S | |
301 | config CPU_ARM1026 | |
302 | bool "Support ARM1026EJ-S processor" | |
303 | depends on ARCH_INTEGRATOR | |
304 | select CPU_32v5 | |
305 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | |
48d7927b | 306 | select CPU_PABRT_NOIFAR |
1da177e4 | 307 | select CPU_CACHE_VIVT |
fefdaa06 | 308 | select CPU_CP15_MMU |
f9c21a6e HC |
309 | select CPU_COPY_V4WB if MMU # can probably do better |
310 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
311 | help |
312 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture | |
313 | based upon the ARM10 integer core. | |
314 | ||
315 | Say Y if you want support for the ARM1026EJ-S processor. | |
316 | Otherwise, say N. | |
317 | ||
318 | # SA110 | |
319 | config CPU_SA110 | |
320 | bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC | |
321 | default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI | |
322 | select CPU_32v3 if ARCH_RPC | |
323 | select CPU_32v4 if !ARCH_RPC | |
324 | select CPU_ABRT_EV4 | |
48d7927b | 325 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
326 | select CPU_CACHE_V4WB |
327 | select CPU_CACHE_VIVT | |
fefdaa06 | 328 | select CPU_CP15_MMU |
f9c21a6e HC |
329 | select CPU_COPY_V4WB if MMU |
330 | select CPU_TLB_V4WB if MMU | |
1da177e4 LT |
331 | help |
332 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and | |
333 | is available at five speeds ranging from 100 MHz to 233 MHz. | |
334 | More information is available at | |
335 | <http://developer.intel.com/design/strong/sa110.htm>. | |
336 | ||
337 | Say Y if you want support for the SA-110 processor. | |
338 | Otherwise, say N. | |
339 | ||
340 | # SA1100 | |
341 | config CPU_SA1100 | |
342 | bool | |
343 | depends on ARCH_SA1100 | |
344 | default y | |
345 | select CPU_32v4 | |
346 | select CPU_ABRT_EV4 | |
48d7927b | 347 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
348 | select CPU_CACHE_V4WB |
349 | select CPU_CACHE_VIVT | |
fefdaa06 | 350 | select CPU_CP15_MMU |
f9c21a6e | 351 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
352 | |
353 | # XScale | |
354 | config CPU_XSCALE | |
355 | bool | |
fa0b6251 | 356 | depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000 |
1da177e4 LT |
357 | default y |
358 | select CPU_32v5 | |
359 | select CPU_ABRT_EV5T | |
48d7927b | 360 | select CPU_PABRT_NOIFAR |
1da177e4 | 361 | select CPU_CACHE_VIVT |
fefdaa06 | 362 | select CPU_CP15_MMU |
f9c21a6e | 363 | select CPU_TLB_V4WBI if MMU |
1da177e4 | 364 | |
23bdf86a LB |
365 | # XScale Core Version 3 |
366 | config CPU_XSC3 | |
367 | bool | |
2c8086a5 | 368 | depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx |
23bdf86a LB |
369 | default y |
370 | select CPU_32v5 | |
371 | select CPU_ABRT_EV5T | |
4a1fd556 | 372 | select CPU_PABRT_NOIFAR |
23bdf86a | 373 | select CPU_CACHE_VIVT |
fefdaa06 | 374 | select CPU_CP15_MMU |
f9c21a6e | 375 | select CPU_TLB_V4WBI if MMU |
23bdf86a LB |
376 | select IO_36 |
377 | ||
e50d6409 AH |
378 | # Feroceon |
379 | config CPU_FEROCEON | |
380 | bool | |
794d15b2 | 381 | depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0 |
e50d6409 AH |
382 | default y |
383 | select CPU_32v5 | |
384 | select CPU_ABRT_EV5T | |
48d7927b | 385 | select CPU_PABRT_NOIFAR |
e50d6409 AH |
386 | select CPU_CACHE_VIVT |
387 | select CPU_CP15_MMU | |
0ed15071 | 388 | select CPU_COPY_FEROCEON if MMU |
99c6dc11 | 389 | select CPU_TLB_FEROCEON if MMU |
e50d6409 | 390 | |
d910a0aa TP |
391 | config CPU_FEROCEON_OLD_ID |
392 | bool "Accept early Feroceon cores with an ARM926 ID" | |
393 | depends on CPU_FEROCEON && !CPU_ARM926T | |
394 | default y | |
395 | help | |
396 | This enables the usage of some old Feroceon cores | |
397 | for which the CPU ID is equal to the ARM926 ID. | |
398 | Relevant for Feroceon-1850 and early Feroceon-2850. | |
399 | ||
1da177e4 LT |
400 | # ARMv6 |
401 | config CPU_V6 | |
402 | bool "Support ARM V6 processor" | |
bc02c58b | 403 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 |
52c543f9 | 404 | default y if ARCH_MX3 |
3042102a | 405 | default y if ARCH_MSM7X00A |
1da177e4 LT |
406 | select CPU_32v6 |
407 | select CPU_ABRT_EV6 | |
48d7927b | 408 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
409 | select CPU_CACHE_V6 |
410 | select CPU_CACHE_VIPT | |
fefdaa06 | 411 | select CPU_CP15_MMU |
7b4c965a | 412 | select CPU_HAS_ASID if MMU |
f9c21a6e HC |
413 | select CPU_COPY_V6 if MMU |
414 | select CPU_TLB_V6 if MMU | |
1da177e4 | 415 | |
4a5f79e7 RK |
416 | # ARMv6k |
417 | config CPU_32v6K | |
418 | bool "Support ARM V6K processor extensions" if !SMP | |
419 | depends on CPU_V6 | |
52c543f9 | 420 | default y if SMP && !ARCH_MX3 |
4a5f79e7 RK |
421 | help |
422 | Say Y here if your ARMv6 processor supports the 'K' extension. | |
423 | This enables the kernel to use some instructions not present | |
424 | on previous processors, and as such a kernel build with this | |
425 | enabled will not boot on processors with do not support these | |
426 | instructions. | |
427 | ||
23688e99 CM |
428 | # ARMv7 |
429 | config CPU_V7 | |
430 | bool "Support ARM V7 processor" | |
41267e20 | 431 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB |
23688e99 CM |
432 | select CPU_32v6K |
433 | select CPU_32v7 | |
434 | select CPU_ABRT_EV7 | |
48d7927b | 435 | select CPU_PABRT_IFAR |
23688e99 CM |
436 | select CPU_CACHE_V7 |
437 | select CPU_CACHE_VIPT | |
438 | select CPU_CP15_MMU | |
2eb8c82b | 439 | select CPU_HAS_ASID if MMU |
23688e99 | 440 | select CPU_COPY_V6 if MMU |
2ccdd1e7 | 441 | select CPU_TLB_V7 if MMU |
23688e99 | 442 | |
1da177e4 LT |
443 | # Figure out what processor architecture version we should be using. |
444 | # This defines the compiler instruction set which depends on the machine type. | |
445 | config CPU_32v3 | |
446 | bool | |
60b6cf68 | 447 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 448 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
1da177e4 LT |
449 | |
450 | config CPU_32v4 | |
451 | bool | |
60b6cf68 | 452 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 453 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
1da177e4 | 454 | |
260e98ed LB |
455 | config CPU_32v4T |
456 | bool | |
457 | select TLS_REG_EMUL if SMP || !MMU | |
458 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | |
459 | ||
1da177e4 LT |
460 | config CPU_32v5 |
461 | bool | |
60b6cf68 | 462 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 463 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
1da177e4 LT |
464 | |
465 | config CPU_32v6 | |
466 | bool | |
367afaf8 | 467 | select TLS_REG_EMUL if !CPU_32v6K && !MMU |
1da177e4 | 468 | |
23688e99 CM |
469 | config CPU_32v7 |
470 | bool | |
471 | ||
1da177e4 | 472 | # The abort model |
0f45d7f3 HC |
473 | config CPU_ABRT_NOMMU |
474 | bool | |
475 | ||
1da177e4 LT |
476 | config CPU_ABRT_EV4 |
477 | bool | |
478 | ||
479 | config CPU_ABRT_EV4T | |
480 | bool | |
481 | ||
482 | config CPU_ABRT_LV4T | |
483 | bool | |
484 | ||
485 | config CPU_ABRT_EV5T | |
486 | bool | |
487 | ||
488 | config CPU_ABRT_EV5TJ | |
489 | bool | |
490 | ||
491 | config CPU_ABRT_EV6 | |
492 | bool | |
493 | ||
23688e99 CM |
494 | config CPU_ABRT_EV7 |
495 | bool | |
496 | ||
48d7927b PB |
497 | config CPU_PABRT_IFAR |
498 | bool | |
499 | ||
500 | config CPU_PABRT_NOIFAR | |
501 | bool | |
502 | ||
1da177e4 LT |
503 | # The cache model |
504 | config CPU_CACHE_V3 | |
505 | bool | |
506 | ||
507 | config CPU_CACHE_V4 | |
508 | bool | |
509 | ||
510 | config CPU_CACHE_V4WT | |
511 | bool | |
512 | ||
513 | config CPU_CACHE_V4WB | |
514 | bool | |
515 | ||
516 | config CPU_CACHE_V6 | |
517 | bool | |
518 | ||
23688e99 CM |
519 | config CPU_CACHE_V7 |
520 | bool | |
521 | ||
1da177e4 LT |
522 | config CPU_CACHE_VIVT |
523 | bool | |
524 | ||
525 | config CPU_CACHE_VIPT | |
526 | bool | |
527 | ||
f9c21a6e | 528 | if MMU |
1da177e4 LT |
529 | # The copy-page model |
530 | config CPU_COPY_V3 | |
531 | bool | |
532 | ||
533 | config CPU_COPY_V4WT | |
534 | bool | |
535 | ||
536 | config CPU_COPY_V4WB | |
537 | bool | |
538 | ||
0ed15071 LB |
539 | config CPU_COPY_FEROCEON |
540 | bool | |
541 | ||
1da177e4 LT |
542 | config CPU_COPY_V6 |
543 | bool | |
544 | ||
545 | # This selects the TLB model | |
546 | config CPU_TLB_V3 | |
547 | bool | |
548 | help | |
549 | ARM Architecture Version 3 TLB. | |
550 | ||
551 | config CPU_TLB_V4WT | |
552 | bool | |
553 | help | |
554 | ARM Architecture Version 4 TLB with writethrough cache. | |
555 | ||
556 | config CPU_TLB_V4WB | |
557 | bool | |
558 | help | |
559 | ARM Architecture Version 4 TLB with writeback cache. | |
560 | ||
561 | config CPU_TLB_V4WBI | |
562 | bool | |
563 | help | |
564 | ARM Architecture Version 4 TLB with writeback cache and invalidate | |
565 | instruction cache entry. | |
566 | ||
99c6dc11 LB |
567 | config CPU_TLB_FEROCEON |
568 | bool | |
569 | help | |
570 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). | |
571 | ||
1da177e4 LT |
572 | config CPU_TLB_V6 |
573 | bool | |
574 | ||
2ccdd1e7 CM |
575 | config CPU_TLB_V7 |
576 | bool | |
577 | ||
f9c21a6e HC |
578 | endif |
579 | ||
516793c6 RK |
580 | config CPU_HAS_ASID |
581 | bool | |
582 | help | |
583 | This indicates whether the CPU has the ASID register; used to | |
584 | tag TLB and possibly cache entries. | |
585 | ||
fefdaa06 HC |
586 | config CPU_CP15 |
587 | bool | |
588 | help | |
589 | Processor has the CP15 register. | |
590 | ||
591 | config CPU_CP15_MMU | |
592 | bool | |
593 | select CPU_CP15 | |
594 | help | |
595 | Processor has the CP15 register, which has MMU related registers. | |
596 | ||
597 | config CPU_CP15_MPU | |
598 | bool | |
599 | select CPU_CP15 | |
600 | help | |
601 | Processor has the CP15 register, which has MPU related registers. | |
602 | ||
23bdf86a LB |
603 | # |
604 | # CPU supports 36-bit I/O | |
605 | # | |
606 | config IO_36 | |
607 | bool | |
608 | ||
1da177e4 LT |
609 | comment "Processor Features" |
610 | ||
611 | config ARM_THUMB | |
612 | bool "Support Thumb user binaries" | |
e50d6409 | 613 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
614 | default y |
615 | help | |
616 | Say Y if you want to include kernel support for running user space | |
617 | Thumb binaries. | |
618 | ||
619 | The Thumb instruction set is a compressed form of the standard ARM | |
620 | instruction set resulting in smaller binaries at the expense of | |
621 | slightly less efficient code. | |
622 | ||
623 | If you don't know what this all is, saying Y is a safe choice. | |
624 | ||
d7f864be CM |
625 | config ARM_THUMBEE |
626 | bool "Enable ThumbEE CPU extension" | |
627 | depends on CPU_V7 | |
628 | help | |
629 | Say Y here if you have a CPU with the ThumbEE extension and code to | |
630 | make use of it. Say N for code that can run on CPUs without ThumbEE. | |
631 | ||
1da177e4 LT |
632 | config CPU_BIG_ENDIAN |
633 | bool "Build big-endian kernel" | |
634 | depends on ARCH_SUPPORTS_BIG_ENDIAN | |
635 | help | |
636 | Say Y if you plan on running a kernel in big-endian mode. | |
637 | Note that your board must be properly built and your board | |
638 | port must properly enable any big-endian related features | |
639 | of your chipset/board/processor. | |
640 | ||
6afd6fae | 641 | config CPU_HIGH_VECTOR |
6340aa61 | 642 | depends on !MMU && CPU_CP15 && !CPU_ARM740T |
6afd6fae HC |
643 | bool "Select the High exception vector" |
644 | default n | |
645 | help | |
646 | Say Y here to select high exception vector(0xFFFF0000~). | |
647 | The exception vector can be vary depending on the platform | |
648 | design in nommu mode. If your platform needs to select | |
649 | high exception vector, say Y. | |
650 | Otherwise or if you are unsure, say N, and the low exception | |
651 | vector (0x00000000~) will be used. | |
652 | ||
1da177e4 | 653 | config CPU_ICACHE_DISABLE |
f12d0d7c HC |
654 | bool "Disable I-Cache (I-bit)" |
655 | depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) | |
1da177e4 LT |
656 | help |
657 | Say Y here to disable the processor instruction cache. Unless | |
658 | you have a reason not to or are unsure, say N. | |
659 | ||
660 | config CPU_DCACHE_DISABLE | |
f12d0d7c HC |
661 | bool "Disable D-Cache (C-bit)" |
662 | depends on CPU_CP15 | |
1da177e4 LT |
663 | help |
664 | Say Y here to disable the processor data cache. Unless | |
665 | you have a reason not to or are unsure, say N. | |
666 | ||
f37f46eb HC |
667 | config CPU_DCACHE_SIZE |
668 | hex | |
669 | depends on CPU_ARM740T || CPU_ARM946E | |
670 | default 0x00001000 if CPU_ARM740T | |
671 | default 0x00002000 # default size for ARM946E-S | |
672 | help | |
673 | Some cores are synthesizable to have various sized cache. For | |
674 | ARM946E-S case, it can vary from 0KB to 1MB. | |
675 | To support such cache operations, it is efficient to know the size | |
676 | before compile time. | |
677 | If your SoC is configured to have a different size, define the value | |
678 | here with proper conditions. | |
679 | ||
1da177e4 LT |
680 | config CPU_DCACHE_WRITETHROUGH |
681 | bool "Force write through D-cache" | |
a7039bd6 | 682 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE |
1da177e4 LT |
683 | default y if CPU_ARM925T |
684 | help | |
685 | Say Y here to use the data cache in writethrough mode. Unless you | |
686 | specifically require this or are unsure, say N. | |
687 | ||
688 | config CPU_CACHE_ROUND_ROBIN | |
689 | bool "Round robin I and D cache replacement algorithm" | |
f37f46eb | 690 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) |
1da177e4 LT |
691 | help |
692 | Say Y here to use the predictable round-robin cache replacement | |
693 | policy. Unless you specifically require this or are unsure, say N. | |
694 | ||
695 | config CPU_BPREDICT_DISABLE | |
696 | bool "Disable branch prediction" | |
23688e99 | 697 | depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 |
1da177e4 LT |
698 | help |
699 | Say Y here to disable branch prediction. If unsure, say N. | |
2d2669b6 | 700 | |
4b0e07a5 NP |
701 | config TLS_REG_EMUL |
702 | bool | |
4b0e07a5 | 703 | help |
70489c88 NP |
704 | An SMP system using a pre-ARMv6 processor (there are apparently |
705 | a few prototypes like that in existence) and therefore access to | |
706 | that required register must be emulated. | |
4b0e07a5 | 707 | |
2d2669b6 NP |
708 | config HAS_TLS_REG |
709 | bool | |
70489c88 NP |
710 | depends on !TLS_REG_EMUL |
711 | default y if SMP || CPU_32v7 | |
2d2669b6 NP |
712 | help |
713 | This selects support for the CP15 thread register. | |
70489c88 NP |
714 | It is defined to be available on some ARMv6 processors (including |
715 | all SMP capable ARMv6's) or later processors. User space may | |
716 | assume directly accessing that register and always obtain the | |
717 | expected value only on ARMv7 and above. | |
2d2669b6 | 718 | |
dcef1f63 NP |
719 | config NEEDS_SYSCALL_FOR_CMPXCHG |
720 | bool | |
dcef1f63 NP |
721 | help |
722 | SMP on a pre-ARMv6 processor? Well OK then. | |
723 | Forget about fast user space cmpxchg support. | |
724 | It is just not possible. | |
725 | ||
953233dc CM |
726 | config OUTER_CACHE |
727 | bool | |
728 | default n | |
382266ad | 729 | |
99c6dc11 LB |
730 | config CACHE_FEROCEON_L2 |
731 | bool "Enable the Feroceon L2 cache controller" | |
794d15b2 | 732 | depends on ARCH_KIRKWOOD || ARCH_MV78XX0 |
99c6dc11 LB |
733 | default y |
734 | select OUTER_CACHE | |
735 | help | |
736 | This option enables the Feroceon L2 cache controller. | |
737 | ||
382266ad | 738 | config CACHE_L2X0 |
ba927951 CM |
739 | bool "Enable the L2x0 outer cache controller" |
740 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 | |
741 | default y | |
382266ad | 742 | select OUTER_CACHE |
ba927951 CM |
743 | help |
744 | This option enables the L2x0 PrimeCell. | |
905a09d5 EM |
745 | |
746 | config CACHE_XSC3L2 | |
747 | bool "Enable the L2 cache on XScale3" | |
748 | depends on CPU_XSC3 | |
749 | default y | |
750 | select OUTER_CACHE | |
751 | help | |
752 | This option enables the L2 cache on XScale3. |