[net-next-2.6.git] / arch / arm / mach-u300 / include / mach / u300-regs.h

/*
 *
 * arch/arm/mach-u300/include/mach/u300-regs.h
 *
 *
 * Copyright (C) 2006-2009 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * Basic register address definitions in physical memory and
 * some block definitions for core devices like the timer.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
 */

#ifndef __MACH_U300_REGS_H
#define __MACH_U300_REGS_H

/*
 * These are the large blocks of memory allocated for I/O.
 * the defines are used for setting up the I/O memory mapping.
 */

/* NAND Flash CS0 */
#define U300_NAND_CS0_PHYS_BASE		0x80000000

/* NFIF */
#define U300_NAND_IF_PHYS_BASE		0x9f800000

/* AHB Peripherals */
#define U300_AHB_PER_PHYS_BASE		0xa0000000
#define U300_AHB_PER_VIRT_BASE		0xff010000

/* FAST Peripherals */
#define U300_FAST_PER_PHYS_BASE		0xc0000000
#define U300_FAST_PER_VIRT_BASE		0xff020000

/* SLOW Peripherals */
#define U300_SLOW_PER_PHYS_BASE		0xc0010000
#define U300_SLOW_PER_VIRT_BASE		0xff000000

/* Boot ROM */
#define U300_BOOTROM_PHYS_BASE		0xffff0000
#define U300_BOOTROM_VIRT_BASE		0xffff0000

/* SEMI config base */
#ifdef CONFIG_MACH_U300_BS335
#define U300_SEMI_CONFIG_BASE		0x2FFE0000
#else
#define U300_SEMI_CONFIG_BASE		0x30000000
#endif

/*
 * All the following peripherals are specified at their PHYSICAL address,
 * so if you need to access them (in the kernel), you MUST use the macros
 * defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST()
 * etc.
 */

/*
 * AHB peripherals
 */

/* AHB Peripherals Bridge Controller */
#define U300_AHB_BRIDGE_BASE		(U300_AHB_PER_PHYS_BASE+0x0000)

/* Vectored Interrupt Controller 0, servicing 32 interrupts */
#define U300_INTCON0_BASE		(U300_AHB_PER_PHYS_BASE+0x1000)
#define U300_INTCON0_VBASE		(U300_AHB_PER_VIRT_BASE+0x1000)

/* Vectored Interrupt Controller 1, servicing 32 interrupts */
#define U300_INTCON1_BASE		(U300_AHB_PER_PHYS_BASE+0x2000)
#define U300_INTCON1_VBASE		(U300_AHB_PER_VIRT_BASE+0x2000)

/* Memory Stick Pro (MSPRO) controller */
#define U300_MSPRO_BASE			(U300_AHB_PER_PHYS_BASE+0x3000)

/* EMIF Configuration Area */
#define U300_EMIF_CFG_BASE		(U300_AHB_PER_PHYS_BASE+0x4000)


/*
 * FAST peripherals
 */

/* FAST bridge control */
#define U300_FAST_BRIDGE_BASE		(U300_FAST_PER_PHYS_BASE+0x0000)

/* MMC/SD controller */
#define U300_MMCSD_BASE			(U300_FAST_PER_PHYS_BASE+0x1000)

/* PCM I2S0 controller */
#define U300_PCM_I2S0_BASE		(U300_FAST_PER_PHYS_BASE+0x2000)

/* PCM I2S1 controller */
#define U300_PCM_I2S1_BASE		(U300_FAST_PER_PHYS_BASE+0x3000)

/* I2C0 controller */
#define U300_I2C0_BASE			(U300_FAST_PER_PHYS_BASE+0x4000)

/* I2C1 controller */
#define U300_I2C1_BASE			(U300_FAST_PER_PHYS_BASE+0x5000)

/* SPI controller */
#define U300_SPI_BASE			(U300_FAST_PER_PHYS_BASE+0x6000)

#ifdef CONFIG_MACH_U300_BS335
/* Fast UART1 on U335 only */
#define U300_UART1_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)
#endif

/*
 * SLOW peripherals
 */

/* SLOW bridge control */
#define U300_SLOW_BRIDGE_BASE		(U300_SLOW_PER_PHYS_BASE)

/* SYSCON */
#define U300_SYSCON_BASE		(U300_SLOW_PER_PHYS_BASE+0x1000)
#define U300_SYSCON_VBASE		(U300_SLOW_PER_VIRT_BASE+0x1000)

/* Watchdog */
#define U300_WDOG_BASE			(U300_SLOW_PER_PHYS_BASE+0x2000)

/* UART0 */
#define U300_UART0_BASE			(U300_SLOW_PER_PHYS_BASE+0x3000)

/* APP side special timer */
#define U300_TIMER_APP_BASE		(U300_SLOW_PER_PHYS_BASE+0x4000)
#define U300_TIMER_APP_VBASE		(U300_SLOW_PER_VIRT_BASE+0x4000)

/* Keypad */
#define U300_KEYPAD_BASE		(U300_SLOW_PER_PHYS_BASE+0x5000)

/* GPIO */
#define U300_GPIO_BASE			(U300_SLOW_PER_PHYS_BASE+0x6000)

/* RTC */
#define U300_RTC_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)

/* Bus tracer */
#define U300_BUSTR_BASE			(U300_SLOW_PER_PHYS_BASE+0x8000)

/* Event handler (hardware queue) */
#define U300_EVHIST_BASE		(U300_SLOW_PER_PHYS_BASE+0x9000)

/* Genric Timer */
#define U300_TIMER_BASE			(U300_SLOW_PER_PHYS_BASE+0xa000)

/* PPM */
#define U300_PPM_BASE			(U300_SLOW_PER_PHYS_BASE+0xb000)


/*
 * REST peripherals
 */

/* ISP (image signal processor) is only available in U335 */
#ifdef CONFIG_MACH_U300_BS335
#define U300_ISP_BASE			(0xA0008000)
#endif

/* DMA Controller base */
#define U300_DMAC_BASE			(0xC0020000)

/* MSL Base */
#define U300_MSL_BASE			(0xc0022000)

/* APEX Base */
#define U300_APEX_BASE			(0xc0030000)

/* Video Encoder Base */
#ifdef CONFIG_MACH_U300_BS335
#define U300_VIDEOENC_BASE		(0xc0080000)
#else
#define U300_VIDEOENC_BASE		(0xc0040000)
#endif

/* XGAM Base */
#define U300_XGAM_BASE			(0xd0000000)

/*
 * Virtual accessor macros for static devices
 */


#endif
Commit	Line	Data
fa59440d LW	1	/*
	2	*
	3	* arch/arm/mach-u300/include/mach/u300-regs.h
	4	*
	5	*
	6	* Copyright (C) 2006-2009 ST-Ericsson AB
	7	* License terms: GNU General Public License (GPL) version 2
	8	* Basic register address definitions in physical memory and
6070d81e	9	* some block definitions for core devices like the timer.
fa59440d LW	10	* Author: Linus Walleij <linus.walleij@stericsson.com>
	11	*/
	12
	13	#ifndef __MACH_U300_REGS_H
	14	#define __MACH_U300_REGS_H
	15
	16	/*
	17	* These are the large blocks of memory allocated for I/O.
	18	* the defines are used for setting up the I/O memory mapping.
	19	*/
	20
	21	/* NAND Flash CS0 */
	22	#define U300_NAND_CS0_PHYS_BASE 0x80000000
fa59440d LW	23
	24	/* NFIF */
	25	#define U300_NAND_IF_PHYS_BASE 0x9f800000
fa59440d LW	26
	27	/* AHB Peripherals */
	28	#define U300_AHB_PER_PHYS_BASE 0xa0000000
	29	#define U300_AHB_PER_VIRT_BASE 0xff010000
	30
	31	/* FAST Peripherals */
	32	#define U300_FAST_PER_PHYS_BASE 0xc0000000
	33	#define U300_FAST_PER_VIRT_BASE 0xff020000
	34
	35	/* SLOW Peripherals */
	36	#define U300_SLOW_PER_PHYS_BASE 0xc0010000
	37	#define U300_SLOW_PER_VIRT_BASE 0xff000000
	38
	39	/* Boot ROM */
	40	#define U300_BOOTROM_PHYS_BASE 0xffff0000
	41	#define U300_BOOTROM_VIRT_BASE 0xffff0000
	42
	43	/* SEMI config base */
	44	#ifdef CONFIG_MACH_U300_BS335
	45	#define U300_SEMI_CONFIG_BASE 0x2FFE0000
	46	#else
	47	#define U300_SEMI_CONFIG_BASE 0x30000000
	48	#endif
	49
	50	/*
	51	* All the following peripherals are specified at their PHYSICAL address,
	52	* so if you need to access them (in the kernel), you MUST use the macros
	53	* defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST()
	54	* etc.
	55	*/
	56
	57	/*
	58	* AHB peripherals
	59	*/
	60
	61	/* AHB Peripherals Bridge Controller */
	62	#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
	63
	64	/* Vectored Interrupt Controller 0, servicing 32 interrupts */
	65	#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
	66	#define U300_INTCON0_VBASE (U300_AHB_PER_VIRT_BASE+0x1000)
	67
	68	/* Vectored Interrupt Controller 1, servicing 32 interrupts */
	69	#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
	70	#define U300_INTCON1_VBASE (U300_AHB_PER_VIRT_BASE+0x2000)
	71
	72	/* Memory Stick Pro (MSPRO) controller */
	73	#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
	74
	75	/* EMIF Configuration Area */
	76	#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
	77
	78
	79	/*
	80	* FAST peripherals
	81	*/
	82
	83	/* FAST bridge control */
	84	#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
	85
	86	/* MMC/SD controller */
	87	#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
	88
	89	/* PCM I2S0 controller */
90	#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
91
92	/* PCM I2S1 controller */
93	#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
94
95	/* I2C0 controller */
96	#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
97
98	/* I2C1 controller */
99	#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
100
101	/* SPI controller */
102	#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
103
104	#ifdef CONFIG_MACH_U300_BS335
105	/* Fast UART1 on U335 only */
106	#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
107	#endif
108
109	/*
110	* SLOW peripherals
111	*/
112
113	/* SLOW bridge control */
114	#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
115
116	/* SYSCON */
117	#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
118	#define U300_SYSCON_VBASE (U300_SLOW_PER_VIRT_BASE+0x1000)
119
120	/* Watchdog */
121	#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
122
123	/* UART0 */
124	#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
125
126	/* APP side special timer */
127	#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
128	#define U300_TIMER_APP_VBASE (U300_SLOW_PER_VIRT_BASE+0x4000)
129
130	/* Keypad */
131	#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
132
133	/* GPIO */
134	#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
135
136	/* RTC */
137	#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
138
139	/* Bus tracer */
140	#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
141
142	/* Event handler (hardware queue) */
143	#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
144
145	/* Genric Timer */
146	#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
147
148	/* PPM */
149	#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
150
151
152	/*
153	* REST peripherals
154	*/
155
156	/* ISP (image signal processor) is only available in U335 */
157	#ifdef CONFIG_MACH_U300_BS335
158	#define U300_ISP_BASE (0xA0008000)
159	#endif
160
161	/* DMA Controller base */
162	#define U300_DMAC_BASE (0xC0020000)
163
164	/* MSL Base */
165	#define U300_MSL_BASE (0xc0022000)
166
167	/* APEX Base */
168	#define U300_APEX_BASE (0xc0030000)
169
170	/* Video Encoder Base */
171	#ifdef CONFIG_MACH_U300_BS335
172	#define U300_VIDEOENC_BASE (0xc0080000)
173	#else
174	#define U300_VIDEOENC_BASE (0xc0040000)
175	#endif
176
177	/* XGAM Base */
178	#define U300_XGAM_BASE (0xd0000000)
179
180	/*
181	* Virtual accessor macros for static devices
182	*/
183
184
185	#endif