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ARM: 5852/1: Add COH 901 318 DMA driver platform config for U300
[net-next-2.6.git] / arch / arm / mach-u300 / core.c
CommitLineData
bb3cee2b
LW		 1/*
2 *
3 * arch/arm/mach-u300/core.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/bitops.h>
16#include <linux/device.h>
17#include <linux/mm.h>
18#include <linux/termios.h>
19#include <linux/amba/bus.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
08d1e2e6 22#include <mach/coh901318.h>
bb3cee2b
LW		 23
24#include <asm/types.h>
25#include <asm/setup.h>
26#include <asm/memory.h>
27#include <asm/hardware/vic.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <mach/hardware.h>
32#include <mach/syscon.h>
08d1e2e6 33#include <mach/dma_channels.h>
bb3cee2b
LW		 34
35#include "clock.h"
36#include "mmc.h"
c7c8c78f 37#include "spi.h"
6be2a0ca 38#include "i2c.h"
bb3cee2b
LW		 39
40/*
41 * Static I/O mappings that are needed for booting the U300 platforms. The
42 * only things we need are the areas where we find the timer, syscon and
43 * intcon, since the remaining device drivers will map their own memory
44 * physical to virtual as the need arise.
45 */
46static struct map_desc u300_io_desc[] __initdata = {
47 {
48 .virtual = U300_SLOW_PER_VIRT_BASE,
49 .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
50 .length = SZ_64K,
51 .type = MT_DEVICE,
52 },
53 {
54 .virtual = U300_AHB_PER_VIRT_BASE,
55 .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
56 .length = SZ_32K,
57 .type = MT_DEVICE,
58 },
59 {
60 .virtual = U300_FAST_PER_VIRT_BASE,
61 .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
62 .length = SZ_32K,
63 .type = MT_DEVICE,
64 },
65 {
66 .virtual = 0xffff2000, /* TCM memory */
67 .pfn = __phys_to_pfn(0xffff2000),
68 .length = SZ_16K,
69 .type = MT_DEVICE,
70 },
71
72 /*
73 * This overlaps with the IRQ vectors etc at 0xffff0000, so these
74 * may have to be moved to 0x00000000 in order to use the ROM.
75 */
76 /*
77 {
78 .virtual = U300_BOOTROM_VIRT_BASE,
79 .pfn = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
80 .length = SZ_64K,
81 .type = MT_ROM,
82 },
83 */
84};
85
86void __init u300_map_io(void)
87{
88 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
89}
90
91/*
92 * Declaration of devices found on the U300 board and
93 * their respective memory locations.
94 */
95static struct amba_device uart0_device = {
96 .dev = {
97 .init_name = "uart0", /* Slow device at 0x3000 offset */
98 .platform_data = NULL,
99 },
100 .res = {
101 .start = U300_UART0_BASE,
102 .end = U300_UART0_BASE + SZ_4K - 1,
103 .flags = IORESOURCE_MEM,
104 },
105 .irq = { IRQ_U300_UART0, NO_IRQ },
106};
107
108/* The U335 have an additional UART1 on the APP CPU */
109#ifdef CONFIG_MACH_U300_BS335
110static struct amba_device uart1_device = {
111 .dev = {
112 .init_name = "uart1", /* Fast device at 0x7000 offset */
113 .platform_data = NULL,
114 },
115 .res = {
116 .start = U300_UART1_BASE,
117 .end = U300_UART1_BASE + SZ_4K - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 .irq = { IRQ_U300_UART1, NO_IRQ },
121};
122#endif
123
124static struct amba_device pl172_device = {
125 .dev = {
126 .init_name = "pl172", /* AHB device at 0x4000 offset */
127 .platform_data = NULL,
128 },
129 .res = {
130 .start = U300_EMIF_CFG_BASE,
131 .end = U300_EMIF_CFG_BASE + SZ_4K - 1,
132 .flags = IORESOURCE_MEM,
133 },
134};
135
136
137/*
138 * Everything within this next ifdef deals with external devices connected to
139 * the APP SPI bus.
140 */
141static struct amba_device pl022_device = {
142 .dev = {
143 .coherent_dma_mask = ~0,
144 .init_name = "pl022", /* Fast device at 0x6000 offset */
145 },
146 .res = {
147 .start = U300_SPI_BASE,
148 .end = U300_SPI_BASE + SZ_4K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 .irq = {IRQ_U300_SPI, NO_IRQ },
152 /*
153 * This device has a DMA channel but the Linux driver does not use
154 * it currently.
155 */
156};
157
158static struct amba_device mmcsd_device = {
159 .dev = {
160 .init_name = "mmci", /* Fast device at 0x1000 offset */
161 .platform_data = NULL, /* Added later */
162 },
163 .res = {
164 .start = U300_MMCSD_BASE,
165 .end = U300_MMCSD_BASE + SZ_4K - 1,
166 .flags = IORESOURCE_MEM,
167 },
168 .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
169 /*
170 * This device has a DMA channel but the Linux driver does not use
171 * it currently.
172 */
173};
174
175/*
176 * The order of device declaration may be important, since some devices
177 * have dependencies on other devices being initialized first.
178 */
179static struct amba_device *amba_devs[] __initdata = {
180 &uart0_device,
181#ifdef CONFIG_MACH_U300_BS335
182 &uart1_device,
183#endif
184 &pl022_device,
185 &pl172_device,
186 &mmcsd_device,
187};
188
189/* Here follows a list of all hw resources that the platform devices
190 * allocate. Note, clock dependencies are not included
191 */
192
193static struct resource gpio_resources[] = {
194 {
195 .start = U300_GPIO_BASE,
196 .end = (U300_GPIO_BASE + SZ_4K - 1),
197 .flags = IORESOURCE_MEM,
198 },
199 {
200 .name = "gpio0",
201 .start = IRQ_U300_GPIO_PORT0,
202 .end = IRQ_U300_GPIO_PORT0,
203 .flags = IORESOURCE_IRQ,
204 },
205 {
206 .name = "gpio1",
207 .start = IRQ_U300_GPIO_PORT1,
208 .end = IRQ_U300_GPIO_PORT1,
209 .flags = IORESOURCE_IRQ,
210 },
211 {
212 .name = "gpio2",
213 .start = IRQ_U300_GPIO_PORT2,
214 .end = IRQ_U300_GPIO_PORT2,
215 .flags = IORESOURCE_IRQ,
216 },
217#ifdef U300_COH901571_3
218 {
219 .name = "gpio3",
220 .start = IRQ_U300_GPIO_PORT3,
221 .end = IRQ_U300_GPIO_PORT3,
222 .flags = IORESOURCE_IRQ,
223 },
224 {
225 .name = "gpio4",
226 .start = IRQ_U300_GPIO_PORT4,
227 .end = IRQ_U300_GPIO_PORT4,
228 .flags = IORESOURCE_IRQ,
229 },
230#ifdef CONFIG_MACH_U300_BS335
231 {
232 .name = "gpio5",
233 .start = IRQ_U300_GPIO_PORT5,
234 .end = IRQ_U300_GPIO_PORT5,
235 .flags = IORESOURCE_IRQ,
236 },
237 {
238 .name = "gpio6",
239 .start = IRQ_U300_GPIO_PORT6,
240 .end = IRQ_U300_GPIO_PORT6,
241 .flags = IORESOURCE_IRQ,
242 },
243#endif /* CONFIG_MACH_U300_BS335 */
244#endif /* U300_COH901571_3 */
245};
246
247static struct resource keypad_resources[] = {
248 {
249 .start = U300_KEYPAD_BASE,
250 .end = U300_KEYPAD_BASE + SZ_4K - 1,
251 .flags = IORESOURCE_MEM,
252 },
253 {
254 .name = "coh901461-press",
255 .start = IRQ_U300_KEYPAD_KEYBF,
256 .end = IRQ_U300_KEYPAD_KEYBF,
257 .flags = IORESOURCE_IRQ,
258 },
259 {
260 .name = "coh901461-release",
261 .start = IRQ_U300_KEYPAD_KEYBR,
262 .end = IRQ_U300_KEYPAD_KEYBR,
263 .flags = IORESOURCE_IRQ,
264 },
265};
266
267static struct resource rtc_resources[] = {
268 {
269 .start = U300_RTC_BASE,
270 .end = U300_RTC_BASE + SZ_4K - 1,
271 .flags = IORESOURCE_MEM,
272 },
273 {
274 .start = IRQ_U300_RTC,
275 .end = IRQ_U300_RTC,
276 .flags = IORESOURCE_IRQ,
277 },
278};
279
280/*
281 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
282 * but these are not yet used by the driver.
283 */
284static struct resource fsmc_resources[] = {
285 {
286 .start = U300_NAND_IF_PHYS_BASE,
287 .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
288 .flags = IORESOURCE_MEM,
289 },
290};
291
292static struct resource i2c0_resources[] = {
293 {
294 .start = U300_I2C0_BASE,
295 .end = U300_I2C0_BASE + SZ_4K - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .start = IRQ_U300_I2C0,
300 .end = IRQ_U300_I2C0,
301 .flags = IORESOURCE_IRQ,
302 },
303};
304
305static struct resource i2c1_resources[] = {
306 {
307 .start = U300_I2C1_BASE,
308 .end = U300_I2C1_BASE + SZ_4K - 1,
309 .flags = IORESOURCE_MEM,
310 },
311 {
312 .start = IRQ_U300_I2C1,
313 .end = IRQ_U300_I2C1,
314 .flags = IORESOURCE_IRQ,
315 },
316
317};
318
319static struct resource wdog_resources[] = {
320 {
321 .start = U300_WDOG_BASE,
322 .end = U300_WDOG_BASE + SZ_4K - 1,
323 .flags = IORESOURCE_MEM,
324 },
325 {
326 .start = IRQ_U300_WDOG,
327 .end = IRQ_U300_WDOG,
328 .flags = IORESOURCE_IRQ,
329 }
330};
331
332/* TODO: These should be protected by suitable #ifdef's */
333static struct resource ave_resources[] = {
334 {
335 .name = "AVE3e I/O Area",
336 .start = U300_VIDEOENC_BASE,
337 .end = U300_VIDEOENC_BASE + SZ_512K - 1,
338 .flags = IORESOURCE_MEM,
339 },
340 {
341 .name = "AVE3e IRQ0",
342 .start = IRQ_U300_VIDEO_ENC_0,
343 .end = IRQ_U300_VIDEO_ENC_0,
344 .flags = IORESOURCE_IRQ,
345 },
346 {
347 .name = "AVE3e IRQ1",
348 .start = IRQ_U300_VIDEO_ENC_1,
349 .end = IRQ_U300_VIDEO_ENC_1,
350 .flags = IORESOURCE_IRQ,
351 },
352 {
353 .name = "AVE3e Physmem Area",
354 .start = 0, /* 0 will be remapped to reserved memory */
355 .end = SZ_1M - 1,
356 .flags = IORESOURCE_MEM,
357 },
358 /*
359 * The AVE3e requires two regions of 256MB that it considers
360 * "invisible". The hardware will not be able to access these
361 * adresses, so they should never point to system RAM.
362 */
363 {
364 .name = "AVE3e Reserved 0",
365 .start = 0xd0000000,
366 .end = 0xd0000000 + SZ_256M - 1,
367 .flags = IORESOURCE_MEM,
368 },
369 {
370 .name = "AVE3e Reserved 1",
371 .start = 0xe0000000,
372 .end = 0xe0000000 + SZ_256M - 1,
373 .flags = IORESOURCE_MEM,
374 },
375};
376
08d1e2e6
LW		 377static struct resource dma_resource[] = {
378 {
379 .start = U300_DMAC_BASE,
380 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
381 .flags = IORESOURCE_MEM,
382 },
383 {
384 .start = IRQ_U300_DMA,
385 .end = IRQ_U300_DMA,
386 .flags = IORESOURCE_IRQ,
387 }
388};
389
390#ifdef CONFIG_MACH_U300_BS335
391/* points out all dma slave channels.
392 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
393 * Select all channels from A to B, end of list is marked with -1,-1
394 */
395static int dma_slave_channels[] = {
396 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
397 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
398
399/* points out all dma memcpy channels. */
400static int dma_memcpy_channels[] = {
401 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
402
403#else /* CONFIG_MACH_U300_BS335 */
404
405static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
406static int dma_memcpy_channels[] = {
407 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
408
409#endif
410
411/** register dma for memory access
412 *
413 * active 1 means dma intends to access memory
414 * 0 means dma wont access memory
415 */
416static void coh901318_access_memory_state(struct device *dev, bool active)
417{
418}
419
420#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
421 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
422 COH901318_CX_CFG_LCR_DISABLE | \
423 COH901318_CX_CFG_TC_IRQ_ENABLE | \
424 COH901318_CX_CFG_BE_IRQ_ENABLE)
425#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
426 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
427 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
428 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
429 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
430 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
431 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
432 COH901318_CX_CTRL_TCP_DISABLE | \
433 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
434 COH901318_CX_CTRL_HSP_DISABLE | \
435 COH901318_CX_CTRL_HSS_DISABLE | \
436 COH901318_CX_CTRL_DDMA_LEGACY | \
437 COH901318_CX_CTRL_PRDD_SOURCE)
438#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
439 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
440 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
441 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
442 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
443 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
444 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
445 COH901318_CX_CTRL_TCP_DISABLE | \
446 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
447 COH901318_CX_CTRL_HSP_DISABLE | \
448 COH901318_CX_CTRL_HSS_DISABLE | \
449 COH901318_CX_CTRL_DDMA_LEGACY | \
450 COH901318_CX_CTRL_PRDD_SOURCE)
451#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
452 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
453 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
454 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
455 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
456 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
457 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
458 COH901318_CX_CTRL_TCP_DISABLE | \
459 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
460 COH901318_CX_CTRL_HSP_DISABLE | \
461 COH901318_CX_CTRL_HSS_DISABLE | \
462 COH901318_CX_CTRL_DDMA_LEGACY | \
463 COH901318_CX_CTRL_PRDD_SOURCE)
464
465const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
466 {
467 .number = U300_DMA_MSL_TX_0,
468 .name = "MSL TX 0",
469 .priority_high = 0,
470 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
471 },
472 {
473 .number = U300_DMA_MSL_TX_1,
474 .name = "MSL TX 1",
475 .priority_high = 0,
476 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
477 .param.config = COH901318_CX_CFG_CH_DISABLE |
478 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
479 COH901318_CX_CFG_LCR_DISABLE |
480 COH901318_CX_CFG_TC_IRQ_ENABLE |
481 COH901318_CX_CFG_BE_IRQ_ENABLE,
482 .param.ctrl_lli_chained = 0 |
483 COH901318_CX_CTRL_TC_ENABLE |
484 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
485 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
486 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
487 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
488 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
489 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
490 COH901318_CX_CTRL_TCP_DISABLE |
491 COH901318_CX_CTRL_TC_IRQ_DISABLE |
492 COH901318_CX_CTRL_HSP_ENABLE |
493 COH901318_CX_CTRL_HSS_DISABLE |
494 COH901318_CX_CTRL_DDMA_LEGACY |
495 COH901318_CX_CTRL_PRDD_SOURCE,
496 .param.ctrl_lli = 0 |
497 COH901318_CX_CTRL_TC_ENABLE |
498 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
499 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
500 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
501 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
502 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
503 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
504 COH901318_CX_CTRL_TCP_ENABLE |
505 COH901318_CX_CTRL_TC_IRQ_DISABLE |
506 COH901318_CX_CTRL_HSP_ENABLE |
507 COH901318_CX_CTRL_HSS_DISABLE |
508 COH901318_CX_CTRL_DDMA_LEGACY |
509 COH901318_CX_CTRL_PRDD_SOURCE,
510 .param.ctrl_lli_last = 0 |
511 COH901318_CX_CTRL_TC_ENABLE |
512 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
513 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
514 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
515 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
516 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
517 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
518 COH901318_CX_CTRL_TCP_ENABLE |
519 COH901318_CX_CTRL_TC_IRQ_ENABLE |
520 COH901318_CX_CTRL_HSP_ENABLE |
521 COH901318_CX_CTRL_HSS_DISABLE |
522 COH901318_CX_CTRL_DDMA_LEGACY |
523 COH901318_CX_CTRL_PRDD_SOURCE,
524 },
525 {
526 .number = U300_DMA_MSL_TX_2,
527 .name = "MSL TX 2",
528 .priority_high = 0,
529 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
530 .param.config = COH901318_CX_CFG_CH_DISABLE |
531 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
532 COH901318_CX_CFG_LCR_DISABLE |
533 COH901318_CX_CFG_TC_IRQ_ENABLE |
534 COH901318_CX_CFG_BE_IRQ_ENABLE,
535 .param.ctrl_lli_chained = 0 |
536 COH901318_CX_CTRL_TC_ENABLE |
537 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
538 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
539 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
540 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
541 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
542 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
543 COH901318_CX_CTRL_TCP_DISABLE |
544 COH901318_CX_CTRL_TC_IRQ_DISABLE |
545 COH901318_CX_CTRL_HSP_ENABLE |
546 COH901318_CX_CTRL_HSS_DISABLE |
547 COH901318_CX_CTRL_DDMA_LEGACY |
548 COH901318_CX_CTRL_PRDD_SOURCE,
549 .param.ctrl_lli = 0 |
550 COH901318_CX_CTRL_TC_ENABLE |
551 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
552 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
553 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
554 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
555 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
556 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
557 COH901318_CX_CTRL_TCP_ENABLE |
558 COH901318_CX_CTRL_TC_IRQ_DISABLE |
559 COH901318_CX_CTRL_HSP_ENABLE |
560 COH901318_CX_CTRL_HSS_DISABLE |
561 COH901318_CX_CTRL_DDMA_LEGACY |
562 COH901318_CX_CTRL_PRDD_SOURCE,
563 .param.ctrl_lli_last = 0 |
564 COH901318_CX_CTRL_TC_ENABLE |
565 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
566 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
567 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
568 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
569 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
570 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
571 COH901318_CX_CTRL_TCP_ENABLE |
572 COH901318_CX_CTRL_TC_IRQ_ENABLE |
573 COH901318_CX_CTRL_HSP_ENABLE |
574 COH901318_CX_CTRL_HSS_DISABLE |
575 COH901318_CX_CTRL_DDMA_LEGACY |
576 COH901318_CX_CTRL_PRDD_SOURCE,
577 .desc_nbr_max = 10,
578 },
579 {
580 .number = U300_DMA_MSL_TX_3,
581 .name = "MSL TX 3",
582 .priority_high = 0,
583 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
584 .param.config = COH901318_CX_CFG_CH_DISABLE |
585 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
586 COH901318_CX_CFG_LCR_DISABLE |
587 COH901318_CX_CFG_TC_IRQ_ENABLE |
588 COH901318_CX_CFG_BE_IRQ_ENABLE,
589 .param.ctrl_lli_chained = 0 |
590 COH901318_CX_CTRL_TC_ENABLE |
591 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
592 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
593 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
594 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
595 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
596 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
597 COH901318_CX_CTRL_TCP_DISABLE |
598 COH901318_CX_CTRL_TC_IRQ_DISABLE |
599 COH901318_CX_CTRL_HSP_ENABLE |
600 COH901318_CX_CTRL_HSS_DISABLE |
601 COH901318_CX_CTRL_DDMA_LEGACY |
602 COH901318_CX_CTRL_PRDD_SOURCE,
603 .param.ctrl_lli = 0 |
604 COH901318_CX_CTRL_TC_ENABLE |
605 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
606 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
607 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
608 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
609 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
610 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
611 COH901318_CX_CTRL_TCP_ENABLE |
612 COH901318_CX_CTRL_TC_IRQ_DISABLE |
613 COH901318_CX_CTRL_HSP_ENABLE |
614 COH901318_CX_CTRL_HSS_DISABLE |
615 COH901318_CX_CTRL_DDMA_LEGACY |
616 COH901318_CX_CTRL_PRDD_SOURCE,
617 .param.ctrl_lli_last = 0 |
618 COH901318_CX_CTRL_TC_ENABLE |
619 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
620 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
621 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
622 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
623 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
624 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
625 COH901318_CX_CTRL_TCP_ENABLE |
626 COH901318_CX_CTRL_TC_IRQ_ENABLE |
627 COH901318_CX_CTRL_HSP_ENABLE |
628 COH901318_CX_CTRL_HSS_DISABLE |
629 COH901318_CX_CTRL_DDMA_LEGACY |
630 COH901318_CX_CTRL_PRDD_SOURCE,
631 },
632 {
633 .number = U300_DMA_MSL_TX_4,
634 .name = "MSL TX 4",
635 .priority_high = 0,
636 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
637 .param.config = COH901318_CX_CFG_CH_DISABLE |
638 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
639 COH901318_CX_CFG_LCR_DISABLE |
640 COH901318_CX_CFG_TC_IRQ_ENABLE |
641 COH901318_CX_CFG_BE_IRQ_ENABLE,
642 .param.ctrl_lli_chained = 0 |
643 COH901318_CX_CTRL_TC_ENABLE |
644 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
645 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
646 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
647 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
648 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
649 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
650 COH901318_CX_CTRL_TCP_DISABLE |
651 COH901318_CX_CTRL_TC_IRQ_DISABLE |
652 COH901318_CX_CTRL_HSP_ENABLE |
653 COH901318_CX_CTRL_HSS_DISABLE |
654 COH901318_CX_CTRL_DDMA_LEGACY |
655 COH901318_CX_CTRL_PRDD_SOURCE,
656 .param.ctrl_lli = 0 |
657 COH901318_CX_CTRL_TC_ENABLE |
658 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
659 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
660 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
661 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
662 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
663 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
664 COH901318_CX_CTRL_TCP_ENABLE |
665 COH901318_CX_CTRL_TC_IRQ_DISABLE |
666 COH901318_CX_CTRL_HSP_ENABLE |
667 COH901318_CX_CTRL_HSS_DISABLE |
668 COH901318_CX_CTRL_DDMA_LEGACY |
669 COH901318_CX_CTRL_PRDD_SOURCE,
670 .param.ctrl_lli_last = 0 |
671 COH901318_CX_CTRL_TC_ENABLE |
672 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
673 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
674 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
675 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
676 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
677 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
678 COH901318_CX_CTRL_TCP_ENABLE |
679 COH901318_CX_CTRL_TC_IRQ_ENABLE |
680 COH901318_CX_CTRL_HSP_ENABLE |
681 COH901318_CX_CTRL_HSS_DISABLE |
682 COH901318_CX_CTRL_DDMA_LEGACY |
683 COH901318_CX_CTRL_PRDD_SOURCE,
684 },
685 {
686 .number = U300_DMA_MSL_TX_5,
687 .name = "MSL TX 5",
688 .priority_high = 0,
689 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
690 },
691 {
692 .number = U300_DMA_MSL_TX_6,
693 .name = "MSL TX 6",
694 .priority_high = 0,
695 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
696 },
697 {
698 .number = U300_DMA_MSL_RX_0,
699 .name = "MSL RX 0",
700 .priority_high = 0,
701 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
702 },
703 {
704 .number = U300_DMA_MSL_RX_1,
705 .name = "MSL RX 1",
706 .priority_high = 0,
707 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
708 .param.config = COH901318_CX_CFG_CH_DISABLE |
709 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
710 COH901318_CX_CFG_LCR_DISABLE |
711 COH901318_CX_CFG_TC_IRQ_ENABLE |
712 COH901318_CX_CFG_BE_IRQ_ENABLE,
713 .param.ctrl_lli_chained = 0 |
714 COH901318_CX_CTRL_TC_ENABLE |
715 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
716 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
717 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
718 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
719 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
720 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
721 COH901318_CX_CTRL_TCP_DISABLE |
722 COH901318_CX_CTRL_TC_IRQ_DISABLE |
723 COH901318_CX_CTRL_HSP_ENABLE |
724 COH901318_CX_CTRL_HSS_DISABLE |
725 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
726 COH901318_CX_CTRL_PRDD_DEST,
727 .param.ctrl_lli = 0,
728 .param.ctrl_lli_last = 0 |
729 COH901318_CX_CTRL_TC_ENABLE |
730 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
731 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
732 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
733 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
734 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
735 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
736 COH901318_CX_CTRL_TCP_DISABLE |
737 COH901318_CX_CTRL_TC_IRQ_ENABLE |
738 COH901318_CX_CTRL_HSP_ENABLE |
739 COH901318_CX_CTRL_HSS_DISABLE |
740 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
741 COH901318_CX_CTRL_PRDD_DEST,
742 },
743 {
744 .number = U300_DMA_MSL_RX_2,
745 .name = "MSL RX 2",
746 .priority_high = 0,
747 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
748 .param.config = COH901318_CX_CFG_CH_DISABLE |
749 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
750 COH901318_CX_CFG_LCR_DISABLE |
751 COH901318_CX_CFG_TC_IRQ_ENABLE |
752 COH901318_CX_CFG_BE_IRQ_ENABLE,
753 .param.ctrl_lli_chained = 0 |
754 COH901318_CX_CTRL_TC_ENABLE |
755 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
756 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
757 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
758 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
759 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
760 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
761 COH901318_CX_CTRL_TCP_DISABLE |
762 COH901318_CX_CTRL_TC_IRQ_DISABLE |
763 COH901318_CX_CTRL_HSP_ENABLE |
764 COH901318_CX_CTRL_HSS_DISABLE |
765 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
766 COH901318_CX_CTRL_PRDD_DEST,
767 .param.ctrl_lli = 0 |
768 COH901318_CX_CTRL_TC_ENABLE |
769 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
770 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
771 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
772 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
773 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
774 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
775 COH901318_CX_CTRL_TCP_DISABLE |
776 COH901318_CX_CTRL_TC_IRQ_ENABLE |
777 COH901318_CX_CTRL_HSP_ENABLE |
778 COH901318_CX_CTRL_HSS_DISABLE |
779 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
780 COH901318_CX_CTRL_PRDD_DEST,
781 .param.ctrl_lli_last = 0 |
782 COH901318_CX_CTRL_TC_ENABLE |
783 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
784 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
785 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
786 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
787 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
788 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
789 COH901318_CX_CTRL_TCP_DISABLE |
790 COH901318_CX_CTRL_TC_IRQ_ENABLE |
791 COH901318_CX_CTRL_HSP_ENABLE |
792 COH901318_CX_CTRL_HSS_DISABLE |
793 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
794 COH901318_CX_CTRL_PRDD_DEST,
795 },
796 {
797 .number = U300_DMA_MSL_RX_3,
798 .name = "MSL RX 3",
799 .priority_high = 0,
800 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
801 .param.config = COH901318_CX_CFG_CH_DISABLE |
802 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
803 COH901318_CX_CFG_LCR_DISABLE |
804 COH901318_CX_CFG_TC_IRQ_ENABLE |
805 COH901318_CX_CFG_BE_IRQ_ENABLE,
806 .param.ctrl_lli_chained = 0 |
807 COH901318_CX_CTRL_TC_ENABLE |
808 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
809 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
810 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
811 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
812 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
813 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
814 COH901318_CX_CTRL_TCP_DISABLE |
815 COH901318_CX_CTRL_TC_IRQ_DISABLE |
816 COH901318_CX_CTRL_HSP_ENABLE |
817 COH901318_CX_CTRL_HSS_DISABLE |
818 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
819 COH901318_CX_CTRL_PRDD_DEST,
820 .param.ctrl_lli = 0 |
821 COH901318_CX_CTRL_TC_ENABLE |
822 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
823 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
824 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
825 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
826 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
827 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
828 COH901318_CX_CTRL_TCP_DISABLE |
829 COH901318_CX_CTRL_TC_IRQ_ENABLE |
830 COH901318_CX_CTRL_HSP_ENABLE |
831 COH901318_CX_CTRL_HSS_DISABLE |
832 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
833 COH901318_CX_CTRL_PRDD_DEST,
834 .param.ctrl_lli_last = 0 |
835 COH901318_CX_CTRL_TC_ENABLE |
836 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
837 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
838 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
839 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
840 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
841 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
842 COH901318_CX_CTRL_TCP_DISABLE |
843 COH901318_CX_CTRL_TC_IRQ_ENABLE |
844 COH901318_CX_CTRL_HSP_ENABLE |
845 COH901318_CX_CTRL_HSS_DISABLE |
846 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
847 COH901318_CX_CTRL_PRDD_DEST,
848 },
849 {
850 .number = U300_DMA_MSL_RX_4,
851 .name = "MSL RX 4",
852 .priority_high = 0,
853 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
854 .param.config = COH901318_CX_CFG_CH_DISABLE |
855 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
856 COH901318_CX_CFG_LCR_DISABLE |
857 COH901318_CX_CFG_TC_IRQ_ENABLE |
858 COH901318_CX_CFG_BE_IRQ_ENABLE,
859 .param.ctrl_lli_chained = 0 |
860 COH901318_CX_CTRL_TC_ENABLE |
861 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
862 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
863 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
864 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
865 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
866 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
867 COH901318_CX_CTRL_TCP_DISABLE |
868 COH901318_CX_CTRL_TC_IRQ_DISABLE |
869 COH901318_CX_CTRL_HSP_ENABLE |
870 COH901318_CX_CTRL_HSS_DISABLE |
871 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
872 COH901318_CX_CTRL_PRDD_DEST,
873 .param.ctrl_lli = 0 |
874 COH901318_CX_CTRL_TC_ENABLE |
875 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
876 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
877 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
878 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
879 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
880 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
881 COH901318_CX_CTRL_TCP_DISABLE |
882 COH901318_CX_CTRL_TC_IRQ_ENABLE |
883 COH901318_CX_CTRL_HSP_ENABLE |
884 COH901318_CX_CTRL_HSS_DISABLE |
885 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
886 COH901318_CX_CTRL_PRDD_DEST,
887 .param.ctrl_lli_last = 0 |
888 COH901318_CX_CTRL_TC_ENABLE |
889 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
890 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
891 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
892 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
893 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
894 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
895 COH901318_CX_CTRL_TCP_DISABLE |
896 COH901318_CX_CTRL_TC_IRQ_ENABLE |
897 COH901318_CX_CTRL_HSP_ENABLE |
898 COH901318_CX_CTRL_HSS_DISABLE |
899 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
900 COH901318_CX_CTRL_PRDD_DEST,
901 },
902 {
903 .number = U300_DMA_MSL_RX_5,
904 .name = "MSL RX 5",
905 .priority_high = 0,
906 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
907 .param.config = COH901318_CX_CFG_CH_DISABLE |
908 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
909 COH901318_CX_CFG_LCR_DISABLE |
910 COH901318_CX_CFG_TC_IRQ_ENABLE |
911 COH901318_CX_CFG_BE_IRQ_ENABLE,
912 .param.ctrl_lli_chained = 0 |
913 COH901318_CX_CTRL_TC_ENABLE |
914 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
915 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
916 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
917 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
918 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
919 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
920 COH901318_CX_CTRL_TCP_DISABLE |
921 COH901318_CX_CTRL_TC_IRQ_DISABLE |
922 COH901318_CX_CTRL_HSP_ENABLE |
923 COH901318_CX_CTRL_HSS_DISABLE |
924 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
925 COH901318_CX_CTRL_PRDD_DEST,
926 .param.ctrl_lli = 0 |
927 COH901318_CX_CTRL_TC_ENABLE |
928 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
929 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
930 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
931 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
932 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
933 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
934 COH901318_CX_CTRL_TCP_DISABLE |
935 COH901318_CX_CTRL_TC_IRQ_ENABLE |
936 COH901318_CX_CTRL_HSP_ENABLE |
937 COH901318_CX_CTRL_HSS_DISABLE |
938 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
939 COH901318_CX_CTRL_PRDD_DEST,
940 .param.ctrl_lli_last = 0 |
941 COH901318_CX_CTRL_TC_ENABLE |
942 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
943 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
944 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
945 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
946 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
947 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
948 COH901318_CX_CTRL_TCP_DISABLE |
949 COH901318_CX_CTRL_TC_IRQ_ENABLE |
950 COH901318_CX_CTRL_HSP_ENABLE |
951 COH901318_CX_CTRL_HSS_DISABLE |
952 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
953 COH901318_CX_CTRL_PRDD_DEST,
954 },
955 {
956 .number = U300_DMA_MSL_RX_6,
957 .name = "MSL RX 6",
958 .priority_high = 0,
959 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
960 },
961 {
962 .number = U300_DMA_MMCSD_RX_TX,
963 .name = "MMCSD RX TX",
964 .priority_high = 0,
965 .dev_addr = U300_MMCSD_BASE + 0x080,
966 .param.config = COH901318_CX_CFG_CH_DISABLE |
967 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
968 COH901318_CX_CFG_LCR_DISABLE |
969 COH901318_CX_CFG_TC_IRQ_ENABLE |
970 COH901318_CX_CFG_BE_IRQ_ENABLE,
971 .param.ctrl_lli_chained = 0 |
972 COH901318_CX_CTRL_TC_ENABLE |
973 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
974 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
975 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
976 COH901318_CX_CTRL_MASTER_MODE_M1RW |
977 COH901318_CX_CTRL_TCP_DISABLE |
978 COH901318_CX_CTRL_TC_IRQ_DISABLE |
979 COH901318_CX_CTRL_HSP_ENABLE |
980 COH901318_CX_CTRL_HSS_DISABLE |
981 COH901318_CX_CTRL_DDMA_LEGACY,
982 .param.ctrl_lli = 0 |
983 COH901318_CX_CTRL_TC_ENABLE |
984 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
985 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
986 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
987 COH901318_CX_CTRL_MASTER_MODE_M1RW |
988 COH901318_CX_CTRL_TCP_ENABLE |
989 COH901318_CX_CTRL_TC_IRQ_DISABLE |
990 COH901318_CX_CTRL_HSP_ENABLE |
991 COH901318_CX_CTRL_HSS_DISABLE |
992 COH901318_CX_CTRL_DDMA_LEGACY,
993 .param.ctrl_lli_last = 0 |
994 COH901318_CX_CTRL_TC_ENABLE |
995 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
996 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
997 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
998 COH901318_CX_CTRL_MASTER_MODE_M1RW |
999 COH901318_CX_CTRL_TCP_ENABLE |
1000 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1001 COH901318_CX_CTRL_HSP_ENABLE |
1002 COH901318_CX_CTRL_HSS_DISABLE |
1003 COH901318_CX_CTRL_DDMA_LEGACY,
1004
1005 },
1006 {
1007 .number = U300_DMA_MSPRO_TX,
1008 .name = "MSPRO TX",
1009 .priority_high = 0,
1010 },
1011 {
1012 .number = U300_DMA_MSPRO_RX,
1013 .name = "MSPRO RX",
1014 .priority_high = 0,
1015 },
1016 {
1017 .number = U300_DMA_UART0_TX,
1018 .name = "UART0 TX",
1019 .priority_high = 0,
1020 },
1021 {
1022 .number = U300_DMA_UART0_RX,
1023 .name = "UART0 RX",
1024 .priority_high = 0,
1025 },
1026 {
1027 .number = U300_DMA_APEX_TX,
1028 .name = "APEX TX",
1029 .priority_high = 0,
1030 },
1031 {
1032 .number = U300_DMA_APEX_RX,
1033 .name = "APEX RX",
1034 .priority_high = 0,
1035 },
1036 {
1037 .number = U300_DMA_PCM_I2S0_TX,
1038 .name = "PCM I2S0 TX",
1039 .priority_high = 1,
1040 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1041 .param.config = COH901318_CX_CFG_CH_DISABLE |
1042 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
1043 COH901318_CX_CFG_LCR_DISABLE |
1044 COH901318_CX_CFG_TC_IRQ_ENABLE |
1045 COH901318_CX_CFG_BE_IRQ_ENABLE,
1046 .param.ctrl_lli_chained = 0 |
1047 COH901318_CX_CTRL_TC_ENABLE |
1048 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1049 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1050 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1051 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1052 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1053 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1054 COH901318_CX_CTRL_TCP_DISABLE |
1055 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1056 COH901318_CX_CTRL_HSP_ENABLE |
1057 COH901318_CX_CTRL_HSS_DISABLE |
1058 COH901318_CX_CTRL_DDMA_LEGACY |
1059 COH901318_CX_CTRL_PRDD_SOURCE,
1060 .param.ctrl_lli = 0 |
1061 COH901318_CX_CTRL_TC_ENABLE |
1062 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1063 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1064 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1065 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1066 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1067 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1068 COH901318_CX_CTRL_TCP_ENABLE |
1069 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1070 COH901318_CX_CTRL_HSP_ENABLE |
1071 COH901318_CX_CTRL_HSS_DISABLE |
1072 COH901318_CX_CTRL_DDMA_LEGACY |
1073 COH901318_CX_CTRL_PRDD_SOURCE,
1074 .param.ctrl_lli_last = 0 |
1075 COH901318_CX_CTRL_TC_ENABLE |
1076 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1077 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1078 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1079 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1080 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1081 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082 COH901318_CX_CTRL_TCP_ENABLE |
1083 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1084 COH901318_CX_CTRL_HSP_ENABLE |
1085 COH901318_CX_CTRL_HSS_DISABLE |
1086 COH901318_CX_CTRL_DDMA_LEGACY |
1087 COH901318_CX_CTRL_PRDD_SOURCE,
1088 },
1089 {
1090 .number = U300_DMA_PCM_I2S0_RX,
1091 .name = "PCM I2S0 RX",
1092 .priority_high = 1,
1093 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1094 .param.config = COH901318_CX_CFG_CH_DISABLE |
1095 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
1096 COH901318_CX_CFG_LCR_DISABLE |
1097 COH901318_CX_CFG_TC_IRQ_ENABLE |
1098 COH901318_CX_CFG_BE_IRQ_ENABLE,
1099 .param.ctrl_lli_chained = 0 |
1100 COH901318_CX_CTRL_TC_ENABLE |
1101 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1102 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1103 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1104 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1105 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1106 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1107 COH901318_CX_CTRL_TCP_DISABLE |
1108 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1109 COH901318_CX_CTRL_HSP_ENABLE |
1110 COH901318_CX_CTRL_HSS_DISABLE |
1111 COH901318_CX_CTRL_DDMA_LEGACY |
1112 COH901318_CX_CTRL_PRDD_DEST,
1113 .param.ctrl_lli = 0 |
1114 COH901318_CX_CTRL_TC_ENABLE |
1115 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1116 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1117 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1118 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1119 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1120 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1121 COH901318_CX_CTRL_TCP_ENABLE |
1122 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1123 COH901318_CX_CTRL_HSP_ENABLE |
1124 COH901318_CX_CTRL_HSS_DISABLE |
1125 COH901318_CX_CTRL_DDMA_LEGACY |
1126 COH901318_CX_CTRL_PRDD_DEST,
1127 .param.ctrl_lli_last = 0 |
1128 COH901318_CX_CTRL_TC_ENABLE |
1129 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1130 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1131 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1132 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1133 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1134 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1135 COH901318_CX_CTRL_TCP_ENABLE |
1136 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1137 COH901318_CX_CTRL_HSP_ENABLE |
1138 COH901318_CX_CTRL_HSS_DISABLE |
1139 COH901318_CX_CTRL_DDMA_LEGACY |
1140 COH901318_CX_CTRL_PRDD_DEST,
1141 },
1142 {
1143 .number = U300_DMA_PCM_I2S1_TX,
1144 .name = "PCM I2S1 TX",
1145 .priority_high = 1,
1146 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
1147 .param.config = COH901318_CX_CFG_CH_DISABLE |
1148 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
1149 COH901318_CX_CFG_LCR_DISABLE |
1150 COH901318_CX_CFG_TC_IRQ_ENABLE |
1151 COH901318_CX_CFG_BE_IRQ_ENABLE,
1152 .param.ctrl_lli_chained = 0 |
1153 COH901318_CX_CTRL_TC_ENABLE |
1154 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1155 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1156 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1157 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1158 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1159 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1160 COH901318_CX_CTRL_TCP_DISABLE |
1161 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1162 COH901318_CX_CTRL_HSP_ENABLE |
1163 COH901318_CX_CTRL_HSS_DISABLE |
1164 COH901318_CX_CTRL_DDMA_LEGACY |
1165 COH901318_CX_CTRL_PRDD_SOURCE,
1166 .param.ctrl_lli = 0 |
1167 COH901318_CX_CTRL_TC_ENABLE |
1168 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1169 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1170 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1171 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1172 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1173 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1174 COH901318_CX_CTRL_TCP_ENABLE |
1175 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1176 COH901318_CX_CTRL_HSP_ENABLE |
1177 COH901318_CX_CTRL_HSS_DISABLE |
1178 COH901318_CX_CTRL_DDMA_LEGACY |
1179 COH901318_CX_CTRL_PRDD_SOURCE,
1180 .param.ctrl_lli_last = 0 |
1181 COH901318_CX_CTRL_TC_ENABLE |
1182 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1183 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1184 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1185 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1186 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1187 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1188 COH901318_CX_CTRL_TCP_ENABLE |
1189 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1190 COH901318_CX_CTRL_HSP_ENABLE |
1191 COH901318_CX_CTRL_HSS_DISABLE |
1192 COH901318_CX_CTRL_DDMA_LEGACY |
1193 COH901318_CX_CTRL_PRDD_SOURCE,
1194 },
1195 {
1196 .number = U300_DMA_PCM_I2S1_RX,
1197 .name = "PCM I2S1 RX",
1198 .priority_high = 1,
1199 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1200 .param.config = COH901318_CX_CFG_CH_DISABLE |
1201 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
1202 COH901318_CX_CFG_LCR_DISABLE |
1203 COH901318_CX_CFG_TC_IRQ_ENABLE |
1204 COH901318_CX_CFG_BE_IRQ_ENABLE,
1205 .param.ctrl_lli_chained = 0 |
1206 COH901318_CX_CTRL_TC_ENABLE |
1207 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1208 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1209 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1210 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1211 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1212 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1213 COH901318_CX_CTRL_TCP_DISABLE |
1214 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1215 COH901318_CX_CTRL_HSP_ENABLE |
1216 COH901318_CX_CTRL_HSS_DISABLE |
1217 COH901318_CX_CTRL_DDMA_LEGACY |
1218 COH901318_CX_CTRL_PRDD_DEST,
1219 .param.ctrl_lli = 0 |
1220 COH901318_CX_CTRL_TC_ENABLE |
1221 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1222 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1223 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1224 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1225 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1226 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1227 COH901318_CX_CTRL_TCP_ENABLE |
1228 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1229 COH901318_CX_CTRL_HSP_ENABLE |
1230 COH901318_CX_CTRL_HSS_DISABLE |
1231 COH901318_CX_CTRL_DDMA_LEGACY |
1232 COH901318_CX_CTRL_PRDD_DEST,
1233 .param.ctrl_lli_last = 0 |
1234 COH901318_CX_CTRL_TC_ENABLE |
1235 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1236 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1237 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1238 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1239 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1240 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1241 COH901318_CX_CTRL_TCP_ENABLE |
1242 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1243 COH901318_CX_CTRL_HSP_ENABLE |
1244 COH901318_CX_CTRL_HSS_DISABLE |
1245 COH901318_CX_CTRL_DDMA_LEGACY |
1246 COH901318_CX_CTRL_PRDD_DEST,
1247 },
1248 {
1249 .number = U300_DMA_XGAM_CDI,
1250 .name = "XGAM CDI",
1251 .priority_high = 0,
1252 },
1253 {
1254 .number = U300_DMA_XGAM_PDI,
1255 .name = "XGAM PDI",
1256 .priority_high = 0,
1257 },
1258 {
1259 .number = U300_DMA_SPI_TX,
1260 .name = "SPI TX",
1261 .priority_high = 0,
1262 },
1263 {
1264 .number = U300_DMA_SPI_RX,
1265 .name = "SPI RX",
1266 .priority_high = 0,
1267 },
1268 {
1269 .number = U300_DMA_GENERAL_PURPOSE_0,
1270 .name = "GENERAL 00",
1271 .priority_high = 0,
1272
1273 .param.config = flags_memcpy_config,
1274 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1275 .param.ctrl_lli = flags_memcpy_lli,
1276 .param.ctrl_lli_last = flags_memcpy_lli_last,
1277 },
1278 {
1279 .number = U300_DMA_GENERAL_PURPOSE_1,
1280 .name = "GENERAL 01",
1281 .priority_high = 0,
1282
1283 .param.config = flags_memcpy_config,
1284 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1285 .param.ctrl_lli = flags_memcpy_lli,
1286 .param.ctrl_lli_last = flags_memcpy_lli_last,
1287 },
1288 {
1289 .number = U300_DMA_GENERAL_PURPOSE_2,
1290 .name = "GENERAL 02",
1291 .priority_high = 0,
1292
1293 .param.config = flags_memcpy_config,
1294 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1295 .param.ctrl_lli = flags_memcpy_lli,
1296 .param.ctrl_lli_last = flags_memcpy_lli_last,
1297 },
1298 {
1299 .number = U300_DMA_GENERAL_PURPOSE_3,
1300 .name = "GENERAL 03",
1301 .priority_high = 0,
1302
1303 .param.config = flags_memcpy_config,
1304 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1305 .param.ctrl_lli = flags_memcpy_lli,
1306 .param.ctrl_lli_last = flags_memcpy_lli_last,
1307 },
1308 {
1309 .number = U300_DMA_GENERAL_PURPOSE_4,
1310 .name = "GENERAL 04",
1311 .priority_high = 0,
1312
1313 .param.config = flags_memcpy_config,
1314 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1315 .param.ctrl_lli = flags_memcpy_lli,
1316 .param.ctrl_lli_last = flags_memcpy_lli_last,
1317 },
1318 {
1319 .number = U300_DMA_GENERAL_PURPOSE_5,
1320 .name = "GENERAL 05",
1321 .priority_high = 0,
1322
1323 .param.config = flags_memcpy_config,
1324 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1325 .param.ctrl_lli = flags_memcpy_lli,
1326 .param.ctrl_lli_last = flags_memcpy_lli_last,
1327 },
1328 {
1329 .number = U300_DMA_GENERAL_PURPOSE_6,
1330 .name = "GENERAL 06",
1331 .priority_high = 0,
1332
1333 .param.config = flags_memcpy_config,
1334 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1335 .param.ctrl_lli = flags_memcpy_lli,
1336 .param.ctrl_lli_last = flags_memcpy_lli_last,
1337 },
1338 {
1339 .number = U300_DMA_GENERAL_PURPOSE_7,
1340 .name = "GENERAL 07",
1341 .priority_high = 0,
1342
1343 .param.config = flags_memcpy_config,
1344 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1345 .param.ctrl_lli = flags_memcpy_lli,
1346 .param.ctrl_lli_last = flags_memcpy_lli_last,
1347 },
1348 {
1349 .number = U300_DMA_GENERAL_PURPOSE_8,
1350 .name = "GENERAL 08",
1351 .priority_high = 0,
1352
1353 .param.config = flags_memcpy_config,
1354 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1355 .param.ctrl_lli = flags_memcpy_lli,
1356 .param.ctrl_lli_last = flags_memcpy_lli_last,
1357 },
1358#ifdef CONFIG_MACH_U300_BS335
1359 {
1360 .number = U300_DMA_UART1_TX,
1361 .name = "UART1 TX",
1362 .priority_high = 0,
1363 },
1364 {
1365 .number = U300_DMA_UART1_RX,
1366 .name = "UART1 RX",
1367 .priority_high = 0,
1368 }
1369#else
1370 {
1371 .number = U300_DMA_GENERAL_PURPOSE_9,
1372 .name = "GENERAL 09",
1373 .priority_high = 0,
1374
1375 .param.config = flags_memcpy_config,
1376 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1377 .param.ctrl_lli = flags_memcpy_lli,
1378 .param.ctrl_lli_last = flags_memcpy_lli_last,
1379 },
1380 {
1381 .number = U300_DMA_GENERAL_PURPOSE_10,
1382 .name = "GENERAL 10",
1383 .priority_high = 0,
1384
1385 .param.config = flags_memcpy_config,
1386 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1387 .param.ctrl_lli = flags_memcpy_lli,
1388 .param.ctrl_lli_last = flags_memcpy_lli_last,
1389 }
1390#endif
1391};
1392
1393
1394static struct coh901318_platform coh901318_platform = {
1395 .chans_slave = dma_slave_channels,
1396 .chans_memcpy = dma_memcpy_channels,
1397 .access_memory_state = coh901318_access_memory_state,
1398 .chan_conf = chan_config,
1399 .max_channels = U300_DMA_CHANNELS,
1400};
1401
bb3cee2b
LW		 1402static struct platform_device wdog_device = {
1403 .name = "wdog",
1404 .id = -1,
1405 .num_resources = ARRAY_SIZE(wdog_resources),
1406 .resource = wdog_resources,
1407};
1408
1409static struct platform_device i2c0_device = {
6be2a0ca 1410 .name = "stu300",
bb3cee2b
LW		 1411 .id = 0,
1412 .num_resources = ARRAY_SIZE(i2c0_resources),
1413 .resource = i2c0_resources,
1414};
1415
1416static struct platform_device i2c1_device = {
6be2a0ca 1417 .name = "stu300",
bb3cee2b
LW		 1418 .id = 1,
1419 .num_resources = ARRAY_SIZE(i2c1_resources),
1420 .resource = i2c1_resources,
1421};
1422
1423static struct platform_device gpio_device = {
1424 .name = "u300-gpio",
1425 .id = -1,
1426 .num_resources = ARRAY_SIZE(gpio_resources),
1427 .resource = gpio_resources,
1428};
1429
1430static struct platform_device keypad_device = {
1431 .name = "keypad",
1432 .id = -1,
1433 .num_resources = ARRAY_SIZE(keypad_resources),
1434 .resource = keypad_resources,
1435};
1436
1437static struct platform_device rtc_device = {
378ce74b 1438 .name = "rtc-coh901331",
bb3cee2b
LW		 1439 .id = -1,
1440 .num_resources = ARRAY_SIZE(rtc_resources),
1441 .resource = rtc_resources,
1442};
1443
1444static struct platform_device fsmc_device = {
1445 .name = "nandif",
1446 .id = -1,
1447 .num_resources = ARRAY_SIZE(fsmc_resources),
1448 .resource = fsmc_resources,
1449};
1450
1451static struct platform_device ave_device = {
1452 .name = "video_enc",
1453 .id = -1,
1454 .num_resources = ARRAY_SIZE(ave_resources),
1455 .resource = ave_resources,
1456};
1457
08d1e2e6
LW		 1458static struct platform_device dma_device = {
1459 .name = "coh901318",
1460 .id = -1,
1461 .resource = dma_resource,
1462 .num_resources = ARRAY_SIZE(dma_resource),
1463 .dev = {
1464 .platform_data = &coh901318_platform,
1465 .coherent_dma_mask = ~0,
1466 },
1467};
1468
bb3cee2b
LW		 1469/*
1470 * Notice that AMBA devices are initialized before platform devices.
1471 *
1472 */
1473static struct platform_device *platform_devs[] __initdata = {
08d1e2e6 1474 &dma_device,
bb3cee2b
LW		 1475 &i2c0_device,
1476 &i2c1_device,
1477 &keypad_device,
1478 &rtc_device,
1479 &gpio_device,
1480 &fsmc_device,
1481 &wdog_device,
1482 &ave_device
1483};
1484
1485
1486/*
1487 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1488 * together so some interrupts are connected to the first one and some
1489 * to the second one.
1490 */
1491void __init u300_init_irq(void)
1492{
1493 u32 mask[2] = {0, 0};
1494 int i;
1495
1496 for (i = 0; i < NR_IRQS; i++)
1497 set_bit(i, (unsigned long *) &mask[0]);
1498 u300_enable_intcon_clock();
6860107a
LW		 1499 vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1500 vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
bb3cee2b
LW		 1501}
1502
1503
1504/*
1505 * U300 platforms peripheral handling
1506 */
1507struct db_chip {
1508 u16 chipid;
1509 const char *name;
1510};
1511
1512/*
1513 * This is a list of the Digital Baseband chips used in the U300 platform.
1514 */
1515static struct db_chip db_chips[] __initdata = {
1516 {
1517 .chipid = 0xb800,
1518 .name = "DB3000",
1519 },
1520 {
1521 .chipid = 0xc000,
1522 .name = "DB3100",
1523 },
1524 {
1525 .chipid = 0xc800,
1526 .name = "DB3150",
1527 },
1528 {
1529 .chipid = 0xd800,
1530 .name = "DB3200",
1531 },
1532 {
1533 .chipid = 0xe000,
1534 .name = "DB3250",
1535 },
1536 {
1537 .chipid = 0xe800,
1538 .name = "DB3210",
1539 },
1540 {
1541 .chipid = 0xf000,
1542 .name = "DB3350 P1x",
1543 },
1544 {
1545 .chipid = 0xf100,
1546 .name = "DB3350 P2x",
1547 },
1548 {
1549 .chipid = 0x0000, /* List terminator */
1550 .name = NULL,
1551 }
1552};
1553
a2bb9f4d 1554static void __init u300_init_check_chip(void)
bb3cee2b
LW		 1555{
1556
1557 u16 val;
1558 struct db_chip *chip;
1559 const char *chipname;
1560 const char unknown[] = "UNKNOWN";
1561
1562 /* Read out and print chip ID */
1563 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1564 /* This is in funky bigendian order... */
1565 val = (val & 0xFFU) << 8 | (val >> 8);
1566 chip = db_chips;
1567 chipname = unknown;
1568
1569 for ( ; chip->chipid; chip++) {
1570 if (chip->chipid == (val & 0xFF00U)) {
1571 chipname = chip->name;
1572 break;
1573 }
1574 }
1575 printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1576 "(chip ID 0x%04x)\n", chipname, val);
1577
1578#ifdef CONFIG_MACH_U300_BS26
1579 if ((val & 0xFF00U) != 0xc800) {
1580 printk(KERN_ERR "Platform configured for BS25/BS26 " \
1581 "with DB3150 but %s detected, expect problems!",
1582 chipname);
1583 }
1584#endif
1585#ifdef CONFIG_MACH_U300_BS330
1586 if ((val & 0xFF00U) != 0xd800) {
1587 printk(KERN_ERR "Platform configured for BS330 " \
1588 "with DB3200 but %s detected, expect problems!",
1589 chipname);
1590 }
1591#endif
1592#ifdef CONFIG_MACH_U300_BS335
1593 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1594 printk(KERN_ERR "Platform configured for BS365 " \
1595 " with DB3350 but %s detected, expect problems!",
1596 chipname);
1597 }
1598#endif
1599#ifdef CONFIG_MACH_U300_BS365
1600 if ((val & 0xFF00U) != 0xe800) {
1601 printk(KERN_ERR "Platform configured for BS365 " \
1602 "with DB3210 but %s detected, expect problems!",
1603 chipname);
1604 }
1605#endif
1606
1607
1608}
1609
1610/*
1611 * Some devices and their resources require reserved physical memory from
1612 * the end of the available RAM. This function traverses the list of devices
1613 * and assigns actual adresses to these.
1614 */
1615static void __init u300_assign_physmem(void)
1616{
1617 unsigned long curr_start = __pa(high_memory);
1618 int i, j;
1619
1620 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1621 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1622 struct resource *const res =
1623 &platform_devs[i]->resource[j];
1624
1625 if (IORESOURCE_MEM == res->flags &&
1626 0 == res->start) {
1627 res->start = curr_start;
1628 res->end += curr_start;
1629 curr_start += (res->end - res->start + 1);
1630
1631 printk(KERN_INFO "core.c: Mapping RAM " \
1632 "%#x-%#x to device %s:%s\n",
1633 res->start, res->end,
1634 platform_devs[i]->name, res->name);
1635 }
1636 }
1637 }
1638}
1639
1640void __init u300_init_devices(void)
1641{
1642 int i;
1643 u16 val;
1644
1645 /* Check what platform we run and print some status information */
1646 u300_init_check_chip();
1647
1648 /* Set system to run at PLL208, max performance, a known state. */
1649 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1650 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1651 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1652 /* Wait for the PLL208 to lock if not locked in yet */
1653 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1654 U300_SYSCON_CSR_PLL208_LOCK_IND));
c7c8c78f
LW		 1655 /* Initialize SPI device with some board specifics */
1656 u300_spi_init(&pl022_device);
bb3cee2b
LW		 1657
1658 /* Register the AMBA devices in the AMBA bus abstraction layer */
1659 u300_clock_primecells();
1660 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1661 struct amba_device *d = amba_devs[i];
1662 amba_device_register(d, &iomem_resource);
1663 }
1664 u300_unclock_primecells();
1665
1666 u300_assign_physmem();
1667
6be2a0ca
LW		 1668 /* Register subdevices on the I2C buses */
1669 u300_i2c_register_board_devices();
1670
c7c8c78f
LW		 1671 /* Register subdevices on the SPI bus */
1672 u300_spi_register_board_devices();
1673
bb3cee2b
LW		 1674 /* Register the platform devices */
1675 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1676
1677#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1678 /*
1679 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1680 * both subsystems are requesting this mode.
1681 * If we not share the Acc SDRAM, this is never the case. Therefore
1682 * enable it here from the App side.
1683 */
1684 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1685 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1686 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1687#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1688}
1689
1690static int core_module_init(void)
1691{
1692 /*
1693 * This needs to be initialized later: it needs the input framework
1694 * to be initialized first.
1695 */
1696 return mmc_init(&mmcsd_device);
1697}
1698module_init(core_module_init);
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