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Merge branches 'perf-fixes-for-linus' and 'x86-fixes-for-linus' of git://git.kernel...
[net-next-2.6.git] / arch / arm / mach-s5pv310 / mach-smdkv310.c
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b1d69cc6
CY		 1/* linux/arch/arm/mach-s5pv310/mach-smdkv310.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
2b11148a
HL		 12#include <linux/gpio.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
cbff3eb3
DM		 15#include <linux/smsc911x.h>
16#include <linux/io.h>
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CY		 17
18#include <asm/mach/arch.h>
19#include <asm/mach-types.h>
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CY		 20
21#include <plat/regs-serial.h>
22#include <plat/s5pv310.h>
23#include <plat/cpu.h>
cdff6e6f 24#include <plat/devs.h>
2b11148a 25#include <plat/sdhci.h>
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CY		 26
27#include <mach/map.h>
cbff3eb3 28#include <mach/regs-srom.h>
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CY		 29
30/* Following are default values for UCON, ULCON and UFCON UART registers */
31#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
32 S3C2410_UCON_RXILEVEL | \
33 S3C2410_UCON_TXIRQMODE | \
34 S3C2410_UCON_RXIRQMODE | \
35 S3C2410_UCON_RXFIFO_TOI | \
36 S3C2443_UCON_RXERR_IRQEN)
37
38#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8
39
40#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
41 S5PV210_UFCON_TXTRIG4 | \
42 S5PV210_UFCON_RXTRIG4)
43
44static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
45 [0] = {
46 .hwport = 0,
47 .flags = 0,
48 .ucon = SMDKV310_UCON_DEFAULT,
49 .ulcon = SMDKV310_ULCON_DEFAULT,
50 .ufcon = SMDKV310_UFCON_DEFAULT,
51 },
52 [1] = {
53 .hwport = 1,
54 .flags = 0,
55 .ucon = SMDKV310_UCON_DEFAULT,
56 .ulcon = SMDKV310_ULCON_DEFAULT,
57 .ufcon = SMDKV310_UFCON_DEFAULT,
58 },
59 [2] = {
60 .hwport = 2,
61 .flags = 0,
62 .ucon = SMDKV310_UCON_DEFAULT,
63 .ulcon = SMDKV310_ULCON_DEFAULT,
64 .ufcon = SMDKV310_UFCON_DEFAULT,
65 },
66 [3] = {
67 .hwport = 3,
68 .flags = 0,
69 .ucon = SMDKV310_UCON_DEFAULT,
70 .ulcon = SMDKV310_ULCON_DEFAULT,
71 .ufcon = SMDKV310_UFCON_DEFAULT,
72 },
73};
74
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HL		 75static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
76 .cd_type = S3C_SDHCI_CD_GPIO,
77 .ext_cd_gpio = S5PV310_GPK0(2),
78 .ext_cd_gpio_invert = 1,
28c80aa7 79 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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HL		 80#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
81 .max_width = 8,
82 .host_caps = MMC_CAP_8_BIT_DATA,
83#endif
84};
85
86static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
87 .cd_type = S3C_SDHCI_CD_GPIO,
88 .ext_cd_gpio = S5PV310_GPK0(2),
89 .ext_cd_gpio_invert = 1,
28c80aa7 90 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
2b11148a
HL		 91};
92
93static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_GPIO,
95 .ext_cd_gpio = S5PV310_GPK2(2),
96 .ext_cd_gpio_invert = 1,
28c80aa7 97 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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HL		 98#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
99 .max_width = 8,
100 .host_caps = MMC_CAP_8_BIT_DATA,
101#endif
102};
103
104static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
105 .cd_type = S3C_SDHCI_CD_GPIO,
106 .ext_cd_gpio = S5PV310_GPK2(2),
107 .ext_cd_gpio_invert = 1,
28c80aa7 108 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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HL		 109};
110
cbff3eb3
DM		 111static struct resource smdkv310_smsc911x_resources[] = {
112 [0] = {
113 .start = S5PV310_PA_SROM_BANK(1),
114 .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
115 .flags = IORESOURCE_MEM,
116 },
117 [1] = {
118 .start = IRQ_EINT(5),
119 .end = IRQ_EINT(5),
120 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
121 },
122};
123
124static struct smsc911x_platform_config smsc9215_config = {
125 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
126 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
127 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
128 .phy_interface = PHY_INTERFACE_MODE_MII,
129 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
130};
131
132static struct platform_device smdkv310_smsc911x = {
133 .name = "smsc911x",
134 .id = -1,
135 .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
136 .resource = smdkv310_smsc911x_resources,
137 .dev = {
138 .platform_data = &smsc9215_config,
139 },
140};
141
cdff6e6f 142static struct platform_device *smdkv310_devices[] __initdata = {
2b11148a
HL		 143 &s3c_device_hsmmc0,
144 &s3c_device_hsmmc1,
145 &s3c_device_hsmmc2,
146 &s3c_device_hsmmc3,
cdff6e6f 147 &s3c_device_rtc,
8d75c912 148 &s3c_device_wdt,
cbff3eb3 149 &smdkv310_smsc911x,
cdff6e6f
CY		 150};
151
cbff3eb3
DM		 152static void __init smdkv310_smsc911x_init(void)
153{
154 u32 cs1;
155
156 /* configure nCS1 width to 16 bits */
157 cs1 = __raw_readl(S5PV310_SROM_BW) &
158 ~(S5PV310_SROM_BW__CS_MASK <<
159 S5PV310_SROM_BW__NCS1__SHIFT);
160 cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
161 (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
162 (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
163 S5PV310_SROM_BW__NCS1__SHIFT;
164 __raw_writel(cs1, S5PV310_SROM_BW);
165
166 /* set timing for nCS1 suitable for ethernet chip */
167 __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
168 (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
169 (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
170 (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
171 (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
172 (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
173 (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
174}
175
b1d69cc6
CY		 176static void __init smdkv310_map_io(void)
177{
178 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
179 s3c24xx_init_clocks(24000000);
180 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
181}
182
183static void __init smdkv310_machine_init(void)
184{
cbff3eb3
DM		 185 smdkv310_smsc911x_init();
186
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HL		 187 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
188 s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
189 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
190 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
191
cdff6e6f 192 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
b1d69cc6
CY		 193}
194
195MACHINE_START(SMDKV310, "SMDKV310")
196 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
197 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
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CY		 198 .boot_params = S5P_PA_SDRAM + 0x100,
199 .init_irq = s5pv310_init_irq,
200 .map_io = smdkv310_map_io,
201 .init_machine = smdkv310_machine_init,
202 .timer = &s5pv310_timer,
203MACHINE_END
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