git://bbs.cooldavid.org / net-next-2.6.git / blame
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| c8bef140 CY |
1 | /* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h |
| 2 | * | |
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
| 4 | * http://www.samsung.com/ | |
| 5 | * | |
| 6 | * S5PV310 - Clock register definitions | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __ASM_ARCH_REGS_CLOCK_H | |
| 14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ | |
| 15 | ||
| 16 | #include <mach/map.h> | |
| 17 | ||
| c598c47d | 18 | #define S5P_CLKREG(x) (S5P_VA_CMU + (x)) |
| c8bef140 CY |
19 | |
| 20 | #define S5P_INFORM0 S5P_CLKREG(0x800) | |
| 21 | ||
| c598c47d KK |
22 | #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) |
| 23 | #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) | |
| 24 | #define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) | |
| 25 | #define S5P_VPLL_CON1 S5P_CLKREG(0x0C124) | |
| c8bef140 | 26 | |
| c598c47d KK |
27 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) |
| 28 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) | |
| e33ed879 KK |
29 | #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) |
| 30 | #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) | |
| 31 | #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) | |
| 32 | #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) | |
| 33 | #define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) | |
| c598c47d | 34 | #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) |
| e33ed879 | 35 | #define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) |
| c8bef140 | 36 | |
| c598c47d | 37 | #define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) |
| e33ed879 KK |
38 | #define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) |
| 39 | #define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) | |
| 40 | #define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) | |
| 41 | #define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) | |
| 42 | #define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) | |
| 43 | #define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) | |
| 44 | #define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) | |
| 45 | #define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C) | |
| c598c47d KK |
46 | #define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) |
| 47 | #define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) | |
| 48 | #define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) | |
| 49 | #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) | |
| 50 | #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) | |
| 51 | #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) | |
| c8bef140 | 52 | |
| e33ed879 KK |
53 | #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) |
| 54 | #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) | |
| 55 | #define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) | |
| 56 | #define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) | |
| 57 | #define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) | |
| 3297c2e6 | 58 | #define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) |
| e33ed879 | 59 | #define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) |
| 3297c2e6 | 60 | |
| e33ed879 KK |
61 | #define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) |
| 62 | #define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) | |
| 63 | #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) | |
| 64 | #define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) | |
| 65 | #define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) | |
| c598c47d | 66 | #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) |
| 82260bf3 | 67 | #define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) |
| c8bef140 | 68 | |
| c598c47d KK |
69 | #define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) |
| 70 | #define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500) | |
| c8bef140 | 71 | |
| c598c47d KK |
72 | #define S5P_APLL_LOCK S5P_CLKREG(0x14000) |
| 73 | #define S5P_MPLL_LOCK S5P_CLKREG(0x14004) | |
| 74 | #define S5P_APLL_CON0 S5P_CLKREG(0x14100) | |
| 75 | #define S5P_APLL_CON1 S5P_CLKREG(0x14104) | |
| 76 | #define S5P_MPLL_CON0 S5P_CLKREG(0x14108) | |
| 77 | #define S5P_MPLL_CON1 S5P_CLKREG(0x1410C) | |
| c8bef140 | 78 | |
| c598c47d KK |
79 | #define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) |
| 80 | #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) | |
| c8bef140 | 81 | |
| c598c47d KK |
82 | #define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) |
| 83 | #define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) | |
| c8bef140 | 84 | |
| c598c47d | 85 | #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) |
| c8bef140 | 86 | |
| d4b34c6c SY |
87 | /* Compatibility defines */ |
| 88 | ||
| 89 | #define S5P_EPLL_CON S5P_EPLL_CON0 | |
| 90 | ||
| c8bef140 | 91 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |