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| Commit | Line | Data |
|---|---|---|
| 2c798557 KK |
1 | /* linux/arch/arm/mach-s5pv210/include/mach/irqs.h |
| 2 | * | |
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
| 4 | * http://www.samsung.com/ | |
| 5 | * | |
| 6 | * S5PV210 - IRQ definitions | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __ASM_ARCH_IRQS_H | |
| 14 | #define __ASM_ARCH_IRQS_H __FILE__ | |
| 15 | ||
| 16 | #include <plat/irqs.h> | |
| 17 | ||
| 18 | /* VIC0: System, DMA, Timer */ | |
| 19 | ||
| 2c798557 KK |
20 | #define IRQ_EINT16_31 S5P_IRQ_VIC0(16) |
| 21 | #define IRQ_BATF S5P_IRQ_VIC0(17) | |
| 22 | #define IRQ_MDMA S5P_IRQ_VIC0(18) | |
| 23 | #define IRQ_PDMA0 S5P_IRQ_VIC0(19) | |
| 24 | #define IRQ_PDMA1 S5P_IRQ_VIC0(20) | |
| 25 | #define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21) | |
| 26 | #define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22) | |
| 27 | #define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23) | |
| 28 | #define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24) | |
| 29 | #define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25) | |
| 30 | #define IRQ_SYSTIMER S5P_IRQ_VIC0(26) | |
| 31 | #define IRQ_WDT S5P_IRQ_VIC0(27) | |
| 32 | #define IRQ_RTC_ALARM S5P_IRQ_VIC0(28) | |
| 33 | #define IRQ_RTC_TIC S5P_IRQ_VIC0(29) | |
| 34 | #define IRQ_GPIOINT S5P_IRQ_VIC0(30) | |
| 35 | #define IRQ_FIMC3 S5P_IRQ_VIC0(31) | |
| 36 | ||
| 37 | /* VIC1: ARM, Power, Memory, Connectivity, Storage */ | |
| 38 | ||
| 02a0456b | 39 | #define IRQ_PMU S5P_IRQ_VIC1(0) |
| 2c798557 KK |
40 | #define IRQ_CORTEX1 S5P_IRQ_VIC1(1) |
| 41 | #define IRQ_CORTEX2 S5P_IRQ_VIC1(2) | |
| 42 | #define IRQ_CORTEX3 S5P_IRQ_VIC1(3) | |
| 43 | #define IRQ_CORTEX4 S5P_IRQ_VIC1(4) | |
| 44 | #define IRQ_IEMAPC S5P_IRQ_VIC1(5) | |
| 45 | #define IRQ_IEMIEC S5P_IRQ_VIC1(6) | |
| 46 | #define IRQ_ONENAND S5P_IRQ_VIC1(7) | |
| 47 | #define IRQ_NFC S5P_IRQ_VIC1(8) | |
| 4b9a5ad5 | 48 | #define IRQ_CFCON S5P_IRQ_VIC1(9) |
| 2c798557 KK |
49 | #define IRQ_UART0 S5P_IRQ_VIC1(10) |
| 50 | #define IRQ_UART1 S5P_IRQ_VIC1(11) | |
| 51 | #define IRQ_UART2 S5P_IRQ_VIC1(12) | |
| 52 | #define IRQ_UART3 S5P_IRQ_VIC1(13) | |
| 53 | #define IRQ_IIC S5P_IRQ_VIC1(14) | |
| 54 | #define IRQ_SPI0 S5P_IRQ_VIC1(15) | |
| 55 | #define IRQ_SPI1 S5P_IRQ_VIC1(16) | |
| 56 | #define IRQ_SPI2 S5P_IRQ_VIC1(17) | |
| 57 | #define IRQ_IRDA S5P_IRQ_VIC1(18) | |
| 023c75c7 KP |
58 | #define IRQ_IIC2 S5P_IRQ_VIC1(19) |
| 59 | #define IRQ_IIC3 S5P_IRQ_VIC1(20) | |
| 2c798557 KK |
60 | #define IRQ_HSIRX S5P_IRQ_VIC1(21) |
| 61 | #define IRQ_HSITX S5P_IRQ_VIC1(22) | |
| 62 | #define IRQ_UHOST S5P_IRQ_VIC1(23) | |
| 63 | #define IRQ_OTG S5P_IRQ_VIC1(24) | |
| 64 | #define IRQ_MSM S5P_IRQ_VIC1(25) | |
| 65 | #define IRQ_HSMMC0 S5P_IRQ_VIC1(26) | |
| 66 | #define IRQ_HSMMC1 S5P_IRQ_VIC1(27) | |
| 67 | #define IRQ_HSMMC2 S5P_IRQ_VIC1(28) | |
| 68 | #define IRQ_MIPICSI S5P_IRQ_VIC1(29) | |
| 69 | #define IRQ_MIPIDSI S5P_IRQ_VIC1(30) | |
| 70 | #define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31) | |
| 71 | ||
| 72 | /* VIC2: Multimedia, Audio, Security */ | |
| 73 | ||
| 74 | #define IRQ_LCD0 S5P_IRQ_VIC2(0) | |
| 75 | #define IRQ_LCD1 S5P_IRQ_VIC2(1) | |
| 76 | #define IRQ_LCD2 S5P_IRQ_VIC2(2) | |
| 77 | #define IRQ_LCD3 S5P_IRQ_VIC2(3) | |
| 78 | #define IRQ_ROTATOR S5P_IRQ_VIC2(4) | |
| 79 | #define IRQ_FIMC0 S5P_IRQ_VIC2(5) | |
| 80 | #define IRQ_FIMC1 S5P_IRQ_VIC2(6) | |
| 81 | #define IRQ_FIMC2 S5P_IRQ_VIC2(7) | |
| 82 | #define IRQ_JPEG S5P_IRQ_VIC2(8) | |
| 83 | #define IRQ_2D S5P_IRQ_VIC2(9) | |
| 84 | #define IRQ_3D S5P_IRQ_VIC2(10) | |
| 85 | #define IRQ_MIXER S5P_IRQ_VIC2(11) | |
| 86 | #define IRQ_HDMI S5P_IRQ_VIC2(12) | |
| 87 | #define IRQ_IIC1 S5P_IRQ_VIC2(13) | |
| 88 | #define IRQ_MFC S5P_IRQ_VIC2(14) | |
| 89 | #define IRQ_TVENC S5P_IRQ_VIC2(15) | |
| 90 | #define IRQ_I2S0 S5P_IRQ_VIC2(16) | |
| 91 | #define IRQ_I2S1 S5P_IRQ_VIC2(17) | |
| 92 | #define IRQ_I2S2 S5P_IRQ_VIC2(18) | |
| 93 | #define IRQ_AC97 S5P_IRQ_VIC2(19) | |
| 94 | #define IRQ_PCM0 S5P_IRQ_VIC2(20) | |
| 95 | #define IRQ_PCM1 S5P_IRQ_VIC2(21) | |
| 96 | #define IRQ_SPDIF S5P_IRQ_VIC2(22) | |
| 97 | #define IRQ_ADC S5P_IRQ_VIC2(23) | |
| 98 | #define IRQ_PENDN S5P_IRQ_VIC2(24) | |
| 99 | #define IRQ_TC IRQ_PENDN | |
| 100 | #define IRQ_KEYPAD S5P_IRQ_VIC2(25) | |
| 101 | #define IRQ_CG S5P_IRQ_VIC2(26) | |
| 102 | #define IRQ_SEC S5P_IRQ_VIC2(27) | |
| 103 | #define IRQ_SECRX S5P_IRQ_VIC2(28) | |
| 104 | #define IRQ_SECTX S5P_IRQ_VIC2(29) | |
| 105 | #define IRQ_SDMIRQ S5P_IRQ_VIC2(30) | |
| 106 | #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) | |
| 107 | ||
| 108 | /* VIC3: Etc */ | |
| 109 | ||
| 110 | #define IRQ_IPC S5P_IRQ_VIC3(0) | |
| 111 | #define IRQ_HOSTIF S5P_IRQ_VIC3(1) | |
| eda9c023 | 112 | #define IRQ_HSMMC3 S5P_IRQ_VIC3(2) |
| 2c798557 KK |
113 | #define IRQ_CEC S5P_IRQ_VIC3(3) |
| 114 | #define IRQ_TSI S5P_IRQ_VIC3(4) | |
| 115 | #define IRQ_MDNIE0 S5P_IRQ_VIC3(5) | |
| 116 | #define IRQ_MDNIE1 S5P_IRQ_VIC3(6) | |
| 117 | #define IRQ_MDNIE2 S5P_IRQ_VIC3(7) | |
| 118 | #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) | |
| 119 | #define IRQ_VIC_END S5P_IRQ_VIC3(31) | |
| 120 | ||
| 5fae4058 PB |
121 | #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) |
| 122 | #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) | |
| 2c798557 | 123 | |
| 5fdc97b5 MS |
124 | /* GPIO interrupt */ |
| 125 | #define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1) | |
| 126 | #define S5P_GPIOINT_GROUP_MAXNR 22 | |
| 127 | ||
| 2c798557 | 128 | /* Set the default NR_IRQS */ |
| 5fdc97b5 | 129 | #define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1) |
| 0df04f82 | 130 | |
| 5b696a67 MS |
131 | /* Compatibility */ |
| 132 | #define IRQ_LCD_FIFO IRQ_LCD0 | |
| 133 | #define IRQ_LCD_VSYNC IRQ_LCD1 | |
| 134 | #define IRQ_LCD_SYSTEM IRQ_LCD2 | |
| 135 | ||
| 2c798557 | 136 | #endif /* ASM_ARCH_IRQS_H */ |