[net-next-2.6.git] / arch / arm / mach-s5pv210 / clock.c

/* linux/arch/arm/mach-s5pv210/clock.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * S5PV210 - Clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>

#include <mach/map.h>

#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5pv210.h>

static struct clksrc_clk clk_mout_apll = {
	.clk	= {
		.name		= "mout_apll",
		.id		= -1,
	},
	.sources	= &clk_src_apll,
	.reg_src	= { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
};

static struct clksrc_clk clk_mout_epll = {
	.clk	= {
		.name		= "mout_epll",
		.id		= -1,
	},
	.sources	= &clk_src_epll,
	.reg_src	= { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
};

static struct clksrc_clk clk_mout_mpll = {
	.clk = {
		.name		= "mout_mpll",
		.id		= -1,
	},
	.sources	= &clk_src_mpll,
	.reg_src	= { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
};

static struct clk *clkset_armclk_list[] = {
	[0] = &clk_mout_apll.clk,
	[1] = &clk_mout_mpll.clk,
};

static struct clksrc_sources clkset_armclk = {
	.sources	= clkset_armclk_list,
	.nr_sources	= ARRAY_SIZE(clkset_armclk_list),
};

static struct clksrc_clk clk_armclk = {
	.clk	= {
		.name		= "armclk",
		.id		= -1,
	},
	.sources	= &clkset_armclk,
	.reg_src	= { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
	.reg_div	= { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
};

static struct clksrc_clk clk_hclk_msys = {
	.clk	= {
		.name		= "hclk_msys",
		.id		= -1,
		.parent		= &clk_armclk.clk,
	},
	.reg_div	= { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
};

static struct clksrc_clk clk_sclk_a2m = {
	.clk	= {
		.name		= "sclk_a2m",
		.id		= -1,
		.parent		= &clk_mout_apll.clk,
	},
	.reg_div	= { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
};

static struct clk *clkset_hclk_sys_list[] = {
	[0] = &clk_mout_mpll.clk,
	[1] = &clk_sclk_a2m.clk,
};

static struct clksrc_sources clkset_hclk_sys = {
	.sources	= clkset_hclk_sys_list,
	.nr_sources	= ARRAY_SIZE(clkset_hclk_sys_list),
};

static struct clksrc_clk clk_hclk_dsys = {
	.clk	= {
		.name	= "hclk_dsys",
		.id	= -1,
	},
	.sources	= &clkset_hclk_sys,
	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
	.reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
};

static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
}

static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
}

static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
}

static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
}

static struct clk clk_h100 = {
	.name		= "hclk100",
	.id		= -1,
};

static struct clk clk_h133 = {
	.name		= "hclk133",
	.id		= -1,
};

static struct clk clk_p100 = {
	.name		= "pclk100",
	.id		= -1,
};

static struct clk clk_p83 = {
	.name		= "pclk83",
	.id		= -1,
};

static struct clk clk_p66 = {
	.name		= "pclk66",
	.id		= -1,
};

static struct clk *sys_clks[] = {
	&clk_h100,
	&clk_h133,
	&clk_p100,
	&clk_p83,
	&clk_p66
};

static struct clk init_clocks_disable[] = {
	{
		.name		= "rot",
		.id		= -1,
		.parent		= &clk_hclk_dsys.clk,
		.enable		= s5pv210_clk_ip0_ctrl,
		.ctrlbit	= (1<<29),
	}, {
		.name		= "otg",
		.id		= -1,
		.parent		= &clk_h133,
		.enable		= s5pv210_clk_ip1_ctrl,
		.ctrlbit	= (1<<16),
	}, {
		.name		= "usb-host",
		.id		= -1,
		.parent		= &clk_h133,
		.enable		= s5pv210_clk_ip1_ctrl,
		.ctrlbit	= (1<<17),
	}, {
		.name		= "lcd",
		.id		= -1,
		.parent		= &clk_hclk_dsys.clk,
		.enable		= s5pv210_clk_ip1_ctrl,
		.ctrlbit	= (1<<0),
	}, {
		.name		= "cfcon",
		.id		= 0,
		.parent		= &clk_h133,
		.enable		= s5pv210_clk_ip1_ctrl,
		.ctrlbit	= (1<<25),
	}, {
		.name		= "hsmmc",
		.id		= 0,
		.parent		= &clk_h133,
		.enable		= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<16),
	}, {
		.name		= "hsmmc",
		.id		= 1,
		.parent		= &clk_h133,
		.enable		= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<17),
	}, {
		.name		= "hsmmc",
		.id		= 2,
		.parent		= &clk_h133,
		.enable		= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<18),
	}, {
		.name		= "hsmmc",
		.id		= 3,
		.parent		= &clk_h133,
		.enable		= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<19),
	}, {
		.name		= "systimer",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<16),
	}, {
		.name		= "watchdog",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<22),
	}, {
		.name		= "rtc",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<15),
	}, {
		.name		= "i2c",
		.id		= 0,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<7),
	}, {
		.name		= "i2c",
		.id		= 1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<8),
	}, {
		.name		= "i2c",
		.id		= 2,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<9),
	}, {
		.name		= "spi",
		.id		= 0,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<12),
	}, {
		.name		= "spi",
		.id		= 1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<13),
	}, {
		.name		= "spi",
		.id		= 2,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<14),
	}, {
		.name		= "timers",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<23),
	}, {
		.name		= "adc",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<24),
	}, {
		.name		= "keypad",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<21),
	}, {
		.name		= "i2s_v50",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<4),
	}, {
		.name		= "i2s_v32",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<4),
	}, {
		.name		= "i2s_v32",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<4),
	}
};

static struct clk init_clocks[] = {
	{
		.name		= "uart",
		.id		= 0,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<7),
	}, {
		.name		= "uart",
		.id		= 1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<8),
	}, {
		.name		= "uart",
		.id		= 2,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<9),
	}, {
		.name		= "uart",
		.id		= 3,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<10),
	},
};

static struct clk *clkset_uart_list[] = {
	[6] = &clk_mout_mpll.clk,
	[7] = &clk_mout_epll.clk,
};

static struct clksrc_sources clkset_uart = {
	.sources	= clkset_uart_list,
	.nr_sources	= ARRAY_SIZE(clkset_uart_list),
};

static struct clksrc_clk clksrcs[] = {
	{
		.clk	= {
			.name		= "uclk1",
			.id		= -1,
			.ctrlbit	= (1<<17),
			.enable		= s5pv210_clk_ip3_ctrl,
		},
		.sources = &clkset_uart,
		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
		.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
	}
};

/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
	&clk_mout_apll,
	&clk_mout_epll,
	&clk_mout_mpll,
	&clk_armclk,
	&clk_hclk_msys,
	&clk_sclk_a2m,
	&clk_hclk_dsys,
};

#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)

void __init_or_cpufreq s5pv210_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long xtal;
	unsigned long armclk;
	unsigned long hclk_msys;
	unsigned long hclk_dsys;
	unsigned long hclk133;
	unsigned long pclk100;
	unsigned long pclk83;
	unsigned long pclk66;
	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned int ptr;
	u32 clkdiv0, clkdiv1;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	clkdiv0 = __raw_readl(S5P_CLK_DIV0);
	clkdiv1 = __raw_readl(S5P_CLK_DIV1);

	printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
				__func__, clkdiv0, clkdiv1);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
	epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);

	clk_fout_apll.rate = apll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;

	printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
			apll, mpll, epll);

	armclk = clk_get_rate(&clk_armclk.clk);
	hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
	hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);

	if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) {
		hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
		hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
	} else
		hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);

	pclk100 = hclk_msys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
	pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
	pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);

	printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
			HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
	       armclk, hclk_msys, hclk_dsys, hclk133, pclk100, pclk83, pclk66);

	clk_f.rate = armclk;
	clk_h.rate = hclk133;
	clk_p.rate = pclk66;
	clk_p66.rate = pclk66;
	clk_p83.rate = pclk83;
	clk_h133.rate = hclk133;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}

static struct clk *clks[] __initdata = {
};

void __init s5pv210_register_clocks(void)
{
	struct clk *clkp;
	int ret;
	int ptr;

	ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
	if (ret > 0)
		printk(KERN_ERR "Failed to register %u clocks\n", ret);

	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
		s3c_register_clksrc(sysclks[ptr], 1);

	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

	ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
	if (ret > 0)
		printk(KERN_ERR "Failed to register system clocks\n");

	clkp = init_clocks_disable;
	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}
		(clkp->enable)(clkp, 0);
	}

	s3c_pwmclk_init();
}
Commit	Line	Data
0c1945d3 KK	1	/* linux/arch/arm/mach-s5pv210/clock.c
	2	*
	3	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com/
	5	*
	6	* S5PV210 - Clock support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/list.h>
	17	#include <linux/errno.h>
	18	#include <linux/err.h>
	19	#include <linux/clk.h>
	20	#include <linux/sysdev.h>
	21	#include <linux/io.h>
	22
	23	#include <mach/map.h>
	24
	25	#include <plat/cpu-freq.h>
	26	#include <mach/regs-clock.h>
	27	#include <plat/clock.h>
	28	#include <plat/cpu.h>
	29	#include <plat/pll.h>
	30	#include <plat/s5p-clock.h>
	31	#include <plat/clock-clksrc.h>
	32	#include <plat/s5pv210.h>
	33
59cda520 TA	34	static struct clksrc_clk clk_mout_apll = {
	35	.clk = {
	36	.name = "mout_apll",
	37	.id = -1,
	38	},
	39	.sources = &clk_src_apll,
	40	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
	41	};
	42
	43	static struct clksrc_clk clk_mout_epll = {
	44	.clk = {
	45	.name = "mout_epll",
	46	.id = -1,
	47	},
	48	.sources = &clk_src_epll,
	49	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
	50	};
	51
	52	static struct clksrc_clk clk_mout_mpll = {
	53	.clk = {
	54	.name = "mout_mpll",
	55	.id = -1,
	56	},
	57	.sources = &clk_src_mpll,
	58	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
	59	};
	60
374e0bf5 TA	61	static struct clk *clkset_armclk_list[] = {
	62	[0] = &clk_mout_apll.clk,
	63	[1] = &clk_mout_mpll.clk,
	64	};
	65
	66	static struct clksrc_sources clkset_armclk = {
	67	.sources = clkset_armclk_list,
	68	.nr_sources = ARRAY_SIZE(clkset_armclk_list),
	69	};
	70
	71	static struct clksrc_clk clk_armclk = {
	72	.clk = {
	73	.name = "armclk",
	74	.id = -1,
	75	},
	76	.sources = &clkset_armclk,
	77	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
	78	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
	79	};
	80
af76a201 TA	81	static struct clksrc_clk clk_hclk_msys = {
	82	.clk = {
	83	.name = "hclk_msys",
	84	.id = -1,
	85	.parent = &clk_armclk.clk,
	86	},
	87	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
	88	};
	89
0fe967a1 TA	90	static struct clksrc_clk clk_sclk_a2m = {
	91	.clk = {
	92	.name = "sclk_a2m",
	93	.id = -1,
	94	.parent = &clk_mout_apll.clk,
	95	},
	96	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
	97	};
	98
	99	static struct clk *clkset_hclk_sys_list[] = {
	100	[0] = &clk_mout_mpll.clk,
	101	[1] = &clk_sclk_a2m.clk,
	102	};
	103
	104	static struct clksrc_sources clkset_hclk_sys = {
	105	.sources = clkset_hclk_sys_list,
	106	.nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
	107	};
	108
	109	static struct clksrc_clk clk_hclk_dsys = {
	110	.clk = {
	111	.name = "hclk_dsys",
	112	.id = -1,
	113	},
	114	.sources = &clkset_hclk_sys,
	115	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
	116	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
	117	};
	118
0c1945d3 KK	119	static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
	120	{
	121	return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
	122	}
	123
	124	static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
	125	{
	126	return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
	127	}
	128
	129	static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
	130	{
	131	return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
	132	}
	133
	134	static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
	135	{
	136	return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
	137	}
	138
0c1945d3 KK	139	static struct clk clk_h100 = {
	140	.name = "hclk100",
	141	.id = -1,
	142	};
	143
0c1945d3 KK	144	static struct clk clk_h133 = {
	145	.name = "hclk133",
	146	.id = -1,
	147	};
	148
	149	static struct clk clk_p100 = {
	150	.name = "pclk100",
	151	.id = -1,
	152	};
	153
	154	static struct clk clk_p83 = {
	155	.name = "pclk83",
	156	.id = -1,
	157	};
	158
	159	static struct clk clk_p66 = {
	160	.name = "pclk66",
	161	.id = -1,
	162	};
	163
	164	static struct clk *sys_clks[] = {
0c1945d3	165	&clk_h100,
0c1945d3 KK	166	&clk_h133,
	167	&clk_p100,
	168	&clk_p83,
	169	&clk_p66
	170	};
	171
	172	static struct clk init_clocks_disable[] = {
	173	{
	174	.name = "rot",
	175	.id = -1,
0fe967a1	176	.parent = &clk_hclk_dsys.clk,
0c1945d3 KK	177	.enable = s5pv210_clk_ip0_ctrl,
	178	.ctrlbit = (1<<29),
	179	}, {
	180	.name = "otg",
	181	.id = -1,
	182	.parent = &clk_h133,
	183	.enable = s5pv210_clk_ip1_ctrl,
	184	.ctrlbit = (1<<16),
	185	}, {
	186	.name = "usb-host",
	187	.id = -1,
	188	.parent = &clk_h133,
	189	.enable = s5pv210_clk_ip1_ctrl,
	190	.ctrlbit = (1<<17),
	191	}, {
	192	.name = "lcd",
	193	.id = -1,
0fe967a1	194	.parent = &clk_hclk_dsys.clk,
0c1945d3 KK	195	.enable = s5pv210_clk_ip1_ctrl,
	196	.ctrlbit = (1<<0),
	197	}, {
	198	.name = "cfcon",
	199	.id = 0,
	200	.parent = &clk_h133,
	201	.enable = s5pv210_clk_ip1_ctrl,
	202	.ctrlbit = (1<<25),
	203	}, {
	204	.name = "hsmmc",
	205	.id = 0,
	206	.parent = &clk_h133,
	207	.enable = s5pv210_clk_ip2_ctrl,
	208	.ctrlbit = (1<<16),
	209	}, {
	210	.name = "hsmmc",
	211	.id = 1,
	212	.parent = &clk_h133,
	213	.enable = s5pv210_clk_ip2_ctrl,
	214	.ctrlbit = (1<<17),
	215	}, {
	216	.name = "hsmmc",
	217	.id = 2,
	218	.parent = &clk_h133,
	219	.enable = s5pv210_clk_ip2_ctrl,
	220	.ctrlbit = (1<<18),
	221	}, {
	222	.name = "hsmmc",
	223	.id = 3,
	224	.parent = &clk_h133,
	225	.enable = s5pv210_clk_ip2_ctrl,
	226	.ctrlbit = (1<<19),
	227	}, {
	228	.name = "systimer",
	229	.id = -1,
	230	.parent = &clk_p66,
	231	.enable = s5pv210_clk_ip3_ctrl,
	232	.ctrlbit = (1<<16),
	233	}, {
	234	.name = "watchdog",
	235	.id = -1,
	236	.parent = &clk_p66,
	237	.enable = s5pv210_clk_ip3_ctrl,
	238	.ctrlbit = (1<<22),
	239	}, {
	240	.name = "rtc",
	241	.id = -1,
	242	.parent = &clk_p66,
	243	.enable = s5pv210_clk_ip3_ctrl,
	244	.ctrlbit = (1<<15),
	245	}, {
	246	.name = "i2c",
	247	.id = 0,
	248	.parent = &clk_p66,
	249	.enable = s5pv210_clk_ip3_ctrl,
	250	.ctrlbit = (1<<7),
	251	}, {
	252	.name = "i2c",
	253	.id = 1,
	254	.parent = &clk_p66,
	255	.enable = s5pv210_clk_ip3_ctrl,
	256	.ctrlbit = (1<<8),
	257	}, {
	258	.name = "i2c",
259	.id = 2,
260	.parent = &clk_p66,
261	.enable = s5pv210_clk_ip3_ctrl,
262	.ctrlbit = (1<<9),
263	}, {
264	.name = "spi",
265	.id = 0,
266	.parent = &clk_p66,
267	.enable = s5pv210_clk_ip3_ctrl,
268	.ctrlbit = (1<<12),
269	}, {
270	.name = "spi",
271	.id = 1,
272	.parent = &clk_p66,
273	.enable = s5pv210_clk_ip3_ctrl,
274	.ctrlbit = (1<<13),
275	}, {
276	.name = "spi",
277	.id = 2,
278	.parent = &clk_p66,
279	.enable = s5pv210_clk_ip3_ctrl,
280	.ctrlbit = (1<<14),
281	}, {
282	.name = "timers",
283	.id = -1,
284	.parent = &clk_p66,
285	.enable = s5pv210_clk_ip3_ctrl,
286	.ctrlbit = (1<<23),
287	}, {
288	.name = "adc",
289	.id = -1,
290	.parent = &clk_p66,
291	.enable = s5pv210_clk_ip3_ctrl,
292	.ctrlbit = (1<<24),
293	}, {
294	.name = "keypad",
295	.id = -1,
296	.parent = &clk_p66,
297	.enable = s5pv210_clk_ip3_ctrl,
298	.ctrlbit = (1<<21),
299	}, {
300	.name = "i2s_v50",
301	.id = 0,
302	.parent = &clk_p,
303	.enable = s5pv210_clk_ip3_ctrl,
304	.ctrlbit = (1<<4),
305	}, {
306	.name = "i2s_v32",
307	.id = 0,
308	.parent = &clk_p,
309	.enable = s5pv210_clk_ip3_ctrl,
310	.ctrlbit = (1<<4),
311	}, {
312	.name = "i2s_v32",
313	.id = 1,
314	.parent = &clk_p,
315	.enable = s5pv210_clk_ip3_ctrl,
316	.ctrlbit = (1<<4),
317	}
318	};
319
320	static struct clk init_clocks[] = {
321	{
322	.name = "uart",
323	.id = 0,
324	.parent = &clk_p66,
325	.enable = s5pv210_clk_ip3_ctrl,
326	.ctrlbit = (1<<7),
327	}, {
328	.name = "uart",
329	.id = 1,
330	.parent = &clk_p66,
331	.enable = s5pv210_clk_ip3_ctrl,
332	.ctrlbit = (1<<8),
333	}, {
334	.name = "uart",
335	.id = 2,
336	.parent = &clk_p66,
337	.enable = s5pv210_clk_ip3_ctrl,
338	.ctrlbit = (1<<9),
339	}, {
340	.name = "uart",
341	.id = 3,
342	.parent = &clk_p66,
343	.enable = s5pv210_clk_ip3_ctrl,
344	.ctrlbit = (1<<10),
345	},
346	};
347
0c1945d3 KK	348	static struct clk *clkset_uart_list[] = {
	349	[6] = &clk_mout_mpll.clk,
	350	[7] = &clk_mout_epll.clk,
	351	};
	352
	353	static struct clksrc_sources clkset_uart = {
	354	.sources = clkset_uart_list,
	355	.nr_sources = ARRAY_SIZE(clkset_uart_list),
	356	};
	357
	358	static struct clksrc_clk clksrcs[] = {
	359	{
	360	.clk = {
	361	.name = "uclk1",
	362	.id = -1,
	363	.ctrlbit = (1<<17),
	364	.enable = s5pv210_clk_ip3_ctrl,
	365	},
	366	.sources = &clkset_uart,
	367	.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
	368	.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
	369	}
	370	};
	371
	372	/* Clock initialisation code */
eb1ef1ed	373	static struct clksrc_clk *sysclks[] = {
0c1945d3 KK	374	&clk_mout_apll,
	375	&clk_mout_epll,
	376	&clk_mout_mpll,
374e0bf5	377	&clk_armclk,
af76a201	378	&clk_hclk_msys,
0fe967a1 TA	379	&clk_sclk_a2m,
0fe967a1 TA	380	&clk_hclk_dsys,
0c1945d3 KK	381	};
	382
	383	#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
	384
	385	void __init_or_cpufreq s5pv210_setup_clocks(void)
	386	{
	387	struct clk *xtal_clk;
	388	unsigned long xtal;
	389	unsigned long armclk;
af76a201	390	unsigned long hclk_msys;
0fe967a1	391	unsigned long hclk_dsys;
0c1945d3 KK	392	unsigned long hclk133;
	393	unsigned long pclk100;
	394	unsigned long pclk83;
	395	unsigned long pclk66;
	396	unsigned long apll;
	397	unsigned long mpll;
	398	unsigned long epll;
	399	unsigned int ptr;
	400	u32 clkdiv0, clkdiv1;
	401
	402	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
	403
	404	clkdiv0 = __raw_readl(S5P_CLK_DIV0);
	405	clkdiv1 = __raw_readl(S5P_CLK_DIV1);
	406
	407	printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
	408	__func__, clkdiv0, clkdiv1);
	409
	410	xtal_clk = clk_get(NULL, "xtal");
	411	BUG_ON(IS_ERR(xtal_clk));
	412
	413	xtal = clk_get_rate(xtal_clk);
	414	clk_put(xtal_clk);
	415
	416	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
	417
	418	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
	419	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
	420	epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
	421
c62ec6a9 TA	422	clk_fout_apll.rate = apll;
	423	clk_fout_mpll.rate = mpll;
	424	clk_fout_epll.rate = epll;
	425
0c1945d3 KK	426	printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
	427	apll, mpll, epll);
	428
374e0bf5	429	armclk = clk_get_rate(&clk_armclk.clk);
af76a201	430	hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
0fe967a1	431	hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
0c1945d3 KK	432
	433	if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) {
	434	hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
	435	hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
	436	} else
	437	hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
	438
af76a201	439	pclk100 = hclk_msys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
0fe967a1	440	pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
0c1945d3 KK	441	pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
	442
	443	printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
	444	HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
0fe967a1	445	armclk, hclk_msys, hclk_dsys, hclk133, pclk100, pclk83, pclk66);
0c1945d3	446
0c1945d3 KK	447	clk_f.rate = armclk;
	448	clk_h.rate = hclk133;
	449	clk_p.rate = pclk66;
	450	clk_p66.rate = pclk66;
	451	clk_p83.rate = pclk83;
	452	clk_h133.rate = hclk133;
0c1945d3	453
0c1945d3 KK	454	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
	455	s3c_set_clksrc(&clksrcs[ptr], true);
	456	}
	457
	458	static struct clk *clks[] __initdata = {
0c1945d3 KK	459	};
	460
	461	void __init s5pv210_register_clocks(void)
	462	{
	463	struct clk *clkp;
	464	int ret;
	465	int ptr;
	466
	467	ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
	468	if (ret > 0)
	469	printk(KERN_ERR "Failed to register %u clocks\n", ret);
	470
eb1ef1ed TA	471	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
	472	s3c_register_clksrc(sysclks[ptr], 1);
	473
0c1945d3 KK	474	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	475	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
	476
	477	ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
	478	if (ret > 0)
	479	printk(KERN_ERR "Failed to register system clocks\n");
	480
	481	clkp = init_clocks_disable;
	482	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
	483	ret = s3c24xx_register_clock(clkp);
	484	if (ret < 0) {
	485	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	486	clkp->name, ret);
	487	}
	488	(clkp->enable)(clkp, 0);
	489	}
	490
	491	s3c_pwmclk_init();
	492	}