git://bbs.cooldavid.org / net-next-2.6.git / blame
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|---|---|---|
| ff54b457 BM |
1 | /* linux/arch/arm/mach-s5pc100/include/mach/map.h |
| 2 | * | |
| 3 | * Copyright 2009 Samsung Electronics Co. | |
| 4 | * Byungho Min <bhmin@samsung.com> | |
| 5 | * | |
| acc84707 | 6 | * S5PC100 - Memory map definitions |
| ff54b457 BM |
7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __ASM_ARCH_MAP_H | |
| 14 | #define __ASM_ARCH_MAP_H __FILE__ | |
| 15 | ||
| 16 | #include <plat/map-base.h> | |
| acc84707 | 17 | #include <plat/map-s5p.h> |
| ff54b457 | 18 | |
| b0cc3031 KP |
19 | /* |
| 20 | * map-base.h has already defined virtual memory address | |
| 21 | * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s) | |
| 22 | * S3C_VA_SYS S3C_ADDR(0x00100000) system control | |
| 23 | * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used) | |
| 24 | * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block | |
| 25 | * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog | |
| 26 | * S3C_VA_UART S3C_ADDR(0x01000000) UART | |
| 27 | * | |
| 28 | * S5PC100 specific virtual memory address can be defined here | |
| 29 | * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO | |
| 30 | * | |
| 31 | */ | |
| ff54b457 | 32 | |
| 999304be MS |
33 | #define S5PC100_PA_ONENAND_BUF (0xB0000000) |
| 34 | #define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M) | |
| 35 | ||
| ff54b457 | 36 | /* Chip ID */ |
| 206a1a82 | 37 | |
| ff54b457 | 38 | #define S5PC100_PA_CHIPID (0xE0000000) |
| acc84707 MS |
39 | #define S5P_PA_CHIPID S5PC100_PA_CHIPID |
| 40 | ||
| 41 | #define S5PC100_PA_SYSCON (0xE0100000) | |
| 42 | #define S5P_PA_SYSCON S5PC100_PA_SYSCON | |
| 43 | ||
| 44 | #define S5PC100_PA_OTHERS (0xE0200000) | |
| 45 | #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) | |
| 46 | ||
| 19a2c065 | 47 | #define S5PC100_PA_GPIO (0xE0300000) |
| b0cc3031 | 48 | #define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) |
| ff54b457 BM |
49 | |
| 50 | /* Interrupt */ | |
| 19a2c065 KK |
51 | #define S5PC100_PA_VIC0 (0xE4000000) |
| 52 | #define S5PC100_PA_VIC1 (0xE4100000) | |
| 53 | #define S5PC100_PA_VIC2 (0xE4200000) | |
| ff54b457 | 54 | #define S5PC100_VA_VIC S3C_VA_IRQ |
| ff54b457 | 55 | #define S5PC100_VA_VIC_OFFSET 0x10000 |
| ff54b457 | 56 | #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) |
| 45c79433 | 57 | |
| b0cc3031 | 58 | |
| 999304be | 59 | #define S5PC100_PA_ONENAND (0xE7100000) |
| ff54b457 | 60 | |
| 66194a74 AK |
61 | #define S5PC100_PA_CFCON (0xE7800000) |
| 62 | ||
| b0cc3031 KP |
63 | /* DMA */ |
| 64 | #define S5PC100_PA_MDMA (0xE8100000) | |
| 65 | #define S5PC100_PA_PDMA0 (0xE9000000) | |
| 66 | #define S5PC100_PA_PDMA1 (0xE9200000) | |
| b0cc3031 | 67 | |
| ff54b457 | 68 | /* Timer */ |
| acc84707 MS |
69 | #define S5PC100_PA_TIMER (0xEA000000) |
| 70 | #define S5P_PA_TIMER S5PC100_PA_TIMER | |
| b0cc3031 | 71 | |
| acc84707 | 72 | #define S5PC100_PA_SYSTIMER (0xEA100000) |
| b0cc3031 | 73 | |
| c4023617 | 74 | #define S5PC100_PA_WATCHDOG (0xEA200000) |
| fa9ce742 | 75 | #define S5PC100_PA_RTC (0xEA300000) |
| c4023617 | 76 | |
| acc84707 | 77 | #define S5PC100_PA_UART (0xEC000000) |
| b0cc3031 | 78 | |
| acc84707 MS |
79 | #define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) |
| 80 | #define S5P_PA_UART1 (S5PC100_PA_UART + 0x400) | |
| 81 | #define S5P_PA_UART2 (S5PC100_PA_UART + 0x800) | |
| 82 | #define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00) | |
| 83 | #define S5P_SZ_UART SZ_256 | |
| b0cc3031 | 84 | |
| acc84707 MS |
85 | #define S5PC100_PA_IIC0 (0xEC100000) |
| 86 | #define S5PC100_PA_IIC1 (0xEC200000) | |
| b0cc3031 | 87 | |
| 7c3943f6 JB |
88 | /* SPI */ |
| 89 | #define S5PC100_PA_SPI0 0xEC300000 | |
| 90 | #define S5PC100_PA_SPI1 0xEC400000 | |
| 91 | #define S5PC100_PA_SPI2 0xEC500000 | |
| 92 | ||
| b0cc3031 KP |
93 | /* USB HS OTG */ |
| 94 | #define S5PC100_PA_USB_HSOTG (0xED200000) | |
| 95 | #define S5PC100_PA_USB_HSPHY (0xED300000) | |
| 96 | ||
| acc84707 | 97 | #define S5PC100_PA_FB (0xEE000000) |
| b0cc3031 | 98 | |
| 33c14ff8 SN |
99 | #define S5PC100_PA_FIMC0 (0xEE200000) |
| 100 | #define S5PC100_PA_FIMC1 (0xEE300000) | |
| 101 | #define S5PC100_PA_FIMC2 (0xEE400000) | |
| 102 | ||
| 45c79433 BD |
103 | #define S5PC100_PA_I2S0 (0xF2000000) |
| 104 | #define S5PC100_PA_I2S1 (0xF2100000) | |
| 105 | #define S5PC100_PA_I2S2 (0xF2200000) | |
| 106 | ||
| 9e4ed5c3 JB |
107 | #define S5PC100_PA_AC97 0xF2300000 |
| 108 | ||
| 109 | /* PCM */ | |
| 110 | #define S5PC100_PA_PCM0 0xF2400000 | |
| 111 | #define S5PC100_PA_PCM1 0xF2500000 | |
| 112 | ||
| 068b432d SY |
113 | #define S5PC100_PA_SPDIF 0xF2600000 |
| 114 | ||
| 327b9030 NKC |
115 | #define S5PC100_PA_TSADC (0xF3000000) |
| 116 | ||
| b0cc3031 KP |
117 | /* KEYPAD */ |
| 118 | #define S5PC100_PA_KEYPAD (0xF3100000) | |
| 119 | ||
| acc84707 | 120 | #define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) |
| ff54b457 | 121 | |
| ff54b457 | 122 | #define S5PC100_PA_SDRAM (0x20000000) |
| acc84707 | 123 | #define S5P_PA_SDRAM S5PC100_PA_SDRAM |
| ff54b457 | 124 | |
| acc84707 | 125 | /* compatibiltiy defines. */ |
| ff54b457 | 126 | #define S3C_PA_UART S5PC100_PA_UART |
| acc84707 MS |
127 | #define S3C_PA_IIC S5PC100_PA_IIC0 |
| 128 | #define S3C_PA_IIC1 S5PC100_PA_IIC1 | |
| b0cc3031 KP |
129 | #define S3C_PA_FB S5PC100_PA_FB |
| 130 | #define S3C_PA_G2D S5PC100_PA_G2D | |
| 131 | #define S3C_PA_G3D S5PC100_PA_G3D | |
| 132 | #define S3C_PA_JPEG S5PC100_PA_JPEG | |
| 133 | #define S3C_PA_ROTATOR S5PC100_PA_ROTATOR | |
| 45c79433 BD |
134 | #define S5P_VA_VIC0 S5PC1XX_VA_VIC(0) |
| 135 | #define S5P_VA_VIC1 S5PC1XX_VA_VIC(1) | |
| 136 | #define S5P_VA_VIC2 S5PC1XX_VA_VIC(2) | |
| b0cc3031 KP |
137 | #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG |
| 138 | #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY | |
| 45c79433 BD |
139 | #define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) |
| 140 | #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) | |
| 141 | #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) | |
| b0cc3031 | 142 | #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD |
| c4023617 | 143 | #define S3C_PA_WDT S5PC100_PA_WATCHDOG |
| 2211f28c | 144 | #define S3C_PA_TSADC S5PC100_PA_TSADC |
| 999304be MS |
145 | #define S3C_PA_ONENAND S5PC100_PA_ONENAND |
| 146 | #define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF | |
| 147 | #define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF | |
| fa9ce742 | 148 | #define S3C_PA_RTC S5PC100_PA_RTC |
| ff54b457 | 149 | |
| 327b9030 | 150 | #define SAMSUNG_PA_ADC S5PC100_PA_TSADC |
| 66194a74 | 151 | #define SAMSUNG_PA_CFCON S5PC100_PA_CFCON |
| 2211f28c | 152 | #define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD |
| 66194a74 | 153 | |
| 33c14ff8 SN |
154 | #define S5P_PA_FIMC0 S5PC100_PA_FIMC0 |
| 155 | #define S5P_PA_FIMC1 S5PC100_PA_FIMC1 | |
| 156 | #define S5P_PA_FIMC2 S5PC100_PA_FIMC2 | |
| 157 | ||
| ff54b457 | 158 | #endif /* __ASM_ARCH_C100_MAP_H */ |